EL5211T [INTERSIL]
60MHz Rail-to-Rail Input-Output Operational Amplifier; 60MHz的轨至轨输入输出运算放大器
| 型号： | EL5211T |
| 厂家： | 
Intersil |
| 描述： | 60MHz Rail-to-Rail Input-Output Operational Amplifier |
| 文件： | 总15页 (文件大小：397K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
60MHz Rail-to-Rail Input-Output Operational Amplifier
EL5211T
Features
• 60MHz (-3dB) Bandwidth
The EL5211T is a high voltage rail-to-rail input-output
amplifier with low power consumption. The EL5211T
contains two amplifiers. Each amplifier exhibits beyond
the rail input capability, rail-to-rail output capability and
is unity gain stable.
• 4.5V to 19V Maximum Supply Voltage Range
• 100V/μs Slew Rate
• 3mA Supply Current (per Amplifier)
• ±65mA Continuous Output Current
• ±300mA Output Short Circuit Current
• Unity-gain Stable
The maximum operating voltage range is from 4.5V to
19V. It can be configured for single or dual supply
operation, and typically consumes only 3mA per
amplifier. The EL5211T has an output short circuit
capability of ±300mA and a continuous output current
capability of ±65mA.
• Beyond the Rails Input Capability
• Rail-to-rail Output Swing
• Built-in Thermal Protection
The EL5211T features a high slew rate of 100V/μs, and
fast settling time. Also, the device provides common
mode input capability beyond the supply rails, rail-to-rail
output capability, and a bandwidth of 60MHz (-3dB). This
enables the amplifiers to offer maximum dynamic range
at any supply voltage. These features make the EL5211T
an ideal amplifier solution for use in TFT-LCD panels as a
• -40°C to +85°C Ambient Temperature Range
• Pb-Free (RoHS Compliant)
Applications*(see page 13)
• TFT-LCD Panels
• V
Amplifiers
COM
V
driver or static gamma buffer, and in high speed
COM
• Static Gamma Buffers
• Drivers for A/D Converters
• Data Acquisition
filtering and signal conditioning applications. Other
applications include battery power and portable devices,
especially where low power consumption is important.
The EL5211T is available in a thermally enhanced 8 Ld
HMSOP package, and a thermally enhanced 8 Ld DFN
package. Both feature a standard operational amplifier
pinout. The device operates over an ambient
temperature range of -40°C to +85°C.
• Video Processing
• Audio Processing
• Active Filters
• Test Equipment
• Battery-powered Applications
• Portable Equipment
10
V
A
C
= ±5V
S
V
8
6
= 1
= 1.5pF
|| 1kΩ (PROBE)
L
R
L
4
1kΩ
2
0
-2
-4
-6
-8
-10
560Ω
150Ω
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 1. TYPICAL TFT-LCD V
APPLICATION
FIGURE 2. FREQUENCY RESPONSE FOR VARIOUS R
L
COM
May 12, 2010
FN6893.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
EL5211T
Pin Configuration
EL5211T
EL5211T
(8 LD DFN)
TOP VIEW
(8 LD HMSOP)
TOP VIEW
VOUTA 1
8 VS+
VOUTA
VS+
1
2
3
4
8
7
6
5
VINA- 2
VINA+ 3
VS- 4
-
+
7 VOUTB
6 VINB-
5 VINB+
VINA-
VINA+
VS-
VOUTB
VINB-
VINB+
PD
-
+
THERMAL PAD IS ELECTRICALLY
CONNECTED TO VS-
THERMAL PAD IS ELECTRICALLY
CONNECTED TO VS-
Pin Descriptions
PIN NUMBER
PIN
(HMSOP, DFN)
NAME
FUNCTION
EQUIVALENT CIRCUIT
1
2
VOUTA
VINA-
VINA+
VS-
Amplifier A output
(Reference Circuit 1)
(Reference Circuit 2)
(Reference Circuit 2)
Amplifier A inverting input
Amplifier A non-inverting input
Negative power supply
3
4
5
VINB+
VINB-
VOUTB
VS+
Amplifier B non-inverting input
Amplifier B inverting input
Amplifier B output
(Reference Circuit 2)
(Reference Circuit 2)
(Reference Circuit 1)
6
7
8
Positive power supply
Pad
PD
Functions as a heat sink. Electrically connected to
VS-. Connect the thermal pad to VS- plane on the
PCB for optimum thermal performance.
V
V
S+
V
V
S+
V
OUTx
V
INx
S-
GND
S-
CIRCUIT 1
CIRCUIT 2
Ordering Information
PART NUMBER
(Notes 2, 3)
PART
MARKING
PACKAGE
(Pb-Free)
PKG.
DWG. #
EL5211TILZ-T13 (Note 1)
EL5211TIYEZ
11T
8 Ld DFN
L8.2x3
BBBNA
BBBNA
BBBNA
8 Ld HMSOP
8 Ld HMSOP
8 Ld HMSOP
MDP0050
MDP0050
MDP0050
EL5211TIYEZ-T7 (Note 1)
EL5211TIYEZ-T13 (Note 1)
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for EL5211T. For more information on MSL please see
techbrief TB363.
FN6893.0
May 12, 2010
2
EL5211T
Absolute Maximum Ratings (T = +25°C)
Thermal Information
A
Supply Voltage between V + and V -. . . . . . . . . . . .+19.8V
Thermal Resistance (Typical)
θ (°C/W) θ (°C/W)
JA JC
S
S
Input Voltage Range (V ) . . . V - - 0.5V, V + + 0.5V
, V
INx+ INx- S S
8 Ld HMSOP (Notes 4, 5) . . . . . . .
8 Ld DFN (Notes 4, 5). . . . . . . . . .
62
58
13
8
Input Differential Voltage (V
- V
) . . . . . . . . . . . . . .
INx-
INx+
. . . . . . . . . . . . . . . . . . . . . . . (V + + 0.5V)-(V - - 0.5V)
S
S
Storage Temperature . . . . . . . . . . . . . . . -65°C to +150°C
Ambient Operating Temperature. . . . . . . . . -40°C to +85°C
Maximum Junction Temperature . . . . . . . . . . . . . . . +150°C
Power Dissipation . . . . . . . . . . . . . . .See Figures 34 and 35
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Maximum Continuous Output Current . . . . . . . . . . .±65mA
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . 3000V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
JA
features. See Tech Brief TB379.
5. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T = T = T
A
J
C
Electrical Specifications V + = +5V, V - = -5V, R = 1kΩ to 0V, T = +25°C, Unless Otherwise Specified.
S
S
L
A
PARAMETER
DESCRIPTION
CONDITIONS
MIN TYP MAX UNIT
INPUT CHARACTERISTICS
Input Offset Voltage
V
V
= 0V
5
13
9
18
60
mV
μV/°C
μV/°C
nA
OS
CM
TCV
Average Offset Voltage Drift (Note 6)
8 Ld HMSOP package
8 Ld DFN package
OS
I
Input Bias Current
V
= 0V
2
B
CM
R
Input Impedance
1
GΩ
IN
IN
C
Input Capacitance
2
pF
CMIR
Common-Mode Input Range
Common-Mode Rejection Ratio
Open-Loop Gain
-5.5
50
+5.5
V
CMRR
For V from -5.5V to 5.5V
IN
73
78
dB
A
-4.5V ≤ V
≤ 4.5V
OUTx
62
dB
VOL
OUTPUT CHARACTERISTICS
V
V
Output Swing Low
Output Swing High
Short-Circuit Current
I = -5mA
-4.95 -4.85
V
V
OL
OH
SC
L
I = +5mA
4.85 4.95
±300
L
I
V
= 0V, Source: V
OUTx
short to V -,
mA
CM
Sink: V
S
short to V +
OUTx
S
I
Output Current
±65
mA
OUT
POWER SUPPLY PERFORMANCE
(V +) - (V -) Supply Voltage Range
4.5
5.5
19
V
S
S
I
Supply Current
V
= 0V, No load
7.5
mA
dB
S
CM
PSRR
Power Supply Rejection Ratio
Supply is moved from ±2.25V to ±9.5V
60
75
DYNAMIC PERFORMANCE
SR Slew Rate (Note 7)
-4.0V ≤ V
≤ 4.0V, 20% to 80%
100
85
V/μs
OUTx
t
Settling to +0.1% (Note 8)
A = +1, V
= 2V step,
ns
S
V
OUTx
R = 1kΩ || 1kΩ (probe), C = 1.5pF
L
L
BW
-3dB Bandwidth
R = 1kΩ, C = 1.5pF
60
MHz
L
L
FN6893.0
May 12, 2010
3
EL5211T
Electrical Specifications V + = +5V, V - = -5V, R = 1kΩ to 0V, T = +25°C, Unless Otherwise Specified. (Continued)
S
S
L
A
PARAMETER
DESCRIPTION
CONDITIONS
MIN TYP MAX UNIT
GBWP
Gain-Bandwidth Product
A = -10, R = 1kΩ, R = 100Ω
32
50
90
MHz
V
F
G
R = 1kΩ || 1kΩ (probe), C = 1.5pF
L
L
PM
CS
Phase Margin
A = -10, R = 1kΩ, R = 100Ω
V F G
°
R = 1kΩ || 1kΩ (probe), C = 1.5pF
L
L
Channel Separation
f = 5MHz
dB
Electrical Specifications V + = +5V, V - = 0V, R = 1kΩ to 2.5V, T = +25°C, Unless Otherwise Specified.
S
S
L
A
PARAMETER
DESCRIPTION
CONDITION
MIN TYP MAX UNIT
INPUT CHARACTERISTICS
Input Offset Voltage
V
V
= 2.5V
5
11
8
18
60
mV
μV/°C
μV/°C
nA
OS
CM
TCV
Average Offset Voltage Drift (Note 6)
8 Ld HMSOP package
8 Ld DFN package
OS
I
Input Bias Current
V
= 2.5V
2
B
CM
R
Input Impedance
1
GΩ
IN
IN
C
Input Capacitance
2
pF
CMIR
Common-Mode Input Range
Common-Mode Rejection Ratio
Open-Loop Gain
-0.5
45
+5.5
V
CMRR
For V from -0.5V to 5.5V
IN
68
82
dB
A
0.5V ≤ V
≤ 4.5V
OUTx
62
dB
VOL
OUTPUT CHARACTERISTICS
V
V
Output Swing Low
Output Swing High
Short-circuit Current
I = -4.2mA
60
150
mV
V
OL
OH
SC
L
I = +4.2mA
4.85 4.94
±110
L
I
V
= 2.5V, Source: V
short to V -,
mA
CM
Sink: V
OUTx
short to V +
S
OUTx
S
I
Output Current
±65
mA
OUT
POWER SUPPLY PERFORMANCE
(V +) - (V -) Supply Voltage Range
4.5
6.0
19
V
S
S
I
Supply Current
V
= 2.5V, No load
7.5
mA
dB
S
CM
PSRR
Power Supply Rejection Ratio
Supply is moved from 4.5V to 19V
60
75
DYNAMIC PERFORMANCE
SR Slew Rate (Note 7)
1V ≤ V
≤ 4V, 20% to 80%
75
90
V/μs
OUTx
t
Settling to +0.1% (Note 8)
A = +1, V
= 2V step,
ns
S
V
OUTx
R = 1kΩ || 1kΩ (probe), C = 1.5pF
L
L
BW
-3dB Bandwidth
R = 1kΩ, C = 1.5pF
60
32
MHz
MHz
L
L
GBWP
Gain-Bandwidth Product
A = -10, R = 1kΩ, R = 100Ω
V F G
R = 1kΩ || 1kΩ (probe), C = 1.5pF
L
L
PM
CS
Phase Margin
A = -10, R = 1kΩ, R = 100Ω
50
90
°
V
F
G
R = 1kΩ || 1kΩ (probe), C = 1.5pF
L
L
Channel Separation
f = 5MHz
dB
FN6893.0
May 12, 2010
4
EL5211T
Electrical Specifications V + = +18V, V - = 0V, R = 1kΩ to 9V, T = +25°C, Unless Otherwise Specified.
S
S
L
A
PARAMETER
DESCRIPTION
CONDITION
MIN
TYP MAX UNIT
INPUT CHARACTERISTICS
Input Offset Voltage
V
V
= 9V
7
14
11
2
18
60
mV
μV/°C
μV/°C
nA
OS
CM
TCV
Average Offset Voltage Drift (Note 6) 8 Ld HMSOP package
8 Ld DFN package
OS
I
Input Bias Current
V
= 9V
B
CM
R
Input Impedance
1
GΩ
IN
IN
C
Input Capacitance
2
pF
CMIR
Common-Mode Input Range
Common-Mode Rejection Ratio
Open-Loop Gain
-0.5
53
+18.5
V
CMRR
For V from -0.5V to 18.5V
IN
75
dB
A
0.5V ≤ V
≤ 17.5V
OUTx
62
104
dB
VOL
OUTPUT CHARACTERISTICS
V
V
Output Swing Low
Output Swing High
Short-circuit Current
I = -6mA
80
150
mV
V
OL
OH
SC
L
I = +6mA
17.85 17.92
±300
L
I
V
= 9V, Source: V
OUTx
short to V -,
mA
CM
Sink: V
S
short to V +
OUTx
S
I
Output Current
±65
mA
OUT
POWER SUPPLY PERFORMANCE
(V +) - (V -) Supply Voltage Range
4.5
6.0
19
V
S
S
I
Supply Current
V
= 9V, No load
7.5
mA
dB
S
CM
PSRR
Power Supply Rejection Ratio
Supply is moved from 4.5V to 19V
60
75
DYNAMIC PERFORMANCE
SR Slew Rate (Note 7)
1V ≤ V
≤ 17V, 20% to 80%
100
100
V/μs
OUTx
t
Settling to +0.1% (Note 8)
A = +1, V
= 2V step,
ns
S
V
OUTx
R = 1kΩ || 1kΩ (probe), C = 1.5pF
L
L
BW
-3dB Bandwidth
R = 1kΩ, C = 1.5pF
60
32
MHz
MHz
L
L
GBWP
Gain-Bandwidth Product
A = -10, R = 1kΩ, R = 100Ω
V F G
R = 1kΩ || 1kΩ (probe), C = 1.5pF
L
L
PM
Phase Margin
A = -10, R = 1kΩ, R = 100Ω
50
90
°
V
F
G
R = 1kΩ || 1kΩ (probe), C = 1.5pF
L
L
CS
Channel Separation
f = 5MHz
dB
NOTES:
6. Measured over -40°C to +85°C ambient operating temperature range. See the typical TCV
the “Typical Performance Curves” on page 6.
production distribution shown in
OS
7. Typical slew rate is an average of the slew rates measured on the rising (20% to 80%) and the falling (80% to 20%) edges
of the output signal.
8. Settling time measured as the time from when the output level crosses the final value on rising/falling edge to when the output
level settles within a ±0.1% error band. The range of the error band is determined by: Final Value(V)±[Full Scale(V)*0.1%].
FN6893.0
May 12, 2010
5
EL5211T
Typical Performance Curves
450
10
9
8
7
6
5
4
3
2
1
0
TYPICAL
V
= ±5V
V
= ±5V
S
S
A
400
350
300
250
200
150
100
50
PRODUCTION
-40°C to +85°C
T
= +25°C
DISTRIBUTION
TYPICAL
PRODUCTION
DISTRIBUTION
0
2
6
10 14 18 22 26 30 34 38
INPUT OFFSET VOLTAGE DRIFT (|μV|/°C)
-12-10 -8 -6 -4 -2
0
2
4
6
8
10 12
INPUT OFFSET VOLTAGE (mV)
FIGURE 3. INPUT OFFSET VOLTAGE DISTRIBUTION
FIGURE 4. INPUT OFFSET VOLTAGE DRIFT (HMSOP)
12
10
V
= ±5V
S
V
= ±5V
S
-40°C to +85°C
10
8
TYPICAL
PRODUCTION
DISTRIBUTION
5
0
6
4
-5
2
0
-10
2
6
10 14 18 22 26 30 34 38
-50
0
50
100
150
INPUT OFFSET VOLTAGE DRIFT (|μV|/°C)
TEMPERATURE (°C)
FIGURE 5. INPUT OFFSET VOLTAGE DRIFT (DFN)
FIGURE 6. INPUT OFFSET VOLTAGE vs TEMPERATURE
4
4.95
V
OUT
= ±5V
V
= ±5V
S
S
I
= +5mA
3
2
1
0
4.94
4.93
4.92
-50
0
50
100
150
-50
0
50
TEMPERATURE (°C)
100
150
TEMPERATURE (°C)
FIGURE 7. INPUT BIAS CURRENT vs TEMPERATURE
FIGURE 8. OUTPUT HIGH VOLTAGE vs TEMPERATURE
FN6893.0
May 12, 2010
6
EL5211T
Typical Performance Curves(Continued)
-4.92
V
OUT
= ±5V
S
V
R
= ±5V
= 1kΩ
S
L
I
= -5mA
100
80
-4.93
-4.94
-4.95
-4.96
-4.97
60
40
-50
-50
0
50
TEMPERATURE (°C)
100
150
0
50
100
150
TEMPERATURE (°C)
FIGURE 9. OUTPUT LOW VOLTAGE vs TEMPERATURE
FIGURE 10. OPEN-LOOP GAIN vs TEMPERATURE
160
2.95
V
R
= ±5V
= 1kΩ
S
L
V
= ±5V
S
NO LOAD
2.90
2.85
2.80
2.75
2.70
140
120
100
80
INPUT AT GND
60
-50
-50
0
50
TEMPERATURE (°C)
100
150
0
50
100
150
TEMPERATURE (°C)
FIGURE 12. SUPPLY CURRENT PER AMPLIFIER vs
TEMPERATURE
FIGURE 11. SLEW RATE vs TEMPERATURE
4.0
3.5
3.0
2.5
2.0
140
120
100
80
T
= +25°C
A
NO LOAD
INPUT AT GND
T
= +25°C
A
A
R
= 1
V
L
L
60
40
= 1kΩ
= 8pF
C
2
4
6
8
10
2.5
3.5
4.5
5.5
6.5
7.5
8.5
9.5
SUPPLY VOLTAGE (±V)
SUPPLY VOLTAGE (±V)
FIGURE 14. SLEW RATE vs SUPPLY VOLTAGE
FIGURE 13. SUPPLY CURRENT PER AMPLIFIER vs
SUPPLY VOLTAGE
FN6893.0
May 12, 2010
7
EL5211T
Typical Performance Curves(Continued)
140
120
100
80
100
200
160
120
80
T
= +25°C
= 1kΩ
A
L
R
80
60
40
20
0
GAIN
PHASE
V
R
R
= ±5V
40
S
F
L
L
= 5kΩ, R = 100Ω
G
= 1kΩ
60
0
C
= 8pF
40
-20
-40
2
4
6
8
10
10
100
1k
10k 100k 1M
FREQUENCY (Hz)
10M 100M
SUPPLY VOLTAGE (±V)
FIGURE 15. OPEN LOOP GAIN vs SUPPLY VOLTAGE
FIGURE 16. OPEN LOOP GAIN AND PHASE
100
80
60
40
20
0
200
160
120
80
10
8
V
A
C
= ±5V
S
V
PHASE
= 1
= 1.5pF
|| 1kΩ (PROBE)
6
L
R
L
4
GAIN
1kΩ
2
0
-2
-4
-6
-8
-10
V
R
R
= ±5V
40
S
F
L
560Ω
= 1kΩ, R = 100Ω
G
= 1kΩ || 1kΩ
0
150Ω
(PROBE)
C
= 1.5pF
L
-20
-40
10
100
1k
10k 100k 1M
FREQUENCY (Hz)
10M 100M
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 17. OPEN LOOP GAIN AND PHASE
FIGURE 18. FREQUENCY RESPONSE FOR VARIOUS R
L
20
1000
V
R
R
= ±5V
= 2kΩ
= 50Ω
S
F
L
15
10
5
1000pF
100pF
SOURCE = 0dBm
100
10
1
47pF
10pF
0
-5
-10
-15
-20
V
A
R
= ±5V
= 1
= 1kΩ
S
V
L
0.1
1k
10k
100k
1M
10M
100M
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 19. FREQUENCY RESPONSE FOR VARIOUS C
FIGURE 20. CLOSED LOOP OUTPUT IMPEDANCE
L
FN6893.0
May 12, 2010
8
EL5211T
Typical Performance Curves(Continued)
12
10
8
-30
-40
-50
-60
-70
-80
-90
2nd HD
3rd HD
6
4
V
A
R
= ±5V
= 2
= 1kΩ
= 1MHz
S
V
L
V
A
R
= ±5V
= 1
S
V
L
2
= 1kΩ
f
IN
DISTORTION <1%
0
0
2
4
6
8
10
10k
100k
1M
10M
100M
OUTPUT VOLTAGE (V
)
FREQUENCY (Hz)
OP-P
FIGURE 21. MAXIMUM OUTPUT SWING vs FREQUENCY
FIGURE 22. HARMONIC DISTORTION vs V
OP-P
0
0
V
T
= ±5V
V
T
= ±5V
S
A
S
A
-10
-20
-30
-40
-50
-60
-70
-80
-90
-10
-20
-30
-40
-50
-60
-70
-80
= +25°C
= +25°C
V
= -10dBm
INx
PSRR+
PSRR-
100k
1k
10k
100k
1E+06 1E+07 1E+08
1k
10k
1E+06 1E+07 1E+08
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 23. CMRR
FIGURE 24. PSRR
1000
100
10
-20
-40
V
= ±5V
T
= +25°C
S
V
A
A
V
= 1
= 0dBm
INx
-60
-80
-100
-120
1
100
1k
10k
100k
1M
10M
100M
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 25. INPUT VOLTAGE NOISE SPECTRAL
DENSITY
FIGURE 26. CHANNEL SEPARATION
FN6893.0
May 12, 2010
9
EL5211T
Typical Performance Curves(Continued)
100
5
4
V
T
= ±5V
= +25°C
= 1
V
T
= ±5V
= +25°C
= 1
S
S
A
A
A
A
V
V
L
80
60
40
20
0
3
R = 1kΩ || 1kΩ
R
V
= 1kΩ
L
(PROBE)
= ±50mV
2
INx
C
=1.5pF
L
1
0
-1
-2
-3
-4
-5
10
100
LOAD CAPACITANCE (pF)
1k
70
80
90
SETTLING TIME (ns)
FIGURE 28. STEP SIZE vs SETTLING TIME
FIGURE 27. SMALL-SIGNAL OVERSHOOT vs LOAD
CAPACITANCE
V
T
= ±5V
= +25°C
= 1
V
T
= ±5V
= +25°C
= 1
S
S
A
A
A
A
V
100mV STEP
V
R = 1kΩ|| 1kΩ
R = 1kΩ || 1kΩ
L
L
(PROBE)
(PROBE)
6V STEP
C
= 1.5pF
C
= 1.5pF
L
L
50ns/DIV
50ns/DIV
FIGURE 29. LARGE SIGNAL TRANSIENT RESPONSE
FIGURE 30. SMALL SIGNAL TRANSIENT RESPONSE
FIGURE 31. BASIC TEST CIRCUIT
FN6893.0
May 12, 2010
10
EL5211T
Applications Information
V
= ±2.5V, T = +25°C, A = 1, V
INx
= 6V R = 1kΩ to GND
P-P, L
S
A
V
Product Description
The EL5211T is a high voltage rail-to-rail input-output
amplifier with low power consumption. The EL5211T
contains four amplifiers. Each amplifier exhibits beyond
the rail input capability, rail-to-rail output capability and
is unity gain stable.
OUTPUT
The EL5211T features a high slew rate of 100V/μs, and
fast settling time. Also, the device provides common
mode input capability beyond the supply rails, rail-to-rail
output capability, and a bandwidth of 60MHz (-3dB). This
enables the amplifiers to offer maximum dynamic range
at any supply voltage.
INPUT
10μs/DIV
FIGURE 32. OPERATION WITH BEYOND-THE-RAILS
INPUT
Operating Voltage, Input and Output
Capability
V
= ±5V, T = +25°C, A = 1, V
= 10V R = 1kΩ to GND
P-P, L
S
A
V
INx
The EL5211T can operate on a single supply or dual
supply configuration. The EL5211T operating voltage
ranges from a minimum of 4.5V to a maximum of 19V.
This range allows for a standard 5V (or ±2.5V) supply
voltage to dip to -10%, or a standard 18V (or ±9V) to
rise by +5.5% without affecting performance or
reliability.
The input common-mode voltage range of the EL5211T
extends 500mV beyond the supply rails. Also, the
EL5211T is immune to phase reversal. However, if the
common mode input voltage exceeds the supply voltage
by more than 0.5V, electrostatic protection diodes in the
input stage of the device begin to conduct. Even though
phase reversal will not occur, to maintain optimal
reliability it is suggested to avoid input overvoltage
conditions. Figure 32 shows the input voltage driven
500mV beyond the supply rails and the device output
swinging between the supply rails.
10μs/DIV
FIGURE 33. OPERATION WITH RAIL-TO-RAIL INPUT
AND OUTPUT
To maintain maximum reliability, the continuous output
current should never exceed ±65mA. This ±65mA limit is
determined by the characteristics of the internal metal
interconnects. Also, see “Power Dissipation” on page 12
for detailed information on ensuring proper device
operation and reliability for temperature and load
conditions.
The EL5211T output typically swings to within 50mV of
positive and negative supply rails with load currents of
±5mA. Decreasing load currents will extend the output
voltage range even closer to the supply rails. Figure 33
shows the input and output waveforms for the device in a
unity-gain configuration. Operation is from ±5V supply
Unused Amplifiers
It is recommended that any unused amplifiers be
configured as a unity gain follower. The inverting input
should be directly connected to the output and the
non-inverting input tied to the ground.
with a 1kΩ load connected to GND. The input is a 10V
P-P
sinusoid and the output voltage is approximately 9.9V
.
P-P
Refer to the “Electrical Specifications” Table beginning on
page 3 for specific device parameters. Parameter
variations with operating voltage, loading and/or
temperature are shown in the “Typical Performance
Curves” on page 6.
Thermal Shutdown
The EL5211T has a built-in thermal protection which
ensures safe operation and prevents internal damage to
the device due to overheating. When the die temperature
reaches +165°C (typical), the device automatically shuts
OFF the outputs by putting them in a high impedance
state. When the die cools by +15°C (typical), the device
automatically turns ON the outputs by putting them in a
low impedance (normal) operating state.
Output Current
The EL5211T is capable of output short circuit currents of
300mA (source and sink), and the device has built-in
protection circuitry which limits the output current to
±300mA (typical).
FN6893.0
May 12, 2010
11
EL5211T
• V - = Negative supply voltage
Driving Capacitive Loads
S
As load capacitance increases, the -3dB bandwidth will
decrease and peaking can occur. Depending on the
application, it may be necessary to reduce peaking and
to improve device stability. To improve device stability a
snubber circuit or a series resistor may be added to the
output of the EL5211T.
• I
= Maximum supply current per amplifier
SMAX
(I
= EL5211T quiescent current ÷ 2)
SMAX
• V
• I
= Output voltage
= Load current
OUT
LOAD
Device overheating can be avoided by calculating the
A snubber is a shunt load consisting of a resistor in series
with a capacitor. An optimized snubber can improve the
phase margin and the stability of the EL5211T. The
advantage of a snubber circuit is that it does not draw
any DC load current or reduce the gain.
minimum resistive load condition, R
the highest power dissipation. To find R
, resulting in
set the two
LOAD
LOAD
P
V
equations equal to each other and solve for
DMAX
/I
. Reference the package power dissipation
OUT LOAD
curves, Figures 34 and 35, for further information.
Another method to reduce peaking is to add a series
output resistor (typically between 1Ω to 10Ω). Depending
on the capacitive loading, a small value resistor may be
the most appropriate choice to minimize any reduction in
gain.
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1.0
781mW
0.8
DFN8
Power Dissipation
θ
= +160°C/W
694mW
JA
0.6
0.4
0.2
0.0
With the high-output drive capability of the EL5211T
amplifiers, it is possible to exceed the +150°C absolute
maximum junction temperature under certain load
current conditions. It is important to calculate the
maximum power dissipation of the EL5211T in the
application. Proper load conditions will ensure that the
EL5211T junction temperature stays within a safe
operating region.
HMSOP8
θ
= +180°C/W
JA
85
0
25
50
75
100
125
150
AMBIENT TEMPERATURE (°C)
The maximum power dissipation allowed in a package is
determined according to Equation 1:
FIGURE 34. PACKAGE POWER DISSIPATION vs
AMBIENT TEMPERATURE
T
– T
AMAX
θ
JMAX
(EQ. 1)
P
= --------------------------------------------
DMAX
JA
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY (4-LAYER) TEST BOARD - EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
where:
• T
= Maximum junction temperature
= Maximum ambient temperature
JMAX
AMAX
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0.0
• T
2.16W
• Θ = Thermal resistance of the package
JA
DFN8
= +58°C/W
θ
JA
2.02W
• P
= Maximum power dissipation allowed
DMAX
The total power dissipation produced by an IC is the total
quiescent supply current times the total power supply
voltage, plus the power dissipation in the IC due to the
loads, or:
HMSOP8
θ
= +62°C/W
JA
(EQ. 2)
P
= Σi[V × I
+ (V + – V
i) × I
i]
LOAD
DMAX
S
SMAX
S
OUT
85
0
25
50
75
100
125
150
when sourcing, and:
AMBIENT TEMPERATURE (°C)
P
= Σi[V × I
+ (V
i – V -) × I
i]
LOAD
(EQ. 3)
DMAX
S
SMAX
OUT
S
FIGURE 35. PACKAGE POWER DISSIPATION vs
AMBIENT TEMPERATURE
when sinking,
where:
Power Supply Bypassing and Printed Circuit
Board Layout
The EL5211T can provide gain at high frequency, so good
printed circuit board layout is necessary for optimum
performance. Ground plane construction is highly
recommended, trace lengths should be as short as
• i = 1 to 2
(1, 2 corresponds to Channel A, B respectively)
• V = Total supply voltage (V + - V -)
S
S
S
• V + = Positive supply voltage
S
FN6893.0
May 12, 2010
12
EL5211T
possible and the power supply pins must be well
bypassed to reduce any risk of oscillation.
It is highly recommended that EL5211T exposed thermal
pad packages should always have the pad connected to
the lowest potential, V -, to optimize thermal and
operating performance. PCB vias should be placed below
the device’s exposed thermal pad to transfer heat to the
S
For normal single supply operation (the V - pin is
S
connected to ground) a 4.7μF capacitor should be placed
from V + to ground, then a parallel 0.1μF capacitor
S
V - plane and away from the device.
S
should be connected as close to the amplifier as possible.
One 4.7μF capacitor may be used for multiple devices.
For dual supply operation, the same capacitor
combination should be placed at each supply pin to
ground.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
FN6893.0
FN6893.0
CHANGE
5/12/10
2/24/10
Initial Release.
Pre-release data sheet submitted for formatting.
Products
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Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
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*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: EL5211T
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FITs are available from our website at http://rel.intersil.com/reports/search.php
FN6893.0
May 12, 2010
13
EL5211T
Package Outline Drawing
L8.2x3
8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 3/10
2.00
A
2X 1.50
PIN 1
INDEX AREA
6X 0.50
B
1
6
PIN #1
1.80 +0.10/-0.15
INDEX AREA
(4X)
0.15
8
4
8X 0.25 +0.07/-0.05
8X 0.40 ±0.10
0.10 M C A B
TOP VIEW
1.65 +0.10/-0.15
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0.90 ±0.10
(1.65)
(1.50)
C
BASE PLANE
SEATING PLANE
(8X 0.60)
0.08 C
0.05 MAX
SIDE VIEW
0.20 REF
(1.80)
(2.80)
C
(6X 0.50)
0.05 MAX
DETAIL "X"
(8X 0.25)
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.25mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
Compies to JEDEC MO-229 VCED-2.
7.
FN6893.0
May 12, 2010
14
EL5211T
HMSOP (Heat-Sink MSOP) Package Family
MDP0050
HMSOP (HEAT-SINK MSOP) PACKAGE FAMILY
E
0.25 M C A B
B
E1
MILLIMETERS
1
N
SYMBOL HMSOP8 HMSOP10
TOLERANCE
Max.
NOTES
A
A1
A2
b
1.00
0.075
0.86
0.30
0.15
3.00
1.85
4.90
3.00
1.73
0.65
0.55
0.95
8
1.00
0.075
0.86
0.20
0.15
3.00
1.85
4.90
3.00
1.73
0.50
0.55
0.95
10
-
D
(N/2)+1
+0.025/-0.050
±0.09
-
-
(N/2)
PIN #1
I.D.
A
+0.07/-0.08
±0.05
-
c
-
TOP VIEW
D
±0.10
1, 3
D1
E
Reference
±0.15
-
E2
EXPOSED
THERMAL PAD
-
E1
E2
e
±0.10
2, 3
Reference
Basic
-
D1
-
L
±0.15
-
L1
N
Basic
-
BOTTOM VIEW
Reference
-
Rev. 1 2/07
NOTES:
e
H
1. Plastic or metal protrusions of 0.15mm maximum per side are not
included.
C
SEATING
PLANE
2. Plastic interlead protrusions of 0.25mm maximum per side are
not included.
0.08
M
C A B
b
0.10 C
N LEADS
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
SIDE VIEW
L1
A
c
END VIEW
SEE DETAIL "X"
A2
GAUGE
PLANE
0.25
L
A1
3° ±3°
DETAIL X
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in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
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FN6893.0
May 12, 2010
15
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