EL5421CYZ [INTERSIL]

Quad 12MHz Rail-to-Rail Input-Output Buffer; 四12MHz的轨至轨输入,输出缓冲器
EL5421CYZ
型号: EL5421CYZ
厂家: Intersil    Intersil
描述:

Quad 12MHz Rail-to-Rail Input-Output Buffer
四12MHz的轨至轨输入,输出缓冲器

文件: 总11页 (文件大小:228K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
EL5421  
®
Data Sheet  
June 14, 2004  
FN7198.1  
Quad 12MHz Rail-to-Rail Input-Output  
Buffer  
Features  
• 12MHz -3dB bandwidth  
The EL5421 is a quad, low power, high  
voltage rail-to-rail input-output buffer.  
• Unity gain buffer  
• Supply voltage = 4.5V to 16.5V  
• Low supply current (per buffer) = 500µA  
• High slew rate = 10V/µs  
• Rail-to-rail operation  
Operating on supplies ranging from 5V  
to 15V, while consuming only 500µA per channel, the  
EL5421 has a bandwidth of 12MHz (-3dB). The EL5421 also  
provides rail-to-rail input and output ability, giving the  
maximum dynamic range at any supply voltage.  
The EL5421 also features fast slewing and settling times, as  
well as a high output drive capability of 30mA (sink and  
source). These features make the EL5421 ideal for use as  
voltage reference buffers in Thin Film Transistor Liquid  
Crystal Displays (TFT-LCD). Other applications include  
battery power, portable devices and anywhere low power  
consumption is important.  
• “Mini” SO package (MSOP)  
• Pb-free package available  
Applications  
• TFT-LCD drive circuits  
• Electronics notebooks  
• Electronics games  
The EL5421 is available in a space saving 10-pin MSOP  
package and operates over a temperature range of -40°C to  
+85°C.  
• Personal communication devices  
• Personal digital assistants (PDA)  
• Portable instrumentation  
• Wireless LANs  
Pinout  
EL 5421  
(10-PIN MSOP)  
TOP VIEW  
• Office automation  
• Active filters  
VOUTA  
VINA  
1
2
3
4
5
10 VOUTD  
• ADC/DAC buffers  
9
8
7
6
VIND  
VS-  
VS+  
Ordering Information  
VINB  
VINC  
VOUTC  
TAPE &  
PART NUMBER  
EL5421CY  
PACKAGE  
10-Pin MSOP  
10-Pin MSOP  
10-Pin MSOP  
REEL  
PKG. DWG. #  
MDP0043  
MDP0043  
MDP0043  
MDP0043  
VOUTB  
-
7”  
13”  
-
EL5421CY-T7  
EL5421CY-T13  
EL5421CYZ  
(Note)  
10-Pin MSOP  
(Pb-Free)  
EL5421CYZ-T7  
(Note)  
10-Pin MSOP  
(Pb-Free)  
7”  
MDP0043  
MDP0043  
EL5421CYZ-T13  
(Note)  
10-Pin MSOP  
(Pb-Free)  
13”  
NOTE: Intersil Pb-free products employ special Pb-free material  
sets; molding compounds/die attach materials and 100% matte tin  
plate termination finish, which is compatible with both SnPb and  
Pb-free soldering operations. Intersil Pb-free products are MSL  
classified at Pb-free peak reflow temperatures that meet or exceed  
the Pb-free requirements of IPC/JEDEC J Std-020B.  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
1
Copyright © Intersil Americas Inc. 2004. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc.  
All other trademarks mentioned are the property of their respective owners.  
EL5421  
Absolute Maximum Ratings (T = 25°C)  
A
Supply Voltage between V + and V -. . . . . . . . . . . . . . . . . . . .+18V  
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C  
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C  
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves  
S
S
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . .V - -0.5V, V + +0.5V  
S
S
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA  
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the  
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests  
are at the specified temperature and are pulsed tests, therefore: T = T = T  
A
J
C
Electrical Specifications V + = +5V, V - = -5V, R = 10kand C = 10pF to 0V, T = 25°C unless otherwise specified.  
S
S
L
L
A
PARAMETER  
DESCRIPTION  
CONDITION  
MIN  
TYP  
MAX  
UNIT  
INPUT CHARACTERISTICS  
V
Input Offset Voltage  
V
= 0V  
2
5
12  
mV  
µV/°C  
nA  
OS  
TCV  
CM  
(Note 1)  
= 0V  
Average Offset Voltage Drift  
Input Bias Current  
Input Impedance  
OS  
I
V
2
50  
B
CM  
R
1
GΩ  
IN  
IN  
V
C
Input Capacitance  
Voltage Gain  
1.35  
pF  
A
-4.5V V  
OUT  
4.5V  
0.995  
1.005  
-4.85  
V/V  
OUTPUT CHARACTERISTICS  
V
V
Output Swing Low  
Output Swing High  
Short Circuit Current  
I = -5mA  
-4.92  
4.92  
V
V
OL  
L
I = 5mA  
4.85  
±80  
OH  
L
I
Short to GND (Note 2)  
±120  
mA  
SC  
POWER SUPPLY PERFORMANCE  
PSRR Power Supply Rejection Ratio  
Supply Current (Per Buffer)  
DYNAMIC PERFORMANCE  
SR Slew Rate (Note 3)  
V
is moved from ±2.25V to ±7.75V  
60  
7
80  
dB  
µA  
S
I
No load  
500  
750  
S
-4.0V V  
4.0V, 20% to 80%  
10  
500  
12  
V/µs  
ns  
OUT  
t
Settling to +0.1%  
-3dB Bandwidth  
V = 2V step  
O
S
BW  
R
= 10k, C = 10pF  
MHz  
dB  
L
L
CS  
Channel Separation  
f = 5MHz  
75  
NOTES:  
1. Measured over the operating temperature range  
2. Parameter is guaranteed (but not test) by design and characterization data  
3. Slew rate is measured on rising and falling edges  
2
EL5421  
Electrical Specifications V + = +5V, V - = 0V, R = 10kand C = 10pF to 2.5V, T = 25°C unless otherwise specified.  
S
S
L
L
A
PARAMETER  
DESCRIPTION  
CONDITION  
MIN  
TYP  
MAX  
UNIT  
INPUT CHARACTERISTICS  
V
Input Offset Voltage  
V
= 2.5V  
2
5
10  
mV  
µV/°C  
nA  
OS  
TCV  
CM  
(Note 1)  
= 2.5V  
Average Offset Voltage Drift  
Input Bias Current  
Input Impedance  
OS  
I
V
2
50  
B
CM  
R
1
GΩ  
IN  
IN  
V
C
Input Capacitance  
Voltage Gain  
1.35  
pF  
A
0.5 V  
OUT  
4.5V  
0.995  
1.005  
150  
V/V  
OUTPUT CHARACTERISTICS  
V
V
Output Swing Low  
Output Swing High  
Short Circuit Current  
I = -5mA  
80  
mV  
V
OL  
L
I = 5mA  
4.85  
±80  
4.92  
±120  
OH  
L
I
Short to GND (Note 2)  
mA  
SC  
POWER SUPPLY PERFORMANCE  
PSRR Power Supply Rejection Ratio  
Supply Current (Per Buffer)  
DYNAMIC PERFORMANCE  
SR Slew Rate (Note 3)  
V
is moved from 4.5V to 15.5V  
60  
7
80  
dB  
µA  
S
I
No load  
500  
750  
S
1V V  
4V, 20% to 80%  
10  
500  
12  
V/µs  
ns  
OUT  
V = 2V step  
O
t
Settling to +0.1%  
-3dB Bandwidth  
S
BW  
R
= 10k, C = 10pF  
MHz  
dB  
L
L
CS  
Channel Separation  
f = 5MHz  
75  
NOTES:  
1. Measured over the operating temperature range  
2. Parameter is guaranteed (but not test) by design and characterization data  
3. Slew rate is measured on rising and falling edges  
3
EL5421  
Electrical Specifications V + = +15V, V - = 0V, R = 10kand C = 10pF to 7.5V, T = 25°C unless otherwise specified.  
S
S
L
L
A
PARAMETER  
DESCRIPTION  
CONDITION  
MIN  
TYP  
MAX  
UNIT  
INPUT CHARACTERISTICS  
V
Input Offset Voltage  
V
= 7.5V  
2
5
14  
mV  
µV/°C  
nA  
OS  
TCV  
CM  
(Note 1)  
= 7.5V  
Average Offset Voltage Drift  
Input Bias Current  
Input Impedance  
OS  
I
V
2
50  
B
CM  
R
1
GΩ  
IN  
IN  
V
C
Input Capacitance  
Voltage Gain  
1.35  
pF  
A
0.5 V  
14.5V  
0.995  
1.005  
150  
V/V  
OUT  
OUTPUT CHARACTERISTICS  
V
V
Output Swing Low  
Output Swing High  
Short Circuit Current  
I = -5mA  
80  
mV  
V
OL  
L
I = 5mA  
14.85  
±80  
14.92  
±120  
OH  
L
I
Short to GND (Note 2)  
mA  
SC  
POWER SUPPLY PERFORMANCE  
PSRR Power Supply Rejection Ratio  
Supply Current (Per Buffer)  
DYNAMIC PERFORMANCE  
SR Slew Rate (Note 3)  
V
is moved from 4.5V to 15.5V  
60  
7
80  
dB  
µA  
S
I
No load  
500  
750  
S
1V V  
14V, 20% to 80%  
10  
500  
12  
V/µs  
ns  
OUT  
V = 2V step  
O
t
Settling to +0.1%  
-3dB Bandwidth  
S
BW  
R
= 10k, C = 10pF  
MHz  
dB  
L
L
CS  
Channel Separation  
f = 5MHz  
75  
NOTES:  
1. Measured over the operating temperature range  
2. Parameter is guaranteed (but not test) by design and characterization data  
3. Slew rate is measured on rising and falling edges  
4
EL5421  
Typical Performance Curves  
1800  
70  
60  
50  
40  
30  
20  
10  
0
V =±5V  
TYPICAL  
V =±5V  
TYPICAL  
S
S
1600  
1400  
1200  
1000  
800  
600  
400  
200  
0
T =25°C  
PRODUCTION  
DISTRIBUTION  
PRODUCTION  
DISTRIBUTION  
A
INPUT OFFSET VOLTAGE (mV)  
INPUT OFFSET VOLTAGE DRIFT, TCV  
(µV/°C)  
OS  
FIGURE 1. INPUT OFFSET VOLTAGE DISTRIBUTION  
FIGURE 2. INPUT OFFSET VOLTAGE DRIFT  
10  
2.0  
V =±5V  
S
V =±5V  
S
5
0
0.0  
-2.0  
-5  
-50  
0
50  
100  
150  
-50  
0
50  
100  
150  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
FIGURE 3. INPUT OFFSET VOLTAGE vs TEMPERATURE  
FIGURE 4. INPUT BIAS CURRENT vs TEMPERATURE  
-4.91  
4.97  
4.96  
4.95  
4.94  
V =±5V  
S
I
=-5mA  
OUT  
-4.92  
-4.93  
-4.94  
-4.95  
-4.96  
-4.97  
V =±5V  
S
OUT  
I
=5mA  
4.93  
-50  
0
50  
100  
150  
-50  
0
50  
100  
150  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
FIGURE 5. OUTPUT HIGH VOLTGE vs TEMPERATURE  
FIGURE 6. OUTPUT LOW VOLTAGE vs TEMPERATURE  
5
EL5421  
Typical Performance Curves  
10.40  
10.35  
10.30  
10.25  
V =±5V  
S
V =±5V  
S
1.0005  
1.0000  
0.9995  
-50  
0
50  
100  
150  
-50  
0
50  
100  
150  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
FIGURE 7. VOLTAGE GAIN vs TEMPERATURE  
FIGURE 8. SLEW RATE vs TEMPERATURE  
700  
T =25°C  
V =±5V  
S
A
0.55  
0.5  
600  
500  
400  
300  
0.45  
-50  
0
50  
100  
150  
0
5
10  
15  
20  
TEMPERATURE (°C)  
SUPPLY VOLTAGE (V)  
FIGURE 9. SUPPLY CURRENT PER CHANNEL vs  
TEMPERATURE  
FIGURE 10. SUPPLY CURRENT PER CHANNEL vs SUPPLY  
VOLTAGE  
5
20  
R =10kΩ  
L
V =±5V  
S
10kΩ  
10  
0
0
12pF  
50pF  
1kΩ  
560Ω  
-5  
150Ω  
-10  
-20  
-30  
100pF  
-10  
1000pF  
1M  
C =10pF  
L
V =±5V  
S
-15  
100K  
1M  
10M  
100M  
100K  
10M  
100M  
FREQUENCY (Hz)  
FREQUENCY (Hz)  
FIGURE 11. FREQUENCY RESPONSE FOR VARIOUS R  
FIGURE 12. FREQUENCY RESPONSE FOR VARIOUS C  
L
L
6
EL5421  
Typical Performance Curves  
200  
12  
10  
8
T =25°C  
A
V =±5V  
S
160  
120  
80  
6
V =±5V  
S
4
T =25°C  
A
R =10kΩ  
L
40  
2
C =12pF  
L
DISTORTION <1%  
0
0
10K  
100K  
1M  
10M  
10K  
100K  
1M  
10M  
FREQUENCY (Hz)  
FREQUENCY (Hz)  
FIGURE 13. OUT PUT IMPEDANCE vs FREQUENCY  
FIGURE 14. MAXIMUM OUTPUT SWING vs FREQUENCY  
600  
80  
PSRR+  
PSRR-  
60  
100  
10  
1
40  
20  
T =25°C  
A
V =±5V  
S
0
100  
1K  
10K  
100K  
1M  
10M  
100M  
100  
1K  
10K  
100K  
1M  
10M  
FREQUENCY (Hz)  
FREQUENCY (Hz)  
FIGURE 15. PSRR vs FREQUENCY  
FIGURE 16. INPUT VOLTAGE NOISE SPECTRAL DENSITY vs  
FREQUENCY  
0.010  
0.009  
0.008  
0.007  
0.006  
0.005  
0.004  
0.003  
0.002  
0.001  
-60  
V =±5V  
S
DUAL MEASURED CH A TO B  
QUAD MEASURED CH A TO D OR B TO C  
OTHER COMBINATIONS YIELD IMPROVED  
R =10kΩ  
L
V
=1V  
RMS  
IN  
-80  
-100  
-120  
-140  
REJECTION  
V =±5V  
S
R =10kΩ  
L
V
=220mV  
IN  
RMS  
1K  
10K  
100K  
FREQUENCY (Hz)  
1M  
6M  
1K  
10K  
100K  
FREQUENCY (Hz)  
FIGURE 17. TOTAL HARMONIC DISTORTION + NOISE vs  
FREQUENCY  
FIGURE 18. CHANNEL SEPARATION vs FREQUENCY  
RESPONSE  
7
EL5421  
Typical Performance Curves  
5
3
V =±5V  
S
V =±5V  
S
90  
R =10kΩ  
R =10kΩ  
L
L
0.1%  
0.1%  
V
=±50mV  
C =12pF  
L
IN  
T =25°C  
T =25°C  
A
A
70  
50  
30  
10  
1
-1  
-3  
-5  
10  
100  
1K  
0
200  
400  
600  
800  
LOAD CAPACITANCE (pF)  
SETTLING TIME (ns)  
FIGURE 19. SMALL SIGNAL OVERSHOOT vs LOAD  
CAPACITANCE  
FIGURE 20. SETTLING TIME vs STEP SIZE  
1V  
1µs  
50mV  
200ns  
V =±5V  
S
T =25°C  
A
V =±5V  
S
R =10kΩ  
L
T =25°C  
A
C =12pF  
L
R =10kΩ  
L
C =12pF  
L
FIGURE 21. LARGE SIGNAL TRANSIENT RESPONSE  
FIGURE 22. SMALL SIGNAL TRANSIENT REPOSNE  
8
EL5421  
Pin Descriptions  
PIN NUMBER  
PIN NAME  
FUNCTION  
EQUIVALENT CIRCUIT  
1
VOUTA  
Buffer A Output  
V +  
S
V -  
S
GND  
CIRCUIT 1  
2
VINA  
Buffer A Input  
V +  
S
V -  
S
CIRCUIT 2  
3
4
VS+  
VINB  
Positive Power Supply  
Buffer B Input  
(Reference Circuit 1)  
(Reference Circuit 2)  
(Reference Circuit 2)  
(Reference Circuit 1)  
5
VOUTB  
VOUTC  
VINC  
Buffer B Output  
Buffer C Output  
Buffer C Input  
6
7
8
VS-  
Negative Power Supply  
Buffer D Input  
9
VIND  
(Reference Circuit 2)  
(Reference Circuit 1)  
10  
VOUTD  
Buffer D Output  
voltage range even closer to the supply rails. Figure 23  
shows the input and output waveforms for the device.  
Operation is from ±5V supply with a 10kload connected to  
Applications Information  
Product Description  
The EL5421 unity gain buffer is fabricated using a high  
voltage CMOS process. It exhibits rail-to-rail input and  
output capability, and has low power consumption (500µA  
per buffer). These features make the EL5421 ideal for a wide  
range of general-purpose applications. When driving a load  
of 10kand 12pF, the EL5421 has a -3dB bandwidth of  
12MHz and exhibits 10V/µs slew rate.  
GND. The input is a 10V  
sinusoid. The output voltage is  
P-P  
P-P  
approximately 9.985V  
.
10µs  
5V  
Operating Voltage, Input, and Output  
The EL5421 is specified with a single nominal supply voltage  
from 5V to 15V or a split supply with its total range from 5V  
to 15V. Correct operation is guaranteed for a supply range of  
4.5V to 16.5V. Most EL5421 specifications are stable over  
both the full supply range and operating temperatures of  
-40°C to +85°C. Parameter variations with operating voltage  
and/or temperature are shown in the typical performance  
curves.  
V =±5V  
S
T =25°C  
A
V
=10V  
P-P  
IN  
5V  
FIGURE 23. OPERATION WITH RAIL-TO-RAIL INPUT AND  
OUTPUT  
Short Circuit Current Limit  
The EL5421 will limit the short circuit current to ±120mA if  
the output is directly shorted to the positive or the negative  
The output swings of the EL5421 typically extend to within  
80mV of positive and negative supply rails with load currents  
of 5mA. Decreasing load currents will extend the output  
9
EL5421  
supply. If an output is shorted indefinitely, the power  
dissipation could easily increase such that the device may  
be damaged. Maximum reliability is maintained if the output  
continuous current never exceeds ±30mA. This limit is set by  
the design of the internal metal interconnects.  
The maximum power dissipation actually produced by an IC  
is the total quiescent supply current times the total power  
supply voltage, plus the power in the IC due to the loads, or:  
P
= Σi[V × I  
+ (V + V  
i) × I  
i]  
LOAD  
DMAX  
S
SMAX  
S
OUT  
Output Phase Reversal  
when sourcing, and:  
The EL5421 is immune to phase reversal as long as the  
input voltage is limited from V - -0.5V to V + +0.5V. Figure  
S
S
P
= Σi[V × I  
+ (V  
i V -) × I  
i]  
LOAD  
24 shows a photo of the output of the device with the input  
voltage driven beyond the supply rails. Although the device's  
output will not change phase, the input's overvoltage should  
be avoided. If an input voltage exceeds supply voltage by  
more than 0.6V, electrostatic protection diodes placed in the  
input stage of the device begin to conduct and overvoltage  
damage could occur.  
DMAX  
S
SMAX  
OUT  
S
when sinking.  
Where:  
i = 1 to 4 for quad  
V
= Total supply voltage  
S
10µs  
1V  
I
= Maximum supply current per channel  
SMAX  
V
i = Maximum output voltage of the application  
OUT  
I
i = Load current  
LOAD  
If we set the two P  
DMAX  
equations equal to each other, we  
can solve for R  
i to avoid device overheat. Figures 25  
LOAD  
and 26 provide a convenient way to see if the device will  
overheat. The maximum safe power dissipation can be  
found graphically, based on the package type and the  
ambient temperature. By using the previous equation, it is a  
V =±2.5V  
S
T =25°C  
A
V
=6V  
IN  
P-P  
1V  
simple matter to see if P  
exceeds the device's power  
DMAX  
FIGURE 24. OPERATION WITH BEYOND-THE-RAILS INPUT  
derating curves. To ensure proper operation, it is important  
to observe the recommended derating curves shown in  
Figures 25 and 26.  
Power Dissipation  
With the high-output drive capability of the EL5421 buffer, it  
is possible to exceed the 125°C 'absolute-maximum junction  
temperature' under certain load current conditions.  
Therefore, it is important to calculate the maximum junction  
temperature for the application to determine if load  
conditions need to be modified for the buffer to remain in the  
safe operating area.  
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL  
CONDUCTIVITY TEST BOARD  
1
0.9  
870mW  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
0
The maximum power dissipation allowed in a package is  
determined according to:  
T
T  
AMAX  
JMAX  
P
= --------------------------------------------  
DMAX  
Θ
JA  
where:  
0
25  
50  
75 85 100  
125  
T
= Maximum junction temperature  
AMBIENT TEMPERATURE (°C)  
JMAX  
T
= Maximum ambient temperature  
AMAX  
FIGURE 25. PACKAGE POWER DISSIPATION vs AMBIENT  
TEMPERATURE  
θ
= Thermal resistance of the package  
JA  
P
= Maximum power dissipation in the package  
DMAX  
10  
EL5421  
Power Supply Bypassing and Printed Circuit  
Board Layout  
The EL5421 can provide gain at high frequency. As with any  
high-frequency device, good printed circuit board layout is  
necessary for optimum performance. Ground plane  
JEDEC JESD51-3 LOW EFFECTIVE THERMAL  
CONDUCTIVITY TEST BOARD  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
0
486mW  
construction is highly recommended, lead lengths should be  
as short as possible and the power supply pins must be well  
bypassed to reduce the risk of oscillation. For normal single  
supply operation, where the V - pin is connected to ground,  
S
a 0.1µF ceramic capacitor should be placed from V + to pin  
S
to V - pin. A 4.7µF tantalum capacitor should then be  
S
connected in parallel, placed in the region of the buffer. One  
4.7µF capacitor may be used for multiple devices. This same  
capacitor combination should be placed at each supply pin  
to ground if split supplies are to be used.  
0
25  
50  
75 85 100  
125  
AMBIENT TEMPERATURE (°C)  
FIGURE 26. PACKAGE POWER DISSIPATION VS AMBIENT  
TEMPERATURE  
Unused Buffers  
It is recommended that any unused buffer have the input tied  
to the ground plane.  
Driving Capacitive Loads  
The EL5421 can drive a wide range of capacitive loads. As  
load capacitance increases, however, the -3dB bandwidth of  
the device will decrease and the peaking increase. The  
buffers drive 10pF loads in parallel with 10kwith just 1.5dB  
of peaking, and 100pF with 6.4dB of peaking. If less peaking  
is desired in these applications, a small series resistor  
(usually between 5and 50) can be placed in series with  
the output. However, this will obviously reduce the gain  
slightly. Another method of reducing peaking is to add a  
"snubber" circuit at the output. A snubber is a shunt load  
consisting of a resistor in series with a capacitor. Values of  
150and 10nF are typical. The advantage of a snubber is  
that it does not draw any DC load current or reduce the gain  
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.  
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality  
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without  
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and  
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result  
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see www.intersil.com  
11  

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