EL5423CRZ-T7 [INTERSIL]
12MHz 4, 8, 10 & 12 Channel Rail-to-Rail Input-Output Buffers; 12MHz的4 ， 8 ， 10及12通道，轨到轨输入输出缓冲器
| 型号： | EL5423CRZ-T7 |
| 厂家： | 
Intersil |
| 描述： | 12MHz 4, 8, 10 & 12 Channel Rail-to-Rail Input-Output Buffers |
| 文件： | 总12页 (文件大小：289K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EL5123, EL5223, EL5323, EL5423
®
Data Sheet
November 19, 2004
FN7176.1
12MHz 4, 8, 10 & 12 Channel Rail-to-Rail
Input-Output Buffers
Features
• 12MHz -3dB bandwidth
The EL5123, EL5223, EL5323, and EL5423 are low power,
high voltage rail-to-rail input/output buffers designed
primarily for use in reference voltage buffering applications
for TFT-LCDs. They are available in quad (EL5123), octal
(EL5223), 10-channel (EL5323), and 12-channel (EL5423)
topologies. All buffers feature a -3dB bandwidth of 12MHz
and operate from just 600µA per buffer. This family also
features fast slewing and settling times, as well as a
continuous output drive capability of 30mA (sink and
source).
• Supply voltage = 4.5V to 16.5V
• Low supply current (per buffer) = 600µA
• High slew rate = 15V/µs
• Rail-to-rail input/output swing
• Ultra-small packages
• Pb-free available (RoHS compliant)
Applications
The quad channel EL5123 is available in the 10-pin MSOP
package. The 8-channel EL5223 is available in both the 20-
pin TSSOP and 24-pin QFN packages, the 10-channel
EL5323 in the 24-pin TSSOP and 24-pin QFN packages,
and the 12-channel EL5423 in the 28-pin TSSOP and 32-pin
QFN packages. All buffers are specified for operation over
the full -40°C to +85°C temperature range.
• TFT-LCD drive circuits
• Electronics notebooks
• Electronic games
• Touch-screen displays
• Personal communication devices
• Personal digital assistants (PDA)
• Portable instrumentation
• Sampling ADC amplifiers
• Wireless LANs
• Office automation
• Active filters
• ADC/DAC buffers
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002-2004. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc.
All other trademarks mentioned are the property of their respective owners.
EL5123, EL5223, EL5323, EL5423
Pinouts
EL5223 & EL5323
(24-PIN QFN)
TOP VIEW
EL5123
(10-PIN MSOP)
TOP VIEW
EL5223
(20-PIN TSSOP)
TOP VIEW
VIN1
VIN2
VS+
1
2
3
4
5
10
9
VIN1
VIN2
VIN3
VIN4
VS+
1
20 VOUT1
19 VOUT2
18 VOUT3
17 VOUT4
16 VS-
VOUT1
VOUT2
VS-
2
3
4
5
6
7
8
9
VIN3
VIN4
VIN5
VS+
1
19 VOUT3
18 VOUT4
17 VOUT5
16 VS-
8
2
3
4
5
6
7
7
VIN3
VIN4
VOUT3
VOUT4
6
THERMAL
PAD
VS+
15 VS-
VIN6
VIN7
VIN8
15 VOUT6
14 VOUT7
13 VOUT8
VIN5
VIN6
VIN7
14 VOUT5
13 VOUT6
12 VOUT7
11 VOUT8
VIN8 10
* NOT AVAILABLE IN EL5223
EL5423
(32-PIN QFN)
TOP VIEW
EL5423
(28-PIN TSSOP)
EL5323
(24-PIN TSSOP)
TOP VIEW
TOP VIEW
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VS+
1
2
3
4
5
6
7
8
9
28 VOUT1
27 VOUT2
26 VOUT3
25 VOUT4
24 VOUT5
23 VOUT6
22 VS-
VIN1
VIN2
VIN3
VIN4
VIN5
VS+
1
24 VOUT1
23 VOUT2
22 VOUT3
21 VOUT4
20 VOUT5
19 VS-
2
3
4
5
6
7
8
9
VIN3
VIN4
VIN5
VIN6
VS+
1
25 VOUT3
2
3
4
5
6
7
8
9
24 VOUT4
23 VOUT5
22 VOUT6
21 VS-
THERMAL
PAD
VS+
18 VS-
VIN7
VIN8
VIN9
VIN10
20 VOUT7
19 VOUT8
18 VOUT9
17 VOUT10
VS+
21 VS-
VIN6
VIN7
17 VOUT6
16 VOUT7
15 VOUT8
14 VOUT9
13 VOUT10
VIN7
20 VOUT7
19 VOUT8
18 VOUT9
17 VOUT10
16 VOUT11
15 VOUT12
VIN8 10
VIN9 11
VIN8 10
VIN9 11
VIN10 12
VIN10 12
VIN11 13
VIN12 14
FN7176.1
November 19, 2004
2
EL5123, EL5223, EL5323, EL5423
Ordering Information
TAPE &
REEL
TAPE &
REEL
PART NO.
EL5123CY
PACKAGE
PKG. DWG. #
PART NO.
PACKAGE
PKG. DWG. #
10-Pin MSOP
-
MDP0043
EL5323CLZ
(See Note)
24-Pin QFN
(Pb-Free)
-
7”
13”
-
MDP0046
EL5123CY-T7
EL5123CY-T13
10-Pin MSOP
10-Pin MSOP
7”
13”
-
MDP0043
MDP0043
MDP0043
MDP0043
MDP0043
MDP0046
MDP0046
MDP0046
MDP0046
MDP0046
MDP0046
MDP0044
MDP0044
MDP0044
MDP0044
MDP0044
MDP0044
MDP0046
MDP0046
MDP0046
EL5323CLZ-T7
(See Note)
24-Pin QFN
(Pb-Free)
MDP0046
MDP0046
MDP0044
MDP0044
MDP0044
MDP0044
MDP0044
MDP0044
MDP0046
MDP0046
MDP0046
MDP0046
MDP0046
MDP0046
MDP0044
MDP0044
MDP0044
MDP0044
MDP0044
MDP0044
EL5323CLZ-T13
(See Note)
24-Pin QFN
(Pb-Free)
EL5123CYZ
(See Note)
10-Pin MSOP
(Pb-Free)
EL5323CR
24-Pin TSSOP
24-Pin TSSOP
24-Pin TSSOP
EL5123CYZ-T7
(See Note)
10-Pin MSOP
(Pb-Free)
7”
13”
-
EL5323CR-T7
EL5323CR-T13
7”
13”
-
EL5123CYZ-T13
(See Note)
10-Pin MSOP
(Pb-Free)
EL5223CL
24-Pin QFN
24-Pin QFN
24-Pin QFN
EL5323CRZ
(See Note)
24-Pin TSSOP
(Pb-Free)
EL5223CL-T7
EL5223CL-T13
7”
13”
-
EL5323CRZ-T7
(See Note)
24-Pin TSSOP
(Pb-Free)
7”
13”
-
EL5323CRZ-T13
(See Note)
24-Pin TSSOP
(Pb-Free)
EL5223CLZ
(See Note)
24-Pin QFN
(Pb-Free)
EL5423CL
32-Pin QFN
32-Pin QFN
32-Pin QFN
EL5223CLZ-T7
(See Note)
24-Pin QFN
(Pb-Free)
7”
13”
-
EL5423CL-T7
EL5423CL-T13
7”
13”
-
EL5223CLZ-T13
(See Note)
24-Pin QFN
(Pb-Free)
EL5223CR
20-Pin TSSOP
20-Pin TSSOP
20-Pin TSSOP
EL5423CLZ
(See Note)
32-Pin QFN
(Pb-Free)
EL5223CR-T7
EL5223CR-T13
7”
13”
-
EL5423CLZ-T7
(See Note)
32-Pin QFN
(Pb-Free)
7”
13”
-
EL5423CLZ-T13
(See Note)
32-Pin QFN
(Pb-Free)
EL5223CRZ
(See Note)
20-Pin TSSOP
(Pb-Free)
EL5423CR
28-Pin TSSOP
28-Pin TSSOP
28-Pin TSSOP
EL5223CRZ-T7
(See Note)
20-Pin TSSOP
(Pb-Free)
7”
13”
-
EL5423CR-T7
EL5423CR-T13
7”
13”
-
EL5223CRZ-T13 20-Pin TSSOP
(See Note)
(Pb-Free)
EL5323CL
24-Pin QFN
EL5423CRZ
(See Note)
28-Pin TSSOP
(Pb-Free)
EL5323CL-T7
EL5323CL-T13
24-Pin QFN
24-Pin QFN
7”
13”
EL5423CRZ-T7
(See Note)
28-Pin TSSOP
(Pb-Free)
7”
13”
EL5423CRZ-T13
(See Note)
28-Pin TSSOP
(Pb-Free)
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination
finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-
free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C.
FN7176.1
November 19, 2004
3
EL5123, EL5223, EL5323, EL5423
Absolute Maximum Ratings (T = 25°C)
A
Supply Voltage between V + and V -. . . . . . . . . . . . . . . . . . . .+18V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
ESD Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kV
S
S
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . .V - -0.5V, V +0.5V
S
S
Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .+125°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T = T = T
A
J
C
Electrical Specifications V + = +5V, V - = -5V, R = 10kΩ and C = 10pF to 0V, T = 25°C unless otherwise specified.
S
S
L
L
A
PARAMETER
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
INPUT CHARACTERISTICS
V
Input Offset Voltage
V
= 0V
0.5
5
12
mV
µV/°C
nA
OS
CM
(Note 1)
= 0V
TCV
Average Offset Voltage Drift
Input Bias Current
Input Impedance
OS
I
V
2
50
B
CM
R
C
1
GΩ
IN
IN
Input Capacitance
Voltage Gain
1.35
pF
A
-4.5V ≤ V
≤ 4.5V
OUT
0.99
4.85
55
1.01
V/V
V
OUTPUT CHARACTERISTICS
V
V
Output Swing Low
I = -5mA
-4.95
4.95
-4.85
V
V
OL
OH
L
Output Swing High
Output Current (Note 2)
I = +5mA
L
I
(max)
R
= 10Ω
±120
mA
OUT
L
POWER SUPPLY PERFORMANCE
PSRR Power Supply Rejection Ratio
Supply Current
V
is moved from ±2.25V to ±7.75V
80
2.4
5.5
6
dB
mA
mA
mA
mA
S
I
No load (EL5123)
No load (EL5223)
No load (EL5323)
No load (EL5423)
3.4
6.8
S
8.5
7.45
10.1
DYNAMIC PERFORMANCE
SR Slew Rate (Note 3)
-4.0V ≤ V
≤ 4.0V, 20% to 80%
(A = +1), V = 2V step
7
15
250
12
V/µs
ns
OUT
t
Settling to +0.1% (A = +1)
V
S
V
O
BW
-3dB Bandwidth
R
= 10kΩ, C = 10pF
MHz
dB
L
L
CS
Channel Separation
f = 5MHz
75
NOTES:
1. Measured over operating temperature range.
2. Instantaneous peak current.
3. Slew rate is measured on rising and falling edges.
FN7176.1
November 19, 2004
4
EL5123, EL5223, EL5323, EL5423
Electrical Specifications V + =+5V, V - = 0V, R = 10kΩ and C = 10pF to 2.5V, T = 25°C unless otherwise specified.
S
S
L
L
A
PARAMETER
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
INPUT CHARACTERISTICS
V
Input Offset Voltage
V
= 2.5V
0.5
5
12
mV
µV/°C
nA
OS
CM
(Note 1)
= 2.5V
TCV
Average Offset Voltage Drift
Input Bias Current
Input Impedance
OS
I
V
2
50
B
CM
R
1
GΩ
IN
IN
C
Input Capacitance
Voltage Gain
1.35
pF
A
0.5V ≤ V
≤ 4.5V
OUT
0.99
4.85
55
1.01
150
V/V
V
OUTPUT CHARACTERISTICS
V
V
Output Swing Low
I = -2.5mA
80
mV
V
OL
OH
L
Output Swing High
Output Current (Note 2)
I = +2.5mA
4.92
±120
L
I
(max)
R
= 10Ω
mA
OUT
L
POWER SUPPLY PERFORMANCE
PSRR Power Supply Rejection Ratio
Supply Current
V
is moved from 4.5V to 15.5V
80
2.4
5.2
5.8
7.2
dB
mA
mA
mA
mA
S
I
No load (EL5123)
No load (EL5223)
No load (EL5323)
No load (EL5423)
3.2
6.5
8
S
9.7
DYNAMIC PERFORMANCE
SR Slew Rate (Note 3)
1V ≤ V
≤ 4V, 20% to 80%
12
250
12
V/µs
ns
OUT
t
Settling to +0.1% (A = +1)
V
(A = +1), V = 2V step
S
V
O
BW
-3dB Bandwidth
R
= 10kΩ, C = 10pF
MHz
dB
L
L
CS
Channel Separation
f = 5MHz
75
NOTES:
1. Measured over operating temperature range.
2. Instantaneous peak current.
3. Slew rate is measured on rising and falling edges
FN7176.1
November 19, 2004
5
EL5123, EL5223, EL5323, EL5423
Electrical Specifications
V + = +15V, V - = 0V, R = 10kΩ and C = 10pF to 7.5V, T = 25°C unless otherwise specified.
S
S
L
L
A
PARAMETER
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
INPUT CHARACTERISTICS
V
Input Offset Voltage
V
= 7.5V
CM
0.5
5
14
mV
µV/°C
nA
OS
TCV
Average Offset Voltage Drift
Input Bias Current
Input Impedance
(Note 1)
= 7.5V
OS
I
V
2
50
B
CM
R
1
GΩ
IN
IN
C
Input Capacitance
Voltage Gain
1.35
pF
A
0.5V ≤ V
≤ 14.5V
OUT
0.99
1.01
150
V/V
V
OUTPUT CHARACTERISTICS
V
V
Output Swing Low
I = -7.5mA
80
mV
V
OL
OH
L
Output Swing High
Output Current (Note 2)
I = +7.5mA
14.85
120
14.95
200
L
I
(max)
R
= 10Ω
mA
OUT
L
POWER SUPPLY PERFORMANCE
PSRR Power Supply Rejection Ratio
Supply Current
V
is moved from 4.5V to 15.5V
55
80
2.4
5.7
6.2
7.8
dB
mA
mA
mA
mA
S
I
No load (EL5123)
No load (EL5223)
No load (EL5323)
No load (EL5423)
3.7
7.1
S
8.7
10.4
DYNAMIC PERFORMANCE
SR Slew Rate (Note 3)
1V ≤ V
≤ 14V, 20% to 80%
18
250
12
V/µs
ns
OUT
t
Settling to +0.1% (A = +1)
V
(A = +1), V = 2V step
S
V
O
BW
-3dB Bandwidth
R
= 10kΩ, C = 10pF
MHz
dB
L
L
CS
Channel Separation
f = 5MHz
75
NOTES:
1. Measured over operating temperature range.
2. Instantaneous peak current.
3. Slew rate is measured on rising and falling edges.
FN7176.1
November 19, 2004
6
EL5123, EL5223, EL5323, EL5423
Typical Performance Curves
12
10
8
0.018
V =±5V
S
R =10kΩ
L
IN
0.016
0.014
0.012
0.01
V
=2V
P-P
6
4
2
0.008
V =±5V
S
R =10kΩ
L
0
10K
0.006
100K
1M
10M
1K
10K
100K
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 1. OUTPUT SWING vs FREQUENCY
FIGURE 2. TOTAL HARMONIC DISTORTION + NOISE vs
FREQUENCY
80
10
V =±5V
S
V =±5V
S
R =10kΩ
R =10kΩ
70
60
50
40
30
20
10
0
L
L
V
=100mV
C =12pF
IN
L
6
2
-2
-6
-10
10
100
1K
200 250 300 350 400 450 500 550 600 650
CAPACITANCE (pF)
SETTLING TIME (ns)
FIGURE 3. OVERSHOOT vs LOAD CAPACITANCE
FIGURE 4. SETTLING TIME vs STEP SIZE
20
20
V =±5V
V =±5V
S
S
1000pF
R =10kΩ
C =10pF
L
L
100pF
12pF
10
0
10
0
1kΩ
10kΩ
47pF
562Ω
-10
-20
-30
-10
-20
-30
150Ω
100K
1M
10M
100M
100K
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 5. FREQUENCY RESPONSE FOR VARIOUS C
FIGURE 6. FREQUENCY RESPONSE FOR VARIOUS R
L
L
FN7176.1
November 19, 2004
7
EL5123, EL5223, EL5323, EL5423
Typical Performance Curves
100
600
V =±5V
S
PSRR+
T =25°C
A
80
480
360
240
120
0
PSRR-
60
40
20
V =±5V
S
0
1K
10K
100K
1M
10M
100K
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 7. PSRR vs FREQUENCY
FIGURE 8. OUTPUT IMPEDANCE vs FREQUENCY
25
20
15
10
5
100
10
1
0
10K
100K
1M
10M
100M
FREQUENCY (Hz)
INPUT OFFSET VOLTAGE (mV)
FIGURE 9. INPUT NOISE SPECTRAL DENSITY vs FREQUENCY
FIGURE 10. INPUT OFFSET VOLTAGE DISTRIBUTION
2.5
4.955
4.95
V =±5V
S
1.5
0.5
4.945
4.94
-0.5
-1.5
-2.5
4.935
4.93
V =±5V
S
I
=5mA
OUT
4.925
-35
-15
5
25
45
65
85
-35
-15
5
25
45
65
85
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 11. INPUT BIAS CURRENT vs TEMPERATURE
FIGURE 12. OUTPUT HIGH VOLTAGE vs TEMPERATURE
FN7176.1
November 19, 2004
8
EL5123, EL5223, EL5323, EL5423
Typical Performance Curves
15.1
-4.934
V =±5V
S
V =±5V
S
I
=-5mA
OUT
14.9
14.7
14.5
14.3
14.1
-4.938
-4.942
-4.946
-4.95
-4.954
-35
-15
5
25
45
65
85
-35
-15
5
25
45
65
85
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 13. SLEW RATE vs TEMPERATURE
FIGURE 14. OUTPUT LOW VOLTAGE vs TEMPERATURE
0.66
1.0014
V =±5V
S
V =±5V
S
1.001
1.0006
1
0.65
0.64
0.63
0.62
0.9998
-35
-15
5
25
45
65
85
-35
-15
5
25
45
65
85
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 15. VOLTAGE GAIN vs TEMPERATURE
FIGURE 16. SUPPLY CURRENT PER CHANNEL vs
TEMPERATURE
0.71
T =25°C
A
V =±5V
S
R =10kΩ
L
C =12pF
L
0.69
0.67
0.65
0.63
50mV/DIV
4
6
8
10
12
14
16
18
200ns/DIV
SUPPLY VOLTAGE (V)
FIGURE 17. SUPPLY CURRENT PER CHANNEL vs SUPPLY
VOLTAGE
FIGURE 18. SMALL SIGNAL TRANSIENT RESPONSE
FN7176.1
November 19, 2004
9
EL5123, EL5223, EL5323, EL5423
Typical Performance Curves
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD, QFN EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
3
2.5
2
2.857W
2.703W
QFN32
QFN24
=37°C/W
θ
=35°C/W
JA
θ
JA
1V/DIV
1.5
1
0.5
0
0
25
50
75 85 100
125
150
1µs/DIV
AMBIENT TEMPERATURE (°C)
FIGURE 19. LARGE SIGNAL TRANSIENT RESPONSE
FIGURE 20. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-3 AND SEMI G42-88
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
(SINGLE LAYER) TEST BOARD
CONDUCTIVITY TEST BOARD
0.8
1.4
758mW
1.333W
0.7
1.2
714mW
1.176W
0.6
TSSOP24
=85°C/W
1.111W
1
QFN32
=132°C/W
JA
θ
JA
0.5
0.4
0.3
0.2
0.1
0
QFN24
=140°C/W
θ
0.8 870mW
θ
TSSOP28
=75°C/W
JA
θ
JA
0.6
TSSOP20
θ
=95°C/W
JA
0.4
0.2
0
MSOP10
θ
=115°C/W
JA
0
25
50
75 85 100
125
150
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 22. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0.9
833mW
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
781mW
TSSOP24
=128°C/W
714mW
486mW
θ
JA
TSSOP28
=120°C/W
θ
JA
MSOP10
=206°C/W
θ
JA
TSSOP20
=140°C/W
θ
JA
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 23. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FN7176.1
November 19, 2004
10
EL5123, EL5223, EL5323, EL5423
exceeds ±30mA. This limit is set by the design of the internal
metal interconnects.
Applications Information
Product Description
Output Phase Reversal
The EL5123, EL5223, EL5323, and EL5423 unity gain
buffers are fabricated using a high voltage CMOS process. It
exhibits rail-to-rail input and output capability and has low
power consumption (600µA per buffer). These features
make the EL5123, EL5223, EL5323, and EL5423 ideal for a
wide range of general-purpose applications. When driving a
load of 10kΩ and 12pF, the EL5123, EL5223, EL5323, and
EL5423 have a -3dB bandwidth of 12MHz and exhibits
15V/µs slew rate.
The EL5123, EL5223, EL5323, and EL5423 are immune to
phase reversal as long as the input voltage is limited from
V - -0.5V to V + +0.5V. Figure 25 shows a photo of the
S
S
output of the device with the input voltage driven beyond the
supply rails. Although the device's output will not change
phase, the input's over-voltage should be avoided. If an input
voltage exceeds supply voltage by more than 0.6V,
electrostatic protection diodes placed in the input stage of
the device begin to conduct and over-voltage damage could
occur.
Operating Voltage, Input, and Output
The EL5123, EL5223, EL5323, and EL5423 are specified
with a single nominal supply voltage from 5V to 15V or a split
supply with its total range from 5V to 15V. Correct operation
is guaranteed for a supply range of 4.5V to 16.5V. Most
EL5123, EL5223, EL5323, and EL5423 specifications are
stable over both the full supply range and operating
temperatures of -40°C to +85°C. Parameter variations with
operating voltage and/or temperature are shown in the
typical performance curves.
1V
10µs
V =±2.5V
S
The output swings of the EL5123, EL5223, EL5323, and
EL5423 typically extend to within 50mV of positive and
negative supply rails with load currents of 5mA. Decreasing
load currents will extend the output voltage range even
closer to the supply rails. Figure 24shows the input and
output waveforms for the device. Operation is from ±5V
supply with a 10kΩ load connected to GND. The input is a
T =25°C
A
IN
V
=6V
P-P
1V
FIGURE 25. OPERATION WITH BEYOND-THE-RAILS INPUT
Power Dissipation
With the high-output drive capability of the EL5123, EL5223,
EL5323, and EL5423 buffer, it is possible to exceed the
125°C “absolute-maximum junction temperature” under
certain load current conditions. Therefore, it is important to
calculate the maximum junction temperature for the
application to determine if load conditions need to be
modified for the buffer to remain in the safe operating area.
10V
9.985V
sinusoid. The output voltage is approximately
P-P
.
P-P
5V
10µs
V =±5V
S
T =25°C
A
V
=10V
IN
P-P
The maximum power dissipation allowed in a package is
determined according to:
T
– T
AMAX
JMAX
--------------------------------------------
P
=
DMAX
dΘ
JA
5V
where:
T
= Maximum junction temperature
= Maximum ambient temperature
JMAX
FIGURE 24. OPERATION WITH RAIL-TO-RAIL INPUT AND
OUTPUT
T
AMAX
θ
= Thermal resistance of the package
JA
Short Circuit Current Limit
P
= Maximum power dissipation in the package
The EL5123, EL5223, EL5323, and EL5423 will limit the
short circuit current to ±120mA if the output is directly
shorted to the positive or the negative supply. If an output is
shorted indefinitely, the power dissipation could easily
increase such that the device may be damaged. Maximum
reliability is maintained if the output continuous current never
DMAX
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the loads, or:
P
= Σi[V × I
+ (V + – V
i) × I
i]
LOAD
DMAX
S
SMAX
S
OUT
FN7176.1
November 19, 2004
11
EL5123, EL5223, EL5323, EL5423
when sourcing, and
Power Supply Bypassing and Printed Circuit
Board Layout
P
= Σi[V × I
+ (V
i – V -) × I
i]
LOAD
DMAX
S
SMAX
OUT
S
As with any high frequency device, good printed circuit
board layout is necessary for optimum performance. Ground
plane construction is highly recommended, lead lengths
should be as short as possible, and the power supply pins
must be well bypassed to reduce the risk of oscillation. For
when sinking.
where:
i = 1 to Total number of buffers
V = Total supply voltage
normal single supply operation, where the V - pin is
S
connected to ground, a 0.1µF ceramic capacitor should be
S
placed from V + pin to ground. A 4.7µF tantalum capacitor
S
I
= Maximum quiescent current per channel
SMAX
should then be connected from V + pin to ground. One
S
4.7µF capacitor may be used for multiple devices. This same
capacitor combination should be placed at each supply pin
to ground if split supplies are to be used.
V
i = Maximum output voltage of the application
OUT
I
i = Load current
LOAD
If we set the two P
DMAX
equations equal to each other, we
can solve for R
i to avoid device overheat. The package
LOAD
power dissipation curves provide a convenient way to see if
the device will overheat. The maximum safe power
dissipation can be found graphically, based on the package
type and the ambient temperature. By using the previous
equation, it is a simple matter to see if P
device's power derating curves.
exceeds the
DMAX
Unused Buffers
It is recommended that any unused buffer have the input tied
to the ground plane.
Driving Capacitive Loads
The EL5123, EL5223, EL5323, and EL5423 can drive a wide
range of capacitive loads. As load capacitance increases,
however, the -3dB bandwidth of the device will decrease and
the peaking increase. The buffers drive 10pF loads in
parallel with 10kΩ with just 1.5dB of peaking, and 100pF
with 6.4dB of peaking. If less peaking is desired in these
applications, a small series resistor (usually between 5Ω and
50Ω) can be placed in series with the output. However, this
will obviously reduce the gain slightly. Another method of
reducing peaking is to add a “snubber” circuit at the output.
A snubber is a shunt load consisting of a resistor in series
with a capacitor. Values of 150Ω and 10nF are typical. The
advantage of a snubber is that it does not draw any DC load
current or reduce the gain.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7176.1
November 19, 2004
12
相关型号：
EL5424CL-T13
13 BUFFER AMPLIFIER, PQCC32, 0.90 MM HEIGHT, EXPOSED PAD, PLASTIC, MO-220, LPP-32
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