EL5524 [INTERSIL]
Integrated Buffers with VCOM; 集成缓冲器，具有VCOM
| 型号： | EL5524 |
| 厂家： | 
Intersil |
| 描述： | Integrated Buffers with VCOM |
| 文件： | 总11页 (文件大小：380K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EL5524, EL5624, EL5724, EL5824
®
Data Sheet
COM
May 23, 2005
FN7346.1
Integrated Buffers with V
Features
The EL5524, EL5624, EL5724, and EL5824 integrate a
• 4 x gamma buffers (EL5524)
• 6 x gamma buffers (EL5624)
• 8 x gamma buffers (EL5724)
• 10 x gamma buffers (EL5824)
number of gamma reference buffers with a single V
COM
amplifier. The EL5524 contains 4 gamma buffers, the
EL5624 contains 6, the EL5724 contains 8, and the EL5824
contains 10. Each gamma buffer has a bandwidth of 12MHz
and features a slew rate of 15V/µs. The output current is
rated at 30mA continuous, 140mA peak.
• Single V
COM
amplifier
output current
• 140mA max V
COM
The V
COM
amplifiers are rated for 60mA continuous output
current and 200mA peak. They also feature higher slew rate
and bandwidth for use in error cancellation circuits.
• Low power
- 5.4mA (EL5524)
- 6.8mA (EL5624)
- 8.3mA (EL5724)
- 9.5mA (EL5824)
The EL5524 is available in the 14-pin HTSSOP package, the
EL5624 in the 20-pin HTSSOP package, the EL5724 in the
24-pin HTSSOP package, and the EL5824 in the 28-pin
HTSSOP package. All are specified for operation over the
-40°C to +85°C temperature range.
• Pb-Free plus Anneal available (RoHS compliant)
Applications
• TFT-LCD displays
• Flat panel monitors
• Notebook displays
• LCD-TVs
Ordering Information (Continued)
Ordering Information
TAPE &
TAPE &
PART NUMBER
EL5724IRE-T13
PACKAGE
24-Pin HTSSOP
REEL
13"
-
PKG. DWG. #
MDP0048
PART NUMBER
EL5524IRE
PACKAGE
REEL
PKG. DWG. #
MDP0048
MDP0048
MDP0048
MDP0048
14-Pin HTSSOP
14-Pin HTSSOP
14-Pin HTSSOP
-
7"
13"
-
EL5724IREZ
(See Note)
24-Pin HTSSOP
(Pb-free)
MDP0048
EL5524IRE-T7
EL5524IRE-T13
EL5724IREZ-T7
(See Note)
24-Pin HTSSOP
(Pb-free)
7"
MDP0048
MDP0048
EL5524IREZ
(See Note)
14-Pin HTSSOP
(Pb-free)
EL5724IREZ-T13 24-Pin HTSSOP
13"
EL5524IREZ-T7
(See Note)
14-Pin HTSSOP
(Pb-free)
7"
MDP0048
MDP0048
(See Note)
(Pb-free)
EL5824IRE
28-Pin HTSSOP
28-Pin HTSSOP
28-Pin HTSSOP
-
7"
13"
-
MDP0048
MDP0048
MDP0048
MDP0048
EL5524IREZ-T13 14-Pin HTSSOP
13"
EL5824IRE-T7
EL5824IRE-T13
(See Note)
(Pb-free)
EL5624IRE
20-Pin HTSSOP
20-Pin HTSSOP
20-Pin HTSSOP
-
7"
13"
-
MDP0048
MDP0048
MDP0048
MDP0048
EL5824IREZ
(See Note)
28-Pin HTSSOP
(Pb-free)
EL5624IRE-T7
EL5624IRE-T13
EL5824IREZ-T7
(See Note)
28-Pin HTSSOP
(Pb-free)
7"
MDP0048
MDP0048
EL5624IREZ
(See Note)
20-Pin HTSSOP
(Pb-free)
EL5824IREZ-T13 28-Pin HTSSOP
(See Note) (Pb-free)
13"
EL5624IREZ-T7
(See Note)
20-Pin HTSSOP
(Pb-free)
7"
MDP0048
MDP0048
NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both
SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.
EL5624IREZ-T13 20-Pin HTSSOP
13"
(See Note)
(Pb-free)
EL5724IRE
EL5724IRE-T7
24-Pin HTSSOP
24-Pin HTSSOP
-
MDP0048
MDP0048
7"
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2003, 2005. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
EL5524, EL5624, EL5724, EL5824
Pinouts
EL5524
(14-PIN HTSSOP)
TOP VIEW
EL5624
(20-PIN HTSSOP)
TOP VIEW
VIN1
VIN2
VIN3
VIN4
VS+
1
2
3
4
5
6
7
14 VOUT1
VIN1
1
2
3
4
5
6
7
8
9
20 VOUT1
13 VOUT2
12 VOUT3
11 VOUT4
10 VS-
VIN2
VIN3
VIN4
VS+
19 VOUT2
18 VOUT3
17 VOUT4
16 VS-
THERMAL
PAD
THERMAL
PAD
VINP
VINN
9
8
VOUT
NC
VS+
15 VS-
VIN5
VIN6
VINP
14 VOUT5
13 VOUT6
12 VOUT
11 NC
VINN 10
EL5724
EL5824
(24-PIN HTSSOP)
(28-PIN HTSSOP)
TOP VIEW
TOP VIEW
VIN1
VIN2
VIN3
VIN4
VIN5
VS+
1
2
3
4
5
6
7
8
9
24 VOUT1
23 VOUT2
22 VOUT3
21 VOUT4
20 VOUT5
19 VS-
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VS+
1
2
3
4
5
6
7
8
9
28 VOUT1
27 VOUT2
26 VOUT3
25 VOUT4
24 VOUT5
23 VOUT6
22 VS-
THERMAL
PAD
VS+
18 VS-
THERMAL
PAD
VIN6
VIN7
17 VOUT6
16 VOUT7
15 VOUT8
14 VOUT
13 NC
VS+
21 VS-
VIN7
20 VOUT7
19 VOUT8
18 VOUT9
17 VOUT10
16 VOUT
15 NC
VIN8 10
VINP 11
VINN 12
VIN8 10
VIN9 11
VIN10 12
VINP 13
VINN 14
2
EL5524, EL5624, EL5724, EL5824
Absolute Maximum Ratings (T = 25°C)
A
Supply Voltage between V + and V -. . . . . . . . . . . . . . . . . . . .+18V
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
S
S
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . .V - -0.5V, V + +0.5V
S
S
Maximum Continuous Output Current (Buffer) . . . . . . . . . . . . 30mA
Maximum Continuous Output Current (V ) . . . . . . . . . . . . 60mA
COM
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T = T = T
A
J
C
Electrical Specifications V + = +15V, V - = 0, R = 10kΩ, C = 10pF to 0V, Gain of V
= 1, RLV
= 1kΩ and
S
S
L
L
COM
CM
T
= 25°C Unless Otherwise Specified
A
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
14
UNIT
INPUT CHARACTERISTICS (REFERENCE BUFFERS)
V
Input Offset Voltage
Average Offset Voltage Drift
Input Bias Current
Input Impedance
V
= 0V
2
5
mV
µV/°C
nA
OS
TCV
CM
(Note 1)
= 0V
OS
I
V
2
50
B
CM
R
C
1
GΩ
IN
IN
Input Capacitance
Voltage Gain
1.35
pF
A
1V ≤ V
≤ 14V
OUT
0.992
1.008
15
V/V
V
INPUT CHARACTERISTICS (V
AMPLIFIER)
COM
Input Offset Voltage
V
V
= 7.5V
1
5
mV
µV/°C
nA
OS
TCV
CM
(Note 1)
Average Offset Voltage Drift
Input Bias Current
Input Impedance
OS
I
V
= 7.5V
2
50
B
CM
R
C
1
GΩ
pF
IN
IN
Input Capacitance
Load Regulation
1.35
V
V
= 1.5V, -60mA < I < 60mA
-20
55
+20
150
150
mV
dB
REG
COM
L
A
Open Loop Gain
R
= 1kΩ
L
75
70
VOL
CMRR
Common Rejection Ratio
45
dB
OUTPUT CHARACTERISTICS (REFERENCE BUFFERS)
V
V
Output Swing Low
Output Swing High
Short Circuit Current
I = 7.5mA
50
mV
V
OL
L
I = 7.5mA
14.85
±120
14.95
±140
OH
L
I
R
= 10Ω
L
mA
SC
OUTPUT CHARACTERISTICS (V
AMPLIFIER)
COM
Output Swing Low
V
V
I = -7.5mA
50
mV
V
OL
L
Output Swing High
Short Circuit Current
I = +7.5mA
14.85
±180
14.95
±200
OH
L
I
R
= 10Ω
L
mA
SC
POWER SUPPLY PERFORMANCE
PSRR Power Supply Rejection Ratio
Reference buffer V from 4.5V to 15.5V
55
55
80
80
dB
dB
S
V
buffer, V from 4.5V to 15.5V
S
COM
I
Total Supply Current
EL5524 (no load)
EL5624 (no load)
EL5724 (no load)
EL5824 (no load)
5.4
6.8
8.3
9.5
7
mA
mA
mA
mA
S
8.5
11
12.5
3
EL5524, EL5624, EL5724, EL5824
Electrical Specifications V + = +15V, V - = 0, R = 10kΩ, C = 10pF to 0V, Gain of V
= 1, RLV
= 1kΩ and
S
S
L
L
COM
CM
T
= 25°C Unless Otherwise Specified (Continued)
A
PARAMETER
DYNAMIC PERFORMANCE (BUFFER AMPLIFIERS)
SR Slew Rate (Note 2)
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
-4V ≤ V
≤ 4V, 20% to 80%
7
15
250
12
8
V/µs
ns
OUT
t
Settling to +0.1% (A = +1)
V
(A = +1), V = 2V step
V O
S
BW
-3dB Bandwidth
R
R
R
= 10kΩ, C = 10pF
MHz
MHz
°
L
L
L
L
GBWP
PM
Gain-Bandwidth Product
Phase Margin
= 10kΩ, C = 10pF
L
= 10kΩ, C = 10pF
50
75
L
CS
Channel Separation
f = 5MHz
dB
DYNAMIC PERFORMANCE (V
AMPLIFIERS)
COM
Slew Rate (Note 2)
SR
-4V ≤ V
≤ 4V, 20% to 80%
65
90
150
35
V/µs
ns
OUT
(A = +1), V = 6V step
t
Settling to +0.1% (A = +1)
V
S
V
O
BW
-3dB Bandwidth
R
R
R
= 1kΩ, C = 2pF
MHz
MHz
°
L
L
L
L
GBWP
PM
Gain-Bandwidth Product
Phase Margin
= 1kΩ, C = 2pF
20
L
= 1kΩ, C = 2pF
50
L
NOTES:
1. Measured over operating temperature range
2. Slew rate is measured on rising and falling edges
4
EL5524, EL5624, EL5724, EL5824
Pin Descriptions
EL5524
EL5624
EL5724
1
EL5824
1
PIN NAME
VIN1
PIN FUNCTION
1
2
1
2
Input
2
2
VIN2
Input
3
3
3
3
VIN3
Input
4
4
4
4
VIN4
Input
5
5, 6
9
6, 7
11
12
13
14
18, 19
21
22
23
24
5
7, 8
13
14
15
16
21, 22
25
26
27
28
5
VS+
Positive supply
Positive input - V
6
VINP
COM
7
10
11
12
15, 16
17
18
19
20
7
VINN
Negative input - V
Not connected
COM
8
NC
9
VOUT
VS-
Output for V
COM
10
11
12
13
14
Negative supply
Output
Output
Output
Output
Input
VOUT4
VOUT3
VOUT2
VOUT1
VIN5
8
8
6
VIN6
Input
14
13
20
17
9
24
23
9
VOUT5
VOUT6
VIN7
Output
Output
Input
10
16
15
10
20
19
11
12
18
17
VIN8
Input
VOUT7
VOUT8
VIN9
Output
Output
Input
VIN10
VOUT9
VONT10
Input
Output
Output
Test Circuits
V
V
V
V
IN
OUT
IN
OUT
+
-
10kΩ
1kΩ
50Ω
50Ω
10pF
2pF
FOR V
COM
FOR BUFFERS
5
EL5524, EL5624, EL5724, EL5824
Typical Performance Curves
20
20
V =±7.5V
V =±7.5V
S
S
1000pF
C =10pF
R =10kΩ
L
L
10
0
10
0
10kΩ
100pF
1kΩ
12pF
47pF
1M
-10
-20
-30
-10
-20
-30
150Ω
562Ω
100K
1M
10M
100M
100K
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 1. FREQUENCY RESPONSE FOR VARIOUS R
(BUFFER)
FIGURE 2. FREQUENCY RESPONSE FOR VARIOUS C
(BUFFER)
L
L
600
100
V =±7.5V
V =±7.5V
S
S
PSRR+
T =25°C
A
480
360
240
120
0
80
60
40
20
0
PSRR-
100K
1M
10M
100M
1K
10K
100K
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 4. OUTPUT IMPEDANCE vs FREQUENCY (BUFFER)
FIGURE 3. PSRR vs FREQUENCY (BUFFER)
80
V =±7.5V
S
70
60
50
40
30
20
10
0
R =10kΩ
100
10
1
L
V
=100mV
IN
10
100
1K
10K
100K
1M
10M
100M
CAPACITANCE (pF)
FREQUENCY (Hz)
FIGURE 6. OVERSHOOT vs LOAD CAPACITANCE (BUFFER)
FIGURE 5. INPUT NOISE SPECIAL DENSITY vs FREQUENCY
(BUFFER)
6
EL5524, EL5624, EL5724, EL5824
Typical Performance Curves (Continued)
10
8
6
4
2
0.018
0.016
0.014
0.012
0.01
V =±7.5V
V =±5V
S
S
R =10kΩ
R =10kΩ
L
L
C =12pF
L
V =2V
IN P-P
0
-2
-4
-6
-8
-10
0.008
0.006
200 250 300 350 400 450 500 550 600 650
SETTLING TIME (ns)
1K
10K
100K
FREQUENCY (Hz)
FIGURE 7. SETTLING TIME vs STEP SIZE (BUFFER)
FIGURE 8. TOTAL HARMONIC DISTORTION + NOISE vs
FREQUENCY (BUFFER)
4
12
10
8
A =1
V
2
0
A =2
V
6
-2
-4
-6
A =10
V
4
A =5
V
V =±7.5V
S
2
R =1kΩ
L
V =±5V
S
C =2pF
L
R =10kΩ
L
0
100K
1M
10M
100M
10K
100K
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 10. FREQUENCY RESPONSE (V
COM
)
FIGURE 9. OUTPUT SWING vs FREQUENCY (BUFFER)
M=1µs/DIV, V =±7.5V, V =0V
IN
S
70
50
0
0mA
5mA
5mA/DIV
-72
PHASE
R =0Ω
S
30
-144
-216
-288
-360
C =200pF
L
GAIN
0V
500mV/DIV
10
R =10Ω
S
C =4.7nF
L
V =±5V
S
R =10Ω
S
R =1kΩ
F
-10
C =1nF
L
R =1kΩ
L
C =1.5pF
L
-30
1K
10K
100K
1M
10M
100M
FREQUENCY (Hz)
FIGURE 12. TRANSIENT LOAD REGULATION - SOURCING
(BUFFER)
FIGURE 11. OPEN LOOP GAIN AND PHASE vs FREQUENCY
7
EL5524, EL5624, EL5724, EL5824
Typical Performance Curves (Continued)
V =±7.5V, R =200Ω, C =150pF
M=1µs/DIV, V =±7.5V, V =0V
IN
S
L
L
S
50mA
0mA
5mA
0mA
5mA/DIV
R =10Ω
S
-50mA
C =1nF
L
0V
500mV/DIV
R =0Ω
R =10Ω
S
S
C =200pF
C =4.7nF
L
L
FIGURE 14. TRANSIENT LOAD REGULATION (V
)
FIGURE 13. TRANSIENT LOAD REGULATION - SINKING
(BUFFER)
COM
V =±7.5V
S
V =±7.5V, R =10kΩ, C =12pF
S
L
L
1V/DIV
50mV/DIV
1µs/DIV
200ns/DIV
FIGURE 16. LARGE SIGNAL TRANSIENT RESPONSE
(BUFFER)
FIGURE 15. SMALL SIGNAL TRANSIENT RESPONSE
(BUFFER)
1
V =±7.5V, R =1kΩ, C =2pF
S
L
L
V =±7.5V, R =1kΩ, C =2pF
S
L
L
100mV/DIV
1V/DIV
100ns/DIV
100ns/DIV
FIGURE 17. SMALL SIGNAL TRANSIENT RESPONSE (V
)
COM
FIGURE 18. LARGE SIGNAL TRANSIENT REPONSE (V
)
COM
8
EL5524, EL5624, EL5724, EL5824
Typical Performance Curves (Continued)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD -
HTSSOP EXPOSED DIEPAD SOLDERED TO
PCB PER JESD51-5
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
1
0.9
3.5
3
909mW
3.333W
3.030W
2.857W
833mW
0.8
800mW
694mW
HTSSOP28
JA
2.5
2
HTSSOP24
2.632W
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
θ
=110°C/W
θ
=33°C/W
JA
HTSSOP24
JA
HTSSOP28
JA
θ
=120°C/W
HTSSOP20
=125°C/W
HTSSOP20
=35°C/W
1.5
1
θ
=30°C/W
θ
θ
JA
JA
HTSSOP14
=38°C/W
HTSSOP14
JA
0.5
0
θ
θ
=144°C/W
JA
0
25
50
75 85 100
125
150
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 20. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 19. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Choice of Feedback Resistor and Gain Bandwidth
Description of Operation and Application
Information
Product Description
The EL5524, EL5624, EL5724, and EL5824 are fabricated
using a high voltage CMOS process. They exhibit rail to rail
input and output capability and have very low power
consumption. When driving a load of 10K and 12pF, the
buffers have a -3dB bandwidth of 12MHz and exhibit 18V/µs
Product for V
Amplifier
COM
For applications that require a gain of +1, no feedback
resistor is required. Just short the output pin to the inverting
input pin. For gains greater than +1, the feedback resistor
forms a pole with the parasitic capacitance at the inverting
input. As this pole becomes smaller, the amplifier's phase
margin is reduced. This causes ringing in the time domain
and peaking in the frequency domain. Therefore, R has
F
slew rate. The V
amplifier has a -3dB bandwidth of
some maximum value that should not be exceeded for
COM
35MHz and exhibit 80V/µs slew rate.
optimum performance. If a large value of R must be used, a
F
small capacitor in the few Pico farad range in parallel with R
can help to reduce the ringing and peaking at the expense of
reducing the bandwidth.
F
Input, Output, and Supply Voltage Range
The EL5524, EL5624, EL5724, and EL5824 are specified
with a single nominal supply voltage from 5V to 15V or a split
supply with its total range from 5V to 15V. Correct operation
is guaranteed for a supply range from 4.5V to 16.5V.
As far as the output stage of the amplifier is concerned, the
output stage is also a gain stage with the load. R and R
F
G
appear in parallel with R for gains other than +1. As this
L
The input common-mode voltage range of the EL5524,
EL5624, EL5724, and EL5824 extends 500mV beyond the
combination gets smaller, the bandwidth falls off.
Consequently, R also has a minimum value that should not
F
supply rails. The output swings of the buffers and V
COM
be exceeded for optimum performance. For gain of +1, R =
F
amplifier typically extend to within 100mV of the positive and
negative supply rails with load currents of 5mA. Decreasing
load currents will extend the output voltage even closer to
each supply rails.
0 is optimum. For the gains other than +1, optimum
response is obtained with R between 1kΩ to 5kΩ.
F
The V
COM
amplifier has a gain bandwidth product of
20MHz. For gains ≥5, its bandwidth can be predicted by the
Output Phase Reversal
following equation:
The EL5524, EL5624, EL5724, and EL5824 are immune to
phase reversal as long as the input voltage is limited from
Gain × BW = 20MHz
V - -0.5V to V + +0.5V. Although the device's output will not
S
S
change phase, the input's overvoltage should be avoided. If
an input voltage exceeds supply voltage by more than 0.6V,
electrostatic protection diode placed in the input stage of the
device begin to conduct and overvoltage damage could
occur.
Output Drive Capability
The EL5524, EL5624, EL5724, and EL5824 do not have
internal short-circuit protection circuitry. The buffers will limit
the short circuit current to ±120mA and the V
amplifier
COM
9
EL5524, EL5624, EL5724, EL5824
will limit the short circuit current to ±200mA if the outputs are
where:
directly shorted to the positive or the negative supply. If the
output is shorted indefinitely, the power dissipation could
easily increase such that the part will be destroyed.
• i = 1 to total number of buffers
• V = Total supply voltage of buffer and V
S
COM
Maximum reliability is maintained if the output continuous
current never exceeds ±30mA for the buffers and ±60mA for
• I
= Total quiescent current
SMAX
• V
• V
i = Maximum output voltage of the application
OUT
OUT
the V
amplifier. These limits are set by the design of the
COM
internal metal interconnections.
= Maximum output voltage of V
i = Load current of buffer
COM
The Unused Buffers
• I
LOAD
It is recommended that any unused buffers should have their
inputs tied to ground plane.
• I = Load current of V
LA COM
If we set the two P
DMAX
equations equal to each other, we
's to avoid device overheat. The
Power Dissipation
can solve for the R
LOAD
package power dissipation curves provide a convenient way
to see if the device will overheat. The maximum safe power
dissipation can be found graphically, based on the package
type and the ambient temperature. By using the previous
With the high-output drive capability of the EL5524, EL5624,
EL5724, and EL5824, it is possible to exceed the 125°C
“absolute-maximum junction temperature” under certain load
current conditions. Therefore, it is important to calculate the
maximum junction temperature for the application to
determine if load conditions need to be modified for the
buffer to remain in the safe operating area.
equation, it is a simple matter to see if P
device's power derating curves.
exceeds the
DMAX
Power Supply Bypassing and Printed Circuit
Board Layout
The maximum power dissipation allowed in a package is
determined according to:
As with any high frequency device, good printed circuit
board layout is necessary for optimum performance. Ground
plane construction is highly recommended, lead lengths
should be as short as possible, and the power supply pins
must be well bypassed to reduce the risk of oscillation. For
T
- T
AMAX
JMAX
P
= --------------------------------------------
DMAX
Θ
JA
where:
• T
normal single supply operation, where the V - pin is
S
= Maximum junction temperature
connected to ground, one 0.1µF ceramic capacitor should be
JMAX
placed from the V + pin to ground. A 4.7µF tantalum
S
• T
AMAX
= Maximum ambient temperature
capacitor should then be connected from the V + pin to
S
• θ = Thermal resistance of the package
JA
ground. One 4.7µF capacitor may be used for multiple
devices. This same capacitor combination should be placed
at each supply pin to ground if split supplies are to be used.
• P
DMAX
= Maximum power dissipation in the package
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the loads, or:
Important Note: The metal plane used for heat sinking of
the device is electrically connected to the negative
supply potential (V -). If V - is tied to ground, the
S
S
P
= V × I + Σi × [(V + – V
i) × I
i] +
LOAD
thermal pad can be connected to ground. Otherwise, the
thermal pad must be isolated from any other power
planes.
DMAX
S
S
S
OUT
(V + – V
) × I
S
OUT
LA
when sourcing, and:
P
= V × I + Σi × [(V
i – V -) × I
i] +
LOAD
DMAX
S
S
OUT
S
(V
– V -) × I
OUT
S
LA
when sinking.
10
EL5524, EL5624, EL5724, EL5824
HTSSOP Package Outline Drawing
NOTE: The package drawings shown here may not be the latest versions. For the latest revisions, please refer to the Intersil website at
www.intersil.com/design/packages/elantec
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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