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EL7531_06 [INTERSIL]

Monolithic 1A Step-Down Regulator with Low Quiescent Current; 单片1A降压型稳压器具有低静态电流
EL7531_06
型号： EL7531_06
厂家： Intersil    Intersil
描述：

Monolithic 1A Step-Down Regulator with Low Quiescent Current
单片1A降压型稳压器具有低静态电流

稳压器
文件： 总11页 (文件大小：344K)
中文：  中文翻译
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EL7531  
®
Data Sheet  
July 13, 2006  
FN7428.9  
Monolithic 1A Step-Down Regulator with  
Low Quiescent Current  
Features  
2
2
• Less than 0.15 in (0.97 cm ) footprint for the complete 1A  
converter  
The EL7531 is a synchronous, integrated FET 1A step-down  
regulator with internal compensation. It operates with an input  
voltage range from 2.5V to 5.5V, which accommodates  
supplies of 3.3V, 5V, or a Li-Ion battery source. The output can  
• Components on one side of PCB  
• Max height 1.1mm MSOP10  
be externally set from 0.8V to V with a resistive divider.  
IN  
• Power-Good (PG) output  
The EL7531 features automatic PFM/PWM mode control, or  
PWM mode only. The PWM frequency is typically 1.4MHz  
and can be synchronized up to 12MHz. The typical no load  
quiescent current is only 120µA. Additional features include  
a Power-Good output, <1µA shut-down current, short-circuit  
protection, and over-temperature protection.  
• Internally-compensated voltage mode controller  
• Up to 94% efficiency  
• <1µA shut-down current  
• 120µA quiescent current  
• Overcurrent and over-temperature protection  
• External synchronizable up to 12MHz  
• Pb-Free plus anneal available (RoHS compliant)  
The EL7531 is available in the 10 Ld MSOP package,  
2
making the entire converter occupy less than 0.15 in of  
PCB area with components on one side only. The 10 Ld  
MSOP package is specified for operation over the full -40°C  
to +85°C temperature range.  
Applications  
• PDA and pocket PC computers  
• Bar code readers  
Ordering Information  
PART  
TAPE &  
REEL  
PKG.  
DWG. #  
PART NUMBER MARKING  
PACKAGE  
10 Ld MSOP  
10 Ld MSOP  
10 Ld MSOP  
• Cellular phones  
EL7531IY  
BEAAA  
BEAAA  
BEAAA  
BHAAA  
-
7”  
13”  
-
MDP0043  
MDP0043  
MDP0043  
MDP0043  
• Portable test equipment  
• Li-Ion battery powered devices  
• Small form factor (SFP) modules  
EL7531IY-T7  
EL7531IY-T13  
EL7531IYZ  
(Note)  
10 Ld MSOP  
(Pb-free)  
Typical Application Diagram  
EL7531IYZ-T7  
(Note)  
BHAAA  
7”  
10 Ld MSOP  
(Pb-free)  
MDP0043  
MDP0043  
EL7531  
TOP VIEW  
EL7531IYZ-T13 BHAAA  
(Note)  
13”  
10 Ld MSOP  
(Pb-free)  
V
V
(2.5V to 5.5V)  
L
1
O
S
VIN  
LX  
NOTE: Intersil Pb-free plus anneal products employ special Pb-free  
material sets; molding compounds/die attach materials and 100% matte  
tin plate termination finish, which are RoHS compliant and compatible  
with both SnPb and Pb-free soldering operations. Intersil Pb-free  
products are MSL classified at Pb-free peak reflow temperatures that  
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.  
1.8µH  
R
100Ω  
3
C
10µF  
1
VDD  
C
10µF  
C
3
2
0.1µF  
EL7531  
R
R
100kΩ  
5
4
R *  
1
124kΩ  
PG  
EN  
C
Pinout  
4
FB  
VO  
470pF  
EL7531 (10 LD MSOP)  
100kΩ  
SYNC  
R *  
2
100kΩ  
TOP VIEW  
R
6
100kΩ  
PGND  
SGND  
SGND  
PGND  
LX  
FB  
VO  
1
2
3
4
5
10  
9
(1.8V @ 1A)  
PG  
8
* V = 0.8V * (1 + R / R )  
O
1
2
VIN  
EN  
7
6
VDD  
SYNC  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
Copyright © Intersil Americas Inc. 2004, 2005, 2006. All Rights Reserved.  
1
All other trademarks mentioned are the property of their respective owners.  
EL7531  
Absolute Maximum Ratings (T = 25°C)  
A
V
, V , PG to SGND . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V  
IN DD  
Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2A  
Operating Ambient Temperature . . . . . . . . . . . . . . . .-40°C to +85°C  
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C  
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C  
LX to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (V + +0.3V)  
SYNC, EN, V , FB to SGND. . . . . . . . . . . . . -0.3V to (V + +0.3V)  
IN  
PGND to SGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V  
IN  
O
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the  
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are  
at the specified temperature and are pulsed tests, therefore: T = T = T  
A
J
C
Electrical Specifications  
V
= V = V  
IN  
= 3.3V, C1 = C2 = 10µF, L = 1.8µH, V = 1.8V (as shown in Typical Application Diagram),  
EN O  
DD  
unless otherwise specified.  
PARAMETER  
DESCRIPTION  
CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
DC CHARACTERISTICS  
V
Feedback Input Voltage  
vs Temperature  
PWM mode  
790  
800  
0.3  
810  
mV  
%
FB  
/V  
∆V  
V
Junction temperature = -40°C to +85°C  
(see Figure 7)  
OUT OUT  
FB  
∆V  
∆V  
/V  
OUT OUT  
Line Regulation  
V
= 3.3V to 5V, I = 1A (see Figure 7)  
0.1  
0.4  
%
%
nA  
V
IN  
I = 0A to 1A, V = 3.3V (see Figure 7)  
O
O
/V  
OUT OUT  
Load Regulation  
IN  
I
Feedback Input Current  
Input Voltage  
100  
5.5  
2.2  
2.4  
FB  
V
, V  
2.5  
2
IN DD  
V
Minimum Voltage for Shutdown  
Maximum Voltage for Startup  
Input Supply Quiescent Current  
Active - PFM Mode  
V
V
falling  
rising  
V
IN,OFF  
IN  
IN  
V
2.2  
V
IN,ON  
I
S
V
V
= 0V  
120  
6.5  
400  
0.1  
70  
145  
7.5  
500  
1
µA  
mA  
µA  
µA  
mΩ  
mΩ  
A
SYNC  
SYNC  
Active - PWM Mode  
Supply Current  
= 3.3V  
I
PWM, V = V  
IN DD  
= 5V  
= 5V  
DD  
EN = 0, V = V  
IN  
DD  
R
PMOS FET Resistance  
NMOS FET Resistance  
Current Limit  
V
= 5V, wafer test only  
= 5V, wafer test only  
100  
75  
DS(ON)-PMOS  
DD  
DD  
R
V
45  
DS(ON)-NMOS  
I
1.5  
145  
130  
LMAX  
T
Over-temperature Threshold  
Over-temperature Hysteresis  
EN, SYNC Current  
T rising  
T falling  
°C  
°C  
µA  
V
OT,OFF  
T
OT,ON  
, I  
I
V
V
V
V
V
, V  
EN RSI  
= 0V and 3.3V  
-1  
2.4  
9
1
EN SYNC  
, V  
V
V
EN, SYNC Rising Threshold  
EN, SYNC Falling Threshold  
= 3.3V  
= 3.3V  
rising  
1.8  
1.4  
EN1 SYNC1  
, V  
DD  
DD  
0.8  
95  
V
EN2 SYNC2  
V
Minimum V for PG, WRT Targeted  
FB  
%
PG  
FB  
V
Value  
FB  
falling  
86  
%
FB  
V
PG Voltage Drop  
I
= 3.3mA  
35  
1.4  
650  
70  
mV  
OLPG  
SINK  
AC CHARACTERISTICS  
F
PWM Switching Frequency  
Minimum SYNC Pulse Width  
Soft-start Time  
1.25  
25  
1.6  
MHz  
ns  
PWM  
t
Guaranteed by design  
SYNC  
t
µs  
SS  
FN7428.9  
July 13, 2006  
2
EL7531  
Pin Descriptions  
PIN NUMBER  
PIN NAME  
PIN FUNCTION  
1
2
3
4
5
6
SGND  
PGND  
LX  
Negative supply for the controller stage  
Negative supply for the power stage  
Inductor drive pin; high current digital output with average voltage equal to the regulator output voltage  
Positive supply for the power stage  
VIN  
VDD  
SYNC  
Power supply for the controller stage  
SYNC input pin; when connected to HI, regulator runs at forced PWM mode; when connected to Low, auto  
PFM/PWM mode; when connected to external sync signal, at external PWM frequency up to 12MHz  
7
8
EN  
PG  
VO  
FB  
Enable  
Power-Good open drain output  
Output voltage sense  
9
10  
Voltage feedback input; connected to an external resistor divider between V and SGND for variable  
O
output  
Block Diagram  
100Ω  
V
V
DD  
INDUCTOR SHORT  
+
O
0.1µF  
10pF  
V
IN  
C4  
-
124K  
CURRENT  
SENSE  
470pF  
5M  
FB  
-
+
PWM  
COMPENSATION  
+
-
PWM  
P-DRIVER  
100K  
COMPARATOR  
1.8µH  
LX  
PFM  
ON-TIME  
CONTROL  
SYNC  
EN  
RAMP  
GENERATOR  
CONTROL  
LOGIC  
1.8V  
0 TO 1A  
SYNC  
EN  
CLOCK  
SOFT-  
START  
+
-
10µF  
10µF  
PWM  
N-DRIVER  
COMPARATOR  
UNDER-  
VOLTAGE  
LOCKOUT  
+
3.3V  
–
PGND  
PG  
BANDGAP  
REFERENCE  
+
-
100K  
TEMPERATURE  
SENSE  
SYNCHRONOUS  
RECTIFIER  
PG  
SGND  
POWER  
GOOD  
FN7428.9  
July 13, 2006  
3
EL7531  
Performance Curves and Waveforms  
All waveforms are taken at V = 3.3V, V = 1.8V, I = 1A with component values shown on page 1 at room ambient temperature, unless otherwise  
IN  
O
O
noted.  
100  
95  
90  
85  
80  
75  
70  
65  
60  
55  
50  
45  
40  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
V
= 3.3V  
O
V
= 3.3V  
O
V
= 2.5V  
O
V
= 2.5V  
= 1.8V  
O
V
O
V
= 1.8V  
O
V
= 1.0V  
V
= 1.5V  
O
O
V
= 1.5V  
O
V
= 1.2V  
O
V
= 0.8V  
O
V
= 1.0V  
O
V
= 1.2V  
O
V
= 0.8V  
O
V
= 5V  
V
= 5V  
IN  
IN  
0.001  
0.010  
0.100  
1.000  
0.001  
0.010  
0.100  
1.000  
I
(A)  
O
I (A)  
O
FIGURE 1. EFFICIENCY vs I (PFM/PWM MODE)  
FIGURE 2. EFFICIENCY vs I (PWM MODE)  
O
O
100  
100  
95  
90  
85  
80  
75  
70  
65  
60  
55  
50  
45  
40  
V
= 2.5V  
= 1.8V  
V
= 2.5V  
= 1.8V  
= 1.5V  
O
O
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
O
V
V
O
V
O
V
= 1.2V  
O
V
= 1.5V  
O
V
= 1.2V  
O
V
= 1.0V  
O
V
= 1.0V  
O
V
= 0.8V  
O
V
= 0.8V  
O
V
= 3.3V  
IN  
V
= 3.3V  
IN  
0.001  
0.010  
0.100  
1.000  
0.001  
0.010  
0.100  
1.000  
I
(A)  
I
(A)  
O
O
FIGURE 3. EFFICIENCY vs I (PFM/PWM MODE)  
O
FIGURE 4. EFFICIENCY vs I (PWM MODE)  
O
1.44  
0.1%  
0.0%  
V
= 3.3V I = 1A  
O
IN  
V
= 5V I = 1A  
O
IN  
V
= 5V I = 0A  
O
IN  
1.42  
1.4  
-0.1%  
V
= 3.3V I = 0A  
O
IN  
V
= 3.3V  
IN  
1.38  
1.36  
1.34  
1.32  
-0.2%  
-0.3%  
-0.4%  
-0.5%  
V
= 5V  
IN  
0
0.2  
0.4  
0.6  
0.8  
1
-50  
0
50  
100  
150  
T
(°C)  
A
I (A)  
O
FIGURE 5. F vs JUNCTION TEMPERATURE (PWM MODE)  
S
FIGURE 6. LOAD REGULATIONS (PWM MODE)  
FN7428.9  
July 13, 2006  
4
EL7531  
Performance Curves and Waveforms (Continued)  
All waveforms are taken at V = 3.3V, V = 1.8V, I = 1A with component values shown on page 1 at room ambient temperature, unless otherwise  
IN  
O
O
noted.  
0.1%  
0.0%  
12  
10  
8
V
= 5V I = 0A  
O
IN  
V
= 3.3V I = 0A  
O
IN  
-0.1%  
-0.2%  
-0.3%  
-0.4%  
-0.5%  
V
= 3.3V I = 1A  
6
4
2
0
IN  
O
V
= 5V I = 1A  
O
-0.6%  
-0.7%  
IN  
-50  
0
50  
100  
150  
3.5  
4
4.5  
5
2.5  
3
T
(°C)  
J
V
(V)  
S
FIGURE 7. PWM MODE LOAD/LINE REGULATIONS vs  
JUNCTION TEMPERATURE  
FIGURE 8. NO LOAD QUIESCENT CURRENT (PWM MODE)  
140  
100  
V
= 3.3V  
O
1.4MHz  
130  
V
= 1.8V  
O
120  
110  
100  
80  
5MHz  
12MHz  
60  
40  
20  
0
V
= 1.5V  
O
V
= 1.2V  
= 1.0V  
O
V
O
90  
V
= 0.8V  
O
80  
70  
60  
50  
2.0  
0
200  
400  
600  
800  
1K  
1.2K  
2.5  
3.0  
3.5  
4.0  
4.5  
5.0  
5.5  
6.0  
V
(V)  
I
(mA)  
S
O
FIGURE 9. NO LOAD QUIESCENT CURRENT (PFM MODE)  
FIGURE 10. EFFICIENCY vs I (PWM MODE)  
O
1
0.5  
0.3  
12MHz  
0.6  
1.4MHz  
12MHz  
0.2  
0.1  
5MHz  
1.4MHz  
-0.1  
0
5MHz  
-0.2  
-0.6  
-0.3  
-0.5  
2.5  
0
200  
400  
600  
800  
1K  
1.2K  
3
3.5  
4
4.5  
5
5.5  
I
(mA)  
V
(V)  
O
IN  
FIGURE 11. LOAD REGULATION (PWM MODE)  
FIGURE 12. LINE REGULATION @ 500mA (PWM MODE)  
FN7428.9  
July 13, 2006  
5
EL7531  
Performance Curves and Waveforms (Continued)  
All waveforms are taken at V = 3.3V, V = 1.8V, I = 1A with component values shown on page 1 at room ambient temperature, unless otherwise  
IN  
O
O
noted.  
V
IN  
(2V/DIV)  
EN  
I
IN  
(0.5A/DIV)  
I
IN  
(0.5A/DIV)  
V
O
(2V/DIV)  
V
PG  
O
(2V/DIV)  
PG  
500µs/DIV  
200µs/DIV  
FIGURE 13. START-UP AT I = 1A  
O
FIGURE 14. ENABLE AND SHUT-DOWN  
LX  
(2V/DIV)  
LX  
(2V/DIV)  
I
L
I
(0.5A/DIV)  
L
(0.5A/DIV)  
∆V  
O
∆V  
(10mV/DIV)  
O
(50mV/DIV)  
0.5µs/DIV  
2µs/DIV  
FIGURE 15. PFM STEADY-STATE OPERATION WAVEFORM  
(I = 100mA)  
FIGURE 16. PWM STEADY-STATE OPERATION (I = 1A)  
O
O
SYNC  
(2V/DIV)  
SYNC  
(2V/DIV)  
LX  
LX  
(2V/DIV)  
(2V/DIV)  
I
I
L
L
(0.5A/DIV)  
(0.5A/DIV)  
20ns/DIV  
0.2µs/DIV  
FIGURE 17. EXTERNAL SYNCHRONIZATION TO 2MHz  
FIGURE 18. EXTERNAL SYNCHRONIZATION TO 12MHz  
FN7428.9  
July 13, 2006  
6
EL7531  
Performance Curves and Waveforms (Continued)  
All waveforms are taken at V = 3.3V, V = 1.8V, I = 1A with component values shown on page 1 at room ambient temperature, unless otherwise  
IN  
O
O
noted.  
I
I
O
O
(0.5A/DIV)  
(0.5A/DIV)  
∆V  
∆V  
O
O
(100mV/DIV)  
(100mV/DIV)  
50µs/DIV  
100µs/DIV  
FIGURE 19. LOAD TRANSIENT RESPONSE (22mA to 1A)  
FIGURE 20. PWM LOAD TRANSIENT RESPONSE (0A TO 1A)  
I
=150mA  
O
SYNC  
(2V/DIV)  
I
O
(0.5A/DIV)  
∆V  
O
(100mV/DIV)  
LX  
(2V/DIV)  
2µs/DIV  
50µs/DIV  
FIGURE 21. PWM LOAD TRANSIENT RESPONSE  
(0.25A TO 0.75A)  
FIGURE 22. PFM-PWM TRANSITION TIME  
3
2
I
=50mA  
O
SYNC  
(2V/DIV)  
1
0
-1  
LX  
PFM  
PWM  
600  
(2V/DIV)  
-2  
-3  
0
200  
400  
800  
1000  
1200  
I
(mA)  
2µs/DIV  
OUT  
FIGURE 23. PFM-PWM TRANSITION TIME  
FIGURE 24. PFM-PWM LOAD REGULATION  
FN7428.9  
July 13, 2006  
7
EL7531  
Performance Curves and Waveforms (Continued)  
All waveforms are taken at V = 3.3V, V = 1.8V, I = 1A with component values shown on page 1 at room ambient temperature, unless otherwise  
IN  
O
O
noted.  
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL  
CONDUCTIVITY TEST BOARD  
JEDEC JESD51-3 LOW EFFECTIVE THERMAL  
CONDUCTIVITY TEST BOARD  
1
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
0
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
0
870mW  
486mW  
0
25  
50  
75 85 100  
125  
0
25  
50  
75 85 100  
125  
AMBIENT TEMPERATURE (°C)  
AMBIENT TEMPERATURE (°C)  
FIGURE 26. PACKAGE POWER DISSIPATION vs AMBIENT  
TEMPERATURE  
FIGURE 25. PACKAGE POWER DISSIPATION vs AMBIENT  
TEMPERATURE  
FN7428.9  
July 13, 2006  
8
EL7531  
PWM Operation  
Applications Information  
The regulator operates the same way in the forced PWM or  
synchronized PWM mode. In this mode, the inductor current  
is always continuous and does not stay at zero.  
Product Description  
The EL7531 is a synchronous, integrated FET 1A step-down  
regulator which operates from an input of 2.5V to 5.5V. The  
output voltage is user-adjustable with a pair of external  
resistors.  
In this mode, the P channel MOSFET and N channel  
MOSFET always operate complementary. When the  
PMOSFET is on and the NMOSFET off, the inductor current  
increases linearly. The input energy is transferred to the  
output and also stored in the inductor. When the P channel  
MOSFET is off and the N channel MOSFET on, the inductor  
current decreases linearly, and energy is transferred from  
the inductor to the output. Hence, the average current  
through the inductor is the output current. Since the inductor  
and the output capacitor act as a low pass filter, the duty  
When the load is very light, the regulator automatically  
operates in the PFM mode, thus achieving high efficiency at  
light load (>70% for 1mA load). When the load increases to  
typically 250mA, the regulator automatically switches over to  
a voltage-mode PWM operating at nominal 1.4MHz  
switching frequency. The efficiency is up to 94%.  
It can also operate in a fixed PWM mode or be synchronized  
to an external clock up to 12MHz for improved EMI  
performance.  
cycle ratio is approximately equal to V divided by V  
.
O
IN  
The output LC filter has a second order effect. To maintain  
the stability of the converter, the overall controller must be  
compensated. This is done with the fixed internally  
compensated error amplifier and the PWM compensator.  
Because the compensations are fixed, the values of input  
and output capacitors are 10µF to 22µF ceramic and  
inductor is 1.5µH to 2.2µH.  
PFM Operation  
The heart of the EL7531 regulator is the automatic  
PFM/PWM controller.  
If the SYNC pin is connected to ground, the regulator  
operates automatically in either the PFM or PWM mode,  
depending on load. When the SYNC pin is connected to V  
,
IN  
Forced PWM Mode/SYNC Input  
the regulator operates in the fixed PWM mode. When the pin  
is connected to an external clock ranging from 1.6MHz to  
12MHz, the regulator is in the fixed PWM mode and  
synchronized to the external clock frequency.  
Pulling the SYNC pin HI (>2.5V) forces the converter into  
PWM mode in the next switching cycle regardless of output  
current. The duration of the transition varies depending on  
the output current. Figures 22 and 23 (under two different  
loading conditions) show the device goes from PFM to PWM  
mode.  
In the automatic PFM/PWM operation, when the load is light,  
the regulator operates in the PFM mode to achieve high  
efficiency. The top P channel MOSFET is turned on first. The  
inductor current increases linearly to a preset value before it  
is turned off. Then the bottom N channel MOSFET turns on,  
and the inductor current linearly decreases to zero current.  
The N channel MOSFET is then turned off, and an anti-  
Note: In forced PWM mode, the IC will continue to start-up in  
PFM mode to support pre-biased load applications.  
Start-Up and Shut-Down  
When the EN pin is tied to V , and V reaches  
IN IN  
ringing MOSFET is turned on to clamp the V pin to V .  
LX  
O
approximately 2.4V, the regulator begins to switch. The  
inductor current limit is gradually increased to ensure proper  
soft-start operation.  
The inductor current looks like triangular pulses. The  
frequency of the pulses is mainly a function of output current.  
The higher the load, the higher the frequency of the pulses  
until the inductor current becomes continuous. At this point,  
the controller automatically changes to PWM operation.  
When the EN pin is connected to a logic low, the EL7531 is  
in the shut-down mode. All the control circuitry and both  
MOSFETs are off, and V  
total input current is less than 1µA.  
falls to zero. In this mode, the  
OUT  
When the controller transitions to PWM mode, there can be  
a perturbation to the output voltage. This perturbation is due  
to the inherent behavior of switching converters when  
transitioning between two control loops. To reduce this  
effect, it is recommended to use the phase-lead capacitor  
When the EN reaches logic HI, the regulator repeats the  
start-up procedure, including the soft-start function.  
Current Limit and Short-Circuit Protection  
(C ) shown in the Typical Application Diagram on page 1.  
4
The current limit is set at about 2A for the PMOS. When a  
short-circuit occurs in the load, the preset current limit  
restricts the amount of current available to the output, which  
causes the output voltage to drop below the preset voltage.  
In the meantime, the excessive current heats up the  
regulator until it reaches the thermal shut-down point.  
This capacitor allows the PWM loop to respond more quickly  
to this type of perturbation. To properly size C , refer to the  
4
Component Selection section.  
FN7428.9  
July 13, 2006  
9
EL7531  
The inductor must be able to handle I for the RMS load  
Thermal Shut-Down  
O
current, and to assure that the inductor is reliable, it must  
handle the 2A surge current that can occur during a current  
limit condition.  
Once the junction reaches about 145°C, the regulator shuts  
down. Both the P channel and the N channel MOSFETs turn  
off. The output voltage will drop to zero. With the output  
MOSFETs turned off, the regulator will soon cool down.  
Once the junction temperature drops to about 130°C, the  
regulator will restart again in the same manner as EN pin  
connects to logic HI.  
In addition to decoupling capacitors and inductor value, it is  
important to properly size the phase-lead capacitor C  
4
(Refer to the Typical Application Diagram). The phase-lead  
capacitor creates additional phase margin in the control loop  
by generating a zero and a pole in the transfer function. As a  
Thermal Performance  
general rule of thumb, C should be sized to start the phase-  
4
The EL7531 is available in a fused-lead MSOP10 package.  
Compared with regular MSOP10 package, the fused- lead  
lead at a frequency of ~2.5kHz. The zero will always appear  
at lower frequency than the pole and follow the equation  
below:  
package provides lower thermal resistance. The θ is  
JA  
100°C/W on a 4-layer board and 125°C/W on 2-layer board.  
Maximizing the copper area around the pins will further  
improve the thermal performance.  
1
f
= ----------------------  
Z
2πR C  
2
4
Power Good Output  
Over a normal range of R (~10-100k), C will range from  
2
4
The PG (pin 8) output is used to indicate when the output  
voltage is properly regulating at the desired set point. It is an  
open-drain output that should be tied to VIN or VCC through  
a 100kΩ resistor. If no faults are detected, EN is high, and  
the output voltage is within ~5% of regulation, the PG pin will  
be allowed to go high. Otherwise, the open-drain NMOS will  
pull PG low.  
~470-4700pF. The pole frequency cannot be set once the  
zero frequency is chosen as it is dictated by the ratio of R  
1
and R , which is solely determined by the desired output set  
2
point. The equation below shows the pole frequency  
relationship:  
1
f
= ---------------------------------------  
P
2π(R R )C  
4
1
2
Output Voltage Selection  
Layout Considerations  
Users can set the output voltage of the variable version with  
a resister divider, which can be chosen based on the  
following formula:  
The layout is very important for the converter to function  
properly. The following PC layout guidelines should be  
followed:  
R
⎛
⎞
⎟
⎠
2
V
= 0.8 × 1 + ------  
⎜
1. Separate the Power Ground ( ) and Signal Ground  
O
R
⎝
1
(
); connect them only at one point right at the pins  
2. Place the input capacitor as close to V and PGND pins  
IN  
Component Selection  
as possible  
Because of the fixed internal compensation, the component  
choice is relatively narrow. For a regulator with fixed output  
voltage, only two capacitors and one inductor are required.  
We recommend 10µf to 22µF multi-layer ceramic capacitors  
with X5R or X7R rating for both the input and output  
capacitors, and 1.5 to 2.2µH for the inductor.  
3. Make the following PC traces as small as possible:  
4. from LX pin to L  
5. from C to PGND  
O
6. If used, connect the trace from the FB pin to R and R  
1
2
as close as possible  
7. Maximize the copper area around the PGND pin  
The RMS current present at the input capacitor is decided by  
the following formula:  
8. Place several via holes under the chip to additional  
ground plane to improve heat dissipation  
V
× (V – V )  
IN O  
O
The demo board is a good example of layout based on this  
outline. Please refer to the EL7531 Application Brief.  
-----------------------------------------------  
I
=
× I  
INRMS  
O
V
IN  
This is about half of the output current I for all the V . This  
O
O
input capacitor must be able to handle this current.  
The inductor peak-to-peak ripple current is given as:  
(V – V ) × V  
O
IN  
O
∆I = -------------------------------------------  
IL  
L × V × f  
IN  
S
L is the inductance  
f
the switching frequency (nominally 1.4MHz)  
S
FN7428.9  
July 13, 2006  
10  
EL7531  
Mini SO Package Family (MSOP)  
MDP0043  
0.25 M C A B  
A
MINI SO PACKAGE FAMILY  
D
(N/2)+1  
SYMBOL  
MSOP8  
1.10  
0.10  
0.86  
0.33  
0.18  
3.00  
4.90  
3.00  
0.65  
0.55  
0.95  
8
MSOP10  
1.10  
0.10  
0.86  
0.23  
0.18  
3.00  
4.90  
3.00  
0.50  
0.55  
0.95  
10  
TOLERANCE  
Max.  
NOTES  
N
A
A1  
A2  
b
-
±0.05  
-
±0.09  
-
E
E1  
PIN #1  
I.D.  
+0.07/-0.08  
±0.05  
-
c
-
D
±0.10  
1, 3  
E
±0.15  
-
1
B
(N/2)  
E1  
e
±0.10  
2, 3  
Basic  
-
L
±0.15  
-
e
H
C
L1  
N
Basic  
-
SEATING  
PLANE  
Reference  
-
Rev. C 6/99  
M
C A B  
b
0.08  
0.10 C  
NOTES:  
N LEADS  
1. Plastic or metal protrusions of 0.15mm maximum per side are not  
included.  
2. Plastic interlead protrusions of 0.25mm maximum per side are  
not included.  
L1  
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.  
4. Dimensioning and tolerancing per ASME Y14.5M-1994.  
A
c
SEE DETAIL "X"  
A2  
GAUGE  
PLANE  
0.25  
L
DETAIL X  
A1  
3° ±3°  
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.  
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality  
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without  
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and  
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result  
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see www.intersil.com  
FN7428.9  
July 13, 2006  
11  

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