EL7566DREZ-T7 [INTERSIL]
Monolithic 6 Amp DC-DC Step-Down Regulator; 单片6安培的DC-DC降压型稳压器
| 型号： | EL7566DREZ-T7 |
| 厂家： | 
Intersil |
| 描述： | Monolithic 6 Amp DC-DC Step-Down Regulator |
| 文件： | 总14页 (文件大小：490K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EL7566
®
Data Sheet
December 1, 2004
FN7102.5
Monolithic 6 Amp DC-DC Step-Down
Regulator
Features
• Integrated MOSFETs
The EL7566 is a full-feature synchronous step-down regulator
capable of up to 6A and 96% efficiency. The device operates
• 6A continuous output current
• Up to 96% efficiency
from 3V to 6V input supply (V ). With internal CMOS power
IN
FETs, the device can operate at up to 100% duty ratio,
• Multiple supply start-up tracking
• Built-in ±5% voltage margining
allowing for an output voltage range of 0.8V to nearly V . An
IN
adjustable switching frequency up to 1MHz enables the use of
small components, thereby reducing board area consumption
to under 0.72sq-in on one side of a PCB. The EL7566
operates in constant frequency PWM mode, making external
synchronization possible. A soft-start feature is integrated in
the EL7566 to limit in-rush currents and allow for a smooth
voltage ramp from zero to regulation. Other start-up features
are integrated to add flexibility for synchronizing many
supplies in multiple configurations. The EL7566 also offers a
voltage margining capability that shifts the output voltage ±5%
for validation of system card performance and reliability during
manufacturing tests. A junction temperature indicator
conveniently monitors the silicon die temperature, saving time
in thermal characterization.
• 3V to 6V input voltage
2
• 0.72 in footprint with components on one side of PCB
• Adjustable switching frequency to 1MHz
• Oscillator synchronization possible
• 100% duty ratio
• Junction temperature indicator
• Over-temperature protection
• Internal soft-start
• Variable output voltage down to 0.8V
• Power-good indicator
An easy-to-use simulation tool is available for download and
can be used to modify design parameters such as switching
frequency, voltage ripple, ambient temperature, as well as
view schematics waveforms, efficiency graphs, and
complete BOM with Gerber layout.
• 28-pin HTSSOP package
• Pb-Free Available (RoHS Compliant)
Applications
• Point-of-regulation power supplies
• FPGA Core and I/O supplies
• DSP, CPU Core, and IO supplies
• Logic/Bus supplies
Ordering Information
PART
TAPE &
PKG.
NUMBER
PACKAGE
28-HTSSOP
REEL DWG. #
EL7566DRE
-
7”
MDP0048
MDP0048
MDP0048
MDP0048
MDP0048
MDP0048
MDP0048
EL7566DRE-T7
28-HTSSOP
• Portable equipment
EL7566DRE-T13
EL7566DREZ (Note)
28-HTSSOP
13”
-
Related Documentation
• Technical Brief 415 - Using the EL7566 Demo Board
28-HTSSOP (Pb-free)
EL7566DREZ-T7 (Note) 28-HTSSOP (Pb-free)
EL7566DREZ-T13 (Note) 28-HTSSOP (Pb-free)
7”
• Easy-to-use applications software simulation tool available
at www.intersil.com/dc-dc
13”
EL7566AIREZ (Note)
28-HTSSOP (Pb-free)
-40°C to 85°C
EL7566AIREZ-T7 (Note) 28-HTSSP (Pb-free)
-40°C to 85°C
7”
MDP0048
MDP0048
EL7566AIREZ-T13
(Note)
28-HTSSOP (Pb-free)
-40°C to 85°C
13”
NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both
SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020C.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004. All Rights Reserved.
1
All other trademarks mentioned are the property of their respective owners.
EL7566
Typical Application Diagram
C
C
R
C
1
2
3
4
5
6
7
8
9
COMP SGND 28
270pF
8200pF 10K
0.047µF
R
10K
2
VREF
FB
COSC 27
STN 26
STP 25
EN 24
R
21.5K
1
VO
0.22µF
VTJ
TM
PG 23
SEL
LX
VDD 22
VIN 21
V
IN
(3V TO
6V)
2.7µH
LX
VIN 20
V
OUT
(2.5V, 6A)
100µF
10 LX
11 LX
12 LX
13 LX
14 NC
VIN 19
150µF
PGND 18
PGND 17
PGND 16
NC 15
FN7102.5
2
December 1, 2004
EL7566
Absolute Maximum Ratings (T = 25°C)
A
V
, V
to SGND. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +135°C
Operating Ambient Temperature DRE. . . . . . . . . . . . . 0°C to +85°C
Operating Ambient Temperatute AIRE . . . . . . . . . . .-40°C to +85°C
IN DD
VX to PGND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V +0.3V
IN
SGND to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
COMP, V
, FB, V , V , TM,
REF TJ
O
SEL, PG, EN, STP, STN, C
OSC
to SGND . . . . . -0.3V to V
+0.3V
DD
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T = T = T
A
J
C
DC Electrical Specifications
PARAMETER
V
= V = 3.3V, T = T = 25°C, C
= 390pF, Unless Otherwise Specified
DD
DESCRIPTION
Input Voltage Range
Reference Accuracy
IN
A
J
OSC
CONDITIONS
MIN
3
TYP
MAX
6
UNIT
V
V
IN
V
1.24
1.26
50
1.28
V
REF
V
Reference Temperature Coefficient
Reference Load Regulation
Oscillator Ramp Amplitude
Oscillator Charge Current
ppm/°C
%
REFTC
V
0 < I
< 50µA
-1
REFLOAD
REF
V
1.15
200
8
V
RAMP
I
0.1V < V
0.1V < V
< 1.25V
µA
mA
mA
mA
V
OSC_CHG
OSC
OSC
I
Oscillator Discharge Current
< 1.25V
OSC_DIS
I
V
V
V
V
Supply Current
Standby Current
for Shutdown
for Startup
V
= 1 (L disconnected)
2
2.7
1
5
VDD
VDD_OFF
DD
DD
DD
DD
EN
EN = 0
I
1.5
V
2.4
2.6
2.65
2.95
DD_OFF
V
V
DD_ON
T
Over-temperature Threshold
Over-temperature Hysteresis
Internal FET Leakage Current
Peak Current Limit
135
20
°C
OT
T
°C
HYS
I
EN = 0, L = 6V (low FET), L = 0V (high FET)
10
50
µA
A
LEAK
X
X
I
7.8
-4
LMAX
R
PMOS On Resistance
29
25
mΩ
mΩ
mΩ/°C
µA
µA
%
DSON1
R
NMOS On Resistance
DSONTC2
R
R
Tempco
0.2
2.5
2.5
DSONTC
DSON
I
STP Pin Input Pull-down Current
STN Pin Input Pull-up Current
Positive Power Good Threshold
Negative Power Good Threshold
Power Good Drive High
V
V
= V /2
IN
STP
STN
STP
STN
I
= V /2
IN
4
V
With respect to target output voltage
With respect to target output voltage
6
14
-6
PGP
PGN
V
-14
2.6
%
V
I
I
= 1mA
V
PG_HI
PG
PG
V
Power Good Drive Low
= -1mA
0.5
V
PG_LO
V
Output Overvoltage Protection
Output Initial Accuracy
10
0.8
0.2
125
±1
%
OVP
V
I
= 0A
0.79
85
0.81
0.5
V
FB
FB_LINE
GM
LOAD
V
Output Line Regulation
V
V
= 3.3V, ∆V = 10%, I
IN
= 0A
%
IN
LOAD
Error Amplifier Transconductance
Output Temperature Stability
Switching Frequency
= 0.65V
165
µs
EA
FB_TC
CC
V
0°C < T < 85°C, I
LOAD
= 3A
%
A
F
300
370
100
440
200
kHz
nA
S
I
Feedback Input Pull-up Current
V
= 0V
FB
FB
FN7102.5
3
December 1, 2004
EL7566
DC Electrical Specifications
V
= V = 3.3V, T = T = 25°C, C
= 390pF, Unless Otherwise Specified (Continued)
DD
IN
A
J
OSC
PARAMETER
DESCRIPTION
EN Input High Threshold
EN Input Low Threshold
Enable Pull-up Current
Input High Level
CONDITIONS
MIN
TYP
MAX
UNIT
V
V
2.6
EN_HI
V
1
V
EN_LO
I
V
= 0
EN
-4
-2.5
µA
V
EN
TM, S
2.6
EL_HI
TM, S
Input Low Level
1
V
EL_LO
Pin Descriptions
PIN NUMBER
PIN NAME
COMP
VREF
PIN FUNCTION
Error amplifier output; place loop compensation components here
Bandgap reference bypass capacitor; typically 0.022µF to 0.047µF to SGND
1
2
3
FB
Voltage feedback input; connected to external resistor divider between V and SGND for adjustable
OUT
output; also used for speed-up capacitor connection
4
VO
VTJ
TM
Output sense for fixed output option. This pin can be open for EL7566
Junction temperature monitor output
5
6
Stress test enable; allows ±5% output movement; connect to SGND if function is not used
Positive or negative stress select; see text
7
8, 9, 10, 11, 12, 13
14, 15
SEL
LX
Inductor drive pin; high current output whose average voltage equals the regulator output voltage
Not used
NC
16, 17, 18
19, 20, 21
22
PGND
VIN
VDD
PG
Ground return of the regulator; connected to the source of the low-side synchronous NMOS Power FET
Power supply input of the regulator; connected to the drain of the high-side PMOS Power FET
Control circuit positive supply; connected to V through an internal 20Ω resistor
IN
23
Power-good window comparator output; logic 1 when regulator output is within ±10% of target output
voltage
24
25
26
EN
Chip enable, active high; a 2.5µA internal pull-up current enables the device if the pin is left open; a
capacitor can be added at this pin to delay the start of a converter
STP
STN
Auxilliary supply tracking positive input; tied to regulator output to synchronize start-up with a second
supply; leave open for standalone operation; 2µA internal pull-up current
Auxiliary supply tracking negative input; connect to output of a second supply to synchronize start-up;
leave open for standalone operation; 2µA internal pull-up current
27
28
COSC
SGND
Oscillator timing capacitor (see performance curves)
Control circuit negative supply or signal ground
FN7102.5
4
December 1, 2004
EL7566
Block Diagram
TM
0.047µF
390pF
SEL
V
C
OSC
REF
V
TJ
JUNCTION
VOLTAGE
OSCILLATOR
TEMPERATURE
REFERENCE
V
DD
V
V
DD
IN
2.2nF
EN
20Ω
0.22µF
100µF
150µF
STP
STN
V
V
IN
POWER
TRACKING
POWER
FET
2.7µH
PWM
CONTROLLER
DRIVERS
OUT
(2.5V, 6A)
POWER
FET
PGND
EA
CURRENT
SENSE
COMP
V
DD
R
C
C
C
V
REF
-
+
PG
SGND
FB
V
O
R
1
R
2
FN7102.5
December 1, 2004
5
EL7566
Typical Performance Curves
V
= V = 5V, V = 2.5V, I = 6A, f = 500kHz, L = 2.7µH, C = 100µF, C = 150µF, T = 25°C unless otherwise noted.
IN OUT A
IN
D
O
O
S
100
95
90
85
80
75
70
65
60
100
V
=3.3V
O
V
=2.5V
O
V
=2.5V
=1.8V
O
O
95
90
85
80
75
70
65
60
V
=1.8V
O
V
=0.8V
O
V
=0.8V
O
V
=1V
3
O
V
=1V
O
V
=1.2V
O
V
=1.2V
V
O
0
1
2
3
4
5
6
0
1
2
4
5
6
I
(A)
I (A)
O
O
FIGURE 1. EFFICIENCY (V = 5V)
IN
FIGURE 2. EFFICIENCY (V = 3.3V)
IN
1.265
1.26
1.6
1.5
1.4
1.3
1.2
1.1
1
V
=3.3V
DD
1.255
1.25
V
=5V
DD
V
=3.3V
DD
V
=5V
DD
1.24
1.245
0
0
50
100
150
0
50
100
150
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
FIGURE 3. V
REF
vs TEMPERATURE
FIGURE 4. V vs TEMPERATURE
TJ
4
3.5
3
1200
1000
800
600
500
200
0
V
EN_HI
V
=5V
DD
2.5
2
V
=3.3V
DD
V
EN_LOW
1.5
1
3
3.5
4
4.5
(V)
5
5.5
6
100
200
300
400
(pF)
500
600
700
V
C
DD
OSC
FIGURE 5. V
& V
vs V
FIGURE 6. F vs C
S OSC
EN_HI
EN_LOW
DD
FN7102.5
December 1, 2004
6
EL7566
Typical Performance Curves
V
= V = 5V, V = 2.5V, I = 6A, f = 500kHz, L = 2.7µH, C = 100µF, C
= 150µF, T = 25°C unless otherwise noted. (Continued)
IN
D
O
O
S
IN
OUT
A
526
524
522
520
518
516
514
512
510
508
506
504
0.1
0.05
0
V
=5V
IN
-0.05
-0.1
-0.15
-0.2
V
=3.3V
IN
-0.25
-0.3
-0.35
0
1
2
3
4
5
6
0
1
2
3
4
5
6
I
(A)
I (A)
O
O
FIGURE 7. F vs LOAD CURRENT
S
FIGURE 8. LOAD REGULATIONS
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD HTSSOP
EXPOSED DIEPAD NOT SOLDERED TO PCB
50
45
40
35
30
25
1.2
1
CONDITION:
28-Pin HTSSOP THERMAL PAD
SOLDERED TO 2-LAYER PCB
WITH 0.039" THICKNESS AND
1 OZ. COPPER ON BOTH SIDES
1.136W
0.8
0.6
0.4
0.2
0
1
2
3
4
5
6
2
7
8
9
0
25
50
75 85 100
125
150
PCB AREA (in )
AMBIENT TEMPERATURE (°C)
FIGURE 9. HTSSOP THERMAL RESISTANCE vs PCB AREA
(NO AIR FLOW)
FIGURE 10. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD HTSSOP EXPOSED
DIEPAD SOLDERED TO PCB PER JESD51-5
4.5
4
4.167W
3.5
3
2.5
2
1.5
1
0.5
0
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (°C)
FIGURE 11. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FN7102.5
7
December 1, 2004
EL7566
Waveforms
V
= V = 5V, V = 2.5V, I = 6A, f = 500kHz, L = 2.7µH, C = 100µF, C
= 150µF, T = 25°C unless otherwise noted.
A
IN
D
O
O
S
IN
OUT
∆V (200mV/DIV)
IN
V
(5V/DIV)
IN
I
(2A/DIV)
L
I
(2A/DIV)
(2V/DIV)
IN
V
O
V
(5V/DIV)
LX
PG
∆V (50mV/DIV)
O
0.5ms/DIV
1µs/DIV
FIGURE 12. START-UP
FIGURE 13. STEADY-STATE OPERATION
4.5A
V
I
EN
O
1.5A
I
(2A/DIV)
IN
∆V (100mV/DIV)
O
V
(2V/DIV)
O
50µs/DIV
100µs/DIV
FIGURE 14. SHUT-DOWN
FIGURE 15. TRANSIENT RESPONSE
TM
PG
V
(2V/dIv)
O
SEL
∆V (200mV/DIV)
O
V
(5V/DIV)
LX
1ms/DIV
0.5ms/DIV
FIGURE 16. VOLTAGE MARGINING
FIGURE 17. OVERVOLTAGE SHUT-DOWN
FN7102.5
December 1, 2004
8
EL7566
Waveforms
V
= V = 5V, V = 2.5V, I = 6A, f = 500kHz, L = 2.7µH, C = 100µF, C
= 150µF, T = 25°C unless otherwise noted. (Continued)
OUT A
IN
D
O
O
S
IN
V
(5V/DIV)
V
(5V/DIV)
IN
IN
I
(2A/DIV)
(2V/DIV)
IN
V
V
=2.5V
=1.8V
O1
O2
V
O
PG
5ms/DIV
5ms/DIV
FIGURE 18. ADJUSTABLE START-UP
FIGURE 19. TRACKING START-UP
Detailed Description
The EL7566 is a 6A capable buck regulator operating from
an input voltage range of 3V to 6V. The duty cycle can be
adjusted from 0% to 100% allowing for a wide range of
programmable output voltages. Patented on-chip
resistorless current-sensing enables current mode control
for excellent step load response. Overcurrent, Overvoltage,
input Undervoltage, and thermal protection is integrated
along with soft-start and power-up sequencing features to
produce an overall robust power solution for general
purpose applications.
placed from the EN pin to GND to program a delay between
when the rising POR threshold for VIN is met and when soft-
start begins. The programmable delay time, T , is governed
D
by Equation 1.
V
EN_HI
-------------------
T
= C
×
EN
D
I
EN
where:
• C
• V
is the capacitance at EN pin
EN
is the EN input high level (function of V
voltage,
DD
EN_HI
EL7566DRE vs. EL7566AIRE
The EL7566AIRE includes the following feature changes
from the EL7566DRE:
see Figure 5)
• I
is the EN pin pull-up current, nominal 2.5µA
EN
Steady-State Operation
• Up to 6A Current Sinking Capability
Under all steady-state conditions the converter will operate
in fixed frequency continuous-conduction mode. For fast
transient response and ease of controllability, a peak
current-mode control method is employed. The inductor
current is sensed from the upper PMOS. This current signal
serves as the ramp to the PWM comparator and is compared
against the difference signal generated by the
transconductance error amplifier. Slope compensation for
the ramp is used to allow for 100% duty cycle operation (see
Figure 20). The pulse-width modulated square wave output
of the PWM comparator is amplified and serves as the gate
drive signals for the switching power FETs.
o
o
• Expanded Temperature Range: -40 C to 85 C
• No Overvoltage Protection
Start-Up
The EL7566 employs a digital soft-start feature to suppress
the in-rush current needed to charge the output capacitance
and smoothly ramp the output voltage to regulation (See
Figure 12). The normal start-up process begins when the
input voltage reaches the rising POR threshold (~2.8V) and
EN pin is transitioned HIGH by an internal 2.5µA current
source. The output voltage is then digitally ramped to
regulation over a 2ms period. The 2ms soft start-up time can
be extended if needed by configuring the STP and STN pins.
(refer to Full Start-Up Control section).
100% DUTY RATIO
EL7566 uses CMOS as internal synchronous power
switches. The upper and lower switches are PMOS and
NMOS respectively. The upper PMOS saves the need for a
boot capacitor normally seen in NMOS/NMOS half-bridges.
If the input voltage is ramped slowly, soft-start may be
initiated before the input supply has reached regulation. The
lower input voltage will have increased current demand
during start-up and may risk an overcurrent event. To
prevent such an event from occurring, a capacitor can be
FN7102.5
9
December 1, 2004
EL7566
It also allows 100% turn-on of the upper PMOS switch,
OSC pin to GND (C ). The triangle waveform has 95%
OSC
achieving V close to V . The maximum achievable V is:
duty ratio and runs from 0.2V to 1.2V. Refer to the curve in
Figure 6 for the appropriate value of C for the desired
O
IN
O
OSC
V
= V – (R + R
) × I
O
IN
L
DSON1
O
frequency. If external synchronization is desired, the circuit
in Figure 21 can be used.
Where R is the DC resistance on the inductor and R
L
DSON1
is the PMOS on-resistance, nominally 30mΩ at room
100pF
temperature with a temperature coefficient of 0.2mΩ/°C.
EL7566
EXTERNAL SYNC
SOURCE
OUTPUT VOLTAGE SELECTION
C
OSC
The output voltage can be as high as the input voltage minus
the PMOS and inductor voltage drops (as seen previously in
Equation 2). Referring to the Typical Application Circuit on
FIGURE 20. EXTERNAL SYNC CIRCUIT
page 2, use R and R to set the output voltage according to
1
2
Always choose the converter self-switching frequency 20%
lower than the sync frequency to accommodate component
variations.
the following formula:
R
1
V
= 0.8 × 1 + ------
O
R
2
Protection Features
The EL7566 features a wide range of protective measures to
prevent the persistence of damaging system conditions.
These features are overvoltage, overcurrent, Power-On-
Reset (POR), and Thermal Shutdown protection.
Some standard values of R and R are listed in Table 1.
1
2
TABLE 1.
V
(V)
R
(kΩ)
R (kΩ)
2
O
1
OVERVOLTAGE PROTECTION (OVP)
The EL7566 monitors the output voltage and will shut down
if it exceeds 110% of the set regulation point. This is
accomplished by comparing the reference to the FB pin
voltage. If an overvoltage condition is met, the controller will
turn the high-side switch off, the low-side switch on, and pull
PGOOD low. The converter will not latch off and will proceed
with a soft-start as soon as the fault condition is cleared.
0.8
1
2
Open
10
2.49
4.99
10
1.2
1.5
1.8
2.5
3.3
10
11.5
10.2
10
12.7
21.5
36
11.5
OVERCURRENT PROTECTION (OCP)
The current information for PWM ramp generation is also
used for overcurrent protection. The measured current is
compared against a preset Overcurrent threshold (~7-10A).
If the output current exceeds the threshold, the output will
shut down by turning off the high-side switch and turning the
low-side switch on. This event, like OVP, will not latch the
converter off. A soft-start will be initiated when the fault is
cleared.
It is important that the series combination of R1 and R2 is
large enough as to not draw excessive current from the
output.
VOLTAGE MARGINING
The EL7566 has built-in 5% load stress test (commonly
called voltage margining) function. Combinations of TM and
SEL set the margins shown in Table 2. When this function is
not used, both pins should be connected to SGND, either
directly or through a 10kΩ resister. Figure 16 shows this
feature.
POWER-ON RESET (POR)
To ensure proper regulator operation, a power-on reset
feature monitors the input voltage. When adequate input
TABLE 2.
voltage is achieved (V
> 2.8V), the converter is allowed to
falls below 2.5V, the regulator will
DD
DD
soft-start. However, if V
CONDITION
Normal
TM
0
SEL
X
V
O
shut down in the same manner as OVP or OCP.
Nominal
THERMAL PROTECTION AND JUNCTION
TEMPERATURE INDICATOR
High Margin
Low Margin
1
1
Nominal + 5%
Nominal - 5%
1
0
An internal temperature sensor continuously monitors the
junction temperature. If the junction temperature exceeds
135°C, the regulator is in a fault condition and will shut
down. When the temperature falls back below 110°C, the
regulator goes through the soft-start procedure again.
SWITCHING FREQUENCY
The regulator has a programmable switching frequency of
200kHz to 1MHz. The switching frequency is generated by a
relaxation comparator and adjusted by a capacitor from the
FN7102.5
December 1, 2004
10
EL7566
The V pin reports a voltage proportional to the junction
TJ
LINEAR START-UP
In the linear start-up tracking configuration, the regulator with
lower output voltage, V , tracks the one with higher output
temperature. Equation 3 illustrates the relationship and can
be used to accurately evaluate thermal design points.
O2
voltage, V
.
O1
1.2 – V
TJ
T
= 75 + ------------------------
J
0.00384
C
STN
STP
Full Start-Up Control
-
-
+
+
The EL7566 offers full start-up control. The core of this
control is a start-up comparator in front of the main PWM
controller. The STP and STN are the inputs to the
comparator, whose HI output forces the PWM comparator to
skip switching cycles. The user can choose any of the
following control configurations:
V
R
O2
V
V
O1
IN
EL7566
EL7566
V
IN
V
V
O1
O2
ADJUSTABLE SOFT-START
In this configuration, the ramp-up time is adjustable to any
time longer than the building soft-start time of 2ms. The
FIGURE 23. LINEAR START-UP TRACKING
approximate ramp-up time, T , is:
ST
OFFSET START-UP
V
O
Compared with the cascade start-up, this configuration
---------
T
= RC
ST
V
allows Regulator 2 to begin the start-up process when V
IN
O1
*(1+R /R ) before PG
reaches a particular value of V
REF
B
A
goes HI, where V
is the regulator reference voltage.
REF
V
=1.26.
REF
C
0.1µF
STN
STP
-
+
V
O
R
200K
V
O
V
R
B
REF
-
EL7566
V
IN
V
+
R
A
O2
T
ST
V
O1
EL7566
V
IN
FIGURE 21. ADJUSTABLE START-UP
EL7566
V
IN
CASCADE START-UP
V
(1+R /R
)
REF
B
A
In this configuration, EN pin of Regulator 2 is connected to
the PG pin of Regulator 1 (Figure 22). V will only start
O2
V
V
O1
O2
after V is good.
O1
FIGURE 24. OFFSET START-UP TRACKING
EN
PG
Component Selection
V
V
V
IN
O2
O1
INPUT CAPACITOR
EL7566
EL7566
The main functions of the input capacitor(s) are to maintain
the input voltage steady and to filter out the pulse current
passing through the upper switch. The root-mean-square
value of this current is:
V
V
O1
O2
V
× (V – V )
IN O
O
-----------------------------------------------
I
=
× I ≈ 1/2(I )
O
IN,RMS
O
V
IN
FIGURE 22. CASCADE START-UP
for a wide range of V and V .
IN
O
For long-term reliability, the input capacitor or combination of
capacitors must have the current rating higher than I
.
IN,RMS
Use X5R or X7R type ceramic capacitors, or SPCAP or
POSCAP types of Polymer capacitors for their high current
handling capability.
FN7102.5
11
December 1, 2004
EL7566
INDUCTOR
where:
The NMOSNMOS reverse current limit is set at about 0.5A.
For optimal operation, the peak-to-peak inductor current
• GM
GM
is the transconductance of the PWM comparator,
= 120S
PWM
PWM
ripple ∆I should be less than 1A. The following equation
L
V
O
gives the inductance value:
R
= -------
OUT
I
O
(V – V ) × V
O
IN
O
L = -------------------------------------------
V
× ∆I × F
L S
• ESR is the ESR of the output capacitor
• C is output capacitance
IN
OUT
The peak current the inductor sees is:
• GM is the transconductance of the error amplifier,
EA
∆I
GM = 120µS
EA
L
I
= I + --------
LPK
O
2
• F is the intended crossover frequency of the loop. For
C
best performance, set this value to about one-tenth of the
switching frequency.
When inductor is chosen, it must be rated to handle the peak
current and the average current of I .
O
• Once R is chosen, C is decided by:
C
C
OUTPUT CAPACITOR
R
OUT
Output voltage ripple and transient response are the
predominant factors when choosing the output capacitor.
Initially, output capacitance should be sized with an ESR to
---------------
×
OUT
C
= 1.5 × C
C
R
C
Design Example
A 5V to 2.5V converter with a 6A load requirement.
satisfy the output ripple ∆V requirement:
O
∆V = ∆I × ESR
O
L
1. Choose the input capacitor
The input capacitor or combination of capacitors has to be
able to take about 1/2 of the output current, e.g., 3A.
Panasonic EEFUD0J101XR is rated at 3.3A, 6.3V, meeting
the above criteria.
When a step load change, ∆I , is applied to the converter,
O
the initial voltage drop can be approximated by ESR*∆I .
O
The output voltage will continue to drop until the control loop
begins to correct the output voltage error. Increasing the
output capacitance will lessen the impact of load steps on
output voltage. Increasing loop bandwidth will also reduce
output voltage deviation under step load conditions. Some
experimentation with converter bandwidth and output
filtering will be necessary to generate a good transient
response (Reference Figure 15).
2. Choose the inductor. Set the converter switching
frequency at 500kHz:
(V – V ) × V
O
IN
O
L = -------------------------------------------
V
× ∆I × F
L S
IN
∆I = 1A yields 2.3µH. Leave some margin and choose
L
As with the input capacitor, it is recommended to use X5R or
X7R type of ceramic capacitors. SPCAP or POSCAP type
Polymer capacitors can also be used for the low ESR and
high capacitance requirements of these converters.
L = 2.7µH. Coilcraft's DO3316P-272HC has the required
current rating.
3. Choose the output capacitor
L = 2.7µH yields about 1A inductor ripple current. If 25mV of
Generally, the AC current rating of the output capacitor is not
ripple is desired, C
's ESR needs to be less than 25mΩ.
OUT
a concern because the RMS current is only 1/8 of ∆I .
L
Panasonic's EEFUD0G151XR 150µF has an ESR of 12mΩ
and is rated at 4V.
LOOP COMPENSATION
Current-mode control in system forces the inductor current
to be proportional to the error signal. This has the advantage
of eliminating the double pole response of the output filter,
and reducing complexity in the overall loop compensation. A
simple Type 1 compensator is adequate to generate a
stable, high-bandwidth converter. The compensation resister
is decided by:
ESR is not the only factor deciding the output capacitance.
As discussed earlier, output voltage droops less with more
capacitance when converter is in load transient. Multiple
iterations may be needed before final components are
chosen.
4. Loop compensation
50kHz is the intended crossover frequency. With the
conditions R and C are calculated as:
I
F
× 2 × π × (ESR + R
) × C
OUT OUT
O
C
C
C
----------- -------------------------------------------------------------------------------------------------
R
=
×
C
VFB
GM
× GM
PWM EA
R
= 10.5kΩ and C = 8900pF, round to standard value of
C
C
8200pF.
FN7102.5
12
December 1, 2004
EL7566
For convenience, Table 3 lists the compensation values for
frequently used output voltages.
Layout Considerations
The layout is very important for the converter to function
properly. Follow these tips for best performance:
TABLE 3. COMPENSATION VALUES
1. Separate the Power Ground ( ) and Signal Ground ( );
connect them only at one point right at the SGND pin
V
(V)
R
(KΩ)
C (PF)
C
O
C
3.3
2.5
1.8
1.5
1.2
1
13.7
8200
8200
8200
8200
8200
8200
8200
2. Place the input capacitor(s) as close to V and PGND
IN
10.5
7.68
6.49
5.23
4.42
3.57
pins as possible
3. Make as small as possible the loop from LX pins to L to
C
to PGND pins
O
4. Place R and R pins as close to the FB pin as possible
1
2
5. Maximize the copper area around the PGND pins; do not
place thermal relief around them
6. Thermal pad should be soldered to PCB. Place several
via holes under the chip to the ground plane to help heat
dissipation
The demo board is a good example of layout based on this
outline. Please refer to the EL7566 Application Brief.
0.8
Thermal Management
The EL7566 is packaged in a thermally-efficient HTSSOP-28
package, which utilizes the exposed thermal pad at the
bottom to spread heat through PCB metal.
Therefore:
1. The thermal pad must be soldered to the PCB.
2. Maximize the PCB area.
3. If a multiple layer PCB is used, thermal vias (13 to 25 mil)
must be placed underneath the thermal pad to connect to
ground plane(s). Do not place thermal reliefs on the vias.
Figure 25 shows a typical connection.
The thermal resistance for this package is as low as 26°C/W
for 2 layer PCB of 0.39" thickness (See Figure 9). The actual
junction temperature can be measured at V pin.
TJ
The thermal performance of the IC is heavily dependent on
the layout of the PCB. The user should exercise care during
the design phase to ensure the IC will operate within the
recommended environmental conditions.
COMPONENT SIDE
CONNECTION
GROUND PLANE
CONNECTION
FIGURE 25. PCB LAYOUT - 28-PIN HTSSOP PACKAGE
FN7102.5
13
December 1, 2004
EL7566
Package Outline Drawing
®
1. The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at
http://www.intersil.com/design/packages/index.asp
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7102.5
14
December 1, 2004
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