EL7571 [INTERSIL]
Programmable PWM Controller; 可编程PWM控制器
| 型号： | EL7571 |
| 厂家： | 
Intersil |
| 描述： | Programmable PWM Controller |
| 文件： | 总19页 (文件大小：309K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EL7571
®
Data Sheet
October 25, 2004
FN7298.1
Programmable PWM Controller
Features
The EL7571 is a flexible, high efficiency, current mode, PWM
step down controller. It incorporates five bit DAC adjustable
output voltage control which conforms to the Intel Voltage
Regulation Module (VRM) Specification for Pentium® II and
Pentium® Pro class processors. The controller employs
synchronous rectification to deliver efficiencies greater than
90% over a wide range of supply voltages and load
conditions. The on-board oscillator frequency is externally
adjustable, or may be slaved to a system clock, allowing
optimization of RFI performance in critical applications. In
single supply operation, the high side FET driver supports
boot-strapped operation. For maximum flexibility, system
operation is possible from either a 5V rail, a single 12V rail,
or dual supply rails with the controller operating from 12V
and the power FETs from 5V.
• Pentium® II Compatible
• 5 bit DAC Controlled Output Voltage
• Greater than 90% Efficiency
• 4.5V to 12.6V Input Range
• Dual NMOS Power FET Drivers
• Fixed frequency, Current Mode Control
• Adjustable Oscillator with External Sync. Capability
• Synchronous Switching
• Internal Soft-Start
• User Adjustable Slope Compensation
• Pulse by Pulse Current Limiting
• 1% Typical Output Accuracy
• Power Good Signal
Pinout
R2
5Ω
D1
• Output Power Down
• Over Voltage Protection
C6 0.1µF
ENABLE
1
2
3
4
5
6
7
8
9
OTEN
CSLOPE
COSC
REF
VH1 20
HSD 19
LX 18
L2
C3 240pF
C3 240pF
• Pb-Free Available (RoHS Compliant)
4.5V
to
12.6V
1.5µH
C1
C8
Q1
1µF 1000µ
F x3
Applications
V
OUT
1.3V to
3.5V
1.4V
• Pentium® II Voltage Regulation Modules (VRMs)
• PC Motherboards
C3
VIN 17
L1
R2
5Ω
0.1µF
5.1µH
C2
C7
PWRGD
VIDO
VINP 16
LSD 15
GNDP 14
GND 13
CS 12
POWER
GOOD
1µF
1000µF
x6
• DC/DC Converters
Q2
D2
• GTL Bus Termination
VID1
Voltage
I.D. (VID
(0:4))
• Secondary Regulation
VID2
VID3
Ordering Information
10 VID4
FB 11
TAPE AND
PART NUMBER
EL7571CM
PACKAGE
20-Pin SO
20-Pin SO
REEL
PKG. DWG. #
MDP0027
Q1, Q2: Siliconix, Si4410, x2
C1: Sanyo, 16MV 1000GX, 1000µF x3
C2: Sanyo, 6MV 1000GX, 1000µF x6
L1: Pulse Engineering, PE-53700, 5.1µH
L2: Micrometals, T30-26, 7T AWG #20, 1.5µH
R1: Dale, WSL-25-12, 15mΩ, x2
D1: BAV99
-
13”
-
EL7571CM-T13
MDP0027
EL7571CMZ
(See Note)
20-Pin SO
(Pb-free)
MDP0027
D2: IR, 32CTQ030
EL7571CMZ-T13
(See Note)
20-Pin SO
(Pb-free)
13”
MDP0027
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003-2004. All Rights Reserved.
1
All other trademarks mentioned are the property of their respective owners.
EL7571
Absolute Maximum Ratings (T = 25°C)
A
Supply Voltage: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 14V
Input Pin Voltage:. . . . . . . . . -.03 below Ground, +0.3 above Supply
VHI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 27V
Storage Temperature Range:. . . . . . . . . . . . . . . . . . 65°C to +150°C
Operating Temperature Range: . . . . . . . . . . . . . . . . . . 0°C to +70°C
Operating Junction Temperature:. . . . . . . . . . . . . . . . . . . . . . . 125°C
Peak Output Current:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3A
Power Dissipation: . . . . . . . . . . . . . . . . . . . . . . . . . . . .SO20 500mW
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T = T = T
J
C
A
DC Electrical Specifications T = 25°C, V = 5V, C
= 330pF, C
SLOPE
= 390pF, R = 7.5mΩ unless otherwise specified.
SENSE
A
IN
OSC
PARAMETER
DESCRIPTION
CONDITION
MIN
4.5
TYP
MAX
12.6
4.4
UNIT
V
V
V
Input Voltage Range
IN
Input Under Voltage Lock out Upper
Limit
Positive going input voltage
Negative going input voltage
See VID table
3.6
4
V
UVLO HI
V
Input Under Voltage Lock out Lower
Limit
3.15
3.5
3.85
V
UVLO LO
V
V
Output Voltage Range
1.3
3.5
V
V
OUT RANGE
Steady State Output Voltage Accuracy, I = 6.5A, V
L
VID = 10111
= 2.8V
2.74
2.82
1.81
2.90
OUT 1
OUT
V
Steady State Output Voltage Accuracy, I = 6.5A, V
L
=1.8V
1.74
1.9
V
OUT 2
OUT
VID = 00101
V
V
V
V
Reference Voltage
1.396
125
-40
1.41
154
-5
1.424
185
20
V
REF
Current Limit Voltage
V
V
V
= (V -V
)
mV
mV
%
ILIM
ILIM
IREV
OUT
CS FB
Current Reversal Threshold
= (V -V
)
IREV
OUT PG
CS FB
Output Voltage Power Good Lower
Level
= 2.05V
-18
-14
-10
Output Voltage Power Good Upper
Level
8
12
16
%
V
V
V
V
V
V
V
Over-Voltage Protection Threshold
Power Down Input Low Level
Power Down Input High Level
Voltage I.D. Input Low Level
Voltage I.D. Input High Level
Oscillator Voltage Swing
+9
+13
+17
1.5
%
V
V
V
V
OVP
V
= -10uA
OTEN LO
OTEN HI
ID LO
IN
(V -1.5)
IN
1.5
(V -1.5)
IN
ID HI
0.85
4.8
V
OSC
P-P
V
Power Good Output Low Level
HSD, LSD Switch On-Resistance
I
= 1mA
0.5
6
PWRGD LO
OUT
R
V
, V
IN INP
= 12V, I
= 100mA,
Ω
DS ON
OUT
(VHI-LX) = 12V
R
R
FB Input Impedance
9.5
115
1.2
kΩ
kΩ
mA
mA
A
FB
CS Input Impedance
CS
I
I
I
Quiescent Supply Current
Supply Current in Output Disable Mode
Peak Driver Output Current
V
V
V
>(V -0.5)V
2
1
VIN
OTEN
IN
<1.5V
0.76
2.5
VIN DIS
OTEN
,V
IN INP
= 12V, Measured at HSD,
SOURCE/SINK
LSD, (VHI-LX) = 12V
I
I
I
I
C
Ramp Current
High Side Switch Active
8.5
14
50
2
20
25
µA
µA
mA
µA
RAMP
SLOPE
Oscillator Charge Current
Oscillator Discharge Current
VREF Output Current
1.2>V
1.2>V
>0.35V
>0.35V
OSC CHARGE
OSC DISCHARGE
REFMAX
OSC
OSC
2
EL7571
DC Electrical Specifications T = 25°C, V = 5V, C
= 330pF, C
SLOPE
= 390pF, R = 7.5mΩ unless otherwise specified.
SENSE
A
IN
OSC
(Continued)
PARAMETER
DESCRIPTION
CONDITION
MIN
3
TYP
5
MAX
UNIT
µA
I
I
VID Input Pull up Current
OTEN Input Pull up Current
7
7
VID
OTEN
3
5
µA
AC Electrical Specifications T = 25°C, V = 5V, C
= 330pF, C = 390pF unless otherwise specified.
SLOPE
A
IN
OSC
PARAMETER
OSC
DESCRIPTION
CONDITIONS
= 330pF
MIN
140
50
TYP
190
500
100
MAX
240
UNIT
kHz
kHz
ns
f
f
t
t
Nominal Oscillator Frequency
Clock Frequency
C
OSC
1000
CLK
Shutdown Delay
V
>1.5V
OTEN
SYNC
OTEN
Oscillator Sync. Pulse Width
Oscillator i/p (COSC) driven with
HCMOS gate
20
800
ns
T
Soft-start Period
V
= 3.5V
100/f
us
%
START
OUT
CLK
D
Maximum Duty Cycle
97
MAX
Pin Descriptions
PIN TYPE
PIN NO. PIN NAME (NOTE 1)
FUNCTION
Chip enable input, internal pull up (5mA typical). Active high.
With a capacitor attached from CSLOPE to GND, generates the voltage ramp compensation for the PWM
current mode controller. Slope rate is determined by an internal 14uA pull up and the C capacitor
1
2
OTEN
I
I
CSLOPE
SLOPE
value. VC
is reset to ground at the termination of the high side cycle.
SLOPE
3
COSC
I
Multi-function pin: with a timing capacitor attached, sets the internal oscillator rate f (kHz) = 57/C
(µF);
OSC
S
when pulsed low for a duration t
synchronizes device to an external clock.
SYNC
4
5
REF
O
O
Band gap reference output. Decouple to GND with 0.1uF.
PWRGD
Power good, open drain output. Set low whenever the output voltage is not within ±13% of the programmed
value.
6
7
VID0
VID1
VID2
VID3
VID4
FB
I
I
I
I
I
I
I
Bit 0 of the output voltage select DAC. Internal pull up sets input high when not driven.
Bit 1 of the output voltage select DAC. Internal pull up sets input high when not driven.
Bit 2 of the output voltage select DAC. Internal pull up sets input high when not driven.
Bit 3 of the output voltage select DAC. Internal pull up sets input high when not driven.
Bit 4 of the output voltage select DAC. Internal pull up sets input high when not driven.
8
9
10
11
12
Voltage regulation feedback input. Tie to V
for normal operation.
OUT
CS
Current sense. Current feedback input of PWM controller and over current capacitor input. Current limit
threshold set at +154mV with respect to FB. Connect sense resistor between CS and FB for normal
operation.
13
14
15
16
17
18
19
GND
GNDP
LSD
VINP
VIN
S
S
O
S
S
S
O
Ground
Power ground for low side FET driver. Tie to GND for normal operation.
Low side gate drive output.
Input supply voltage for low side FET driver. Tie to VIN for normal operation.
Input supply voltage for control unit.
LX
Negative supply input for high side FET driver.
HSD
High side gate drive output. Driver ground referenced to LX. Driver supply may be bootstrapped to enhance
low controller input voltage operation.
20
VH1
S
Positive supply input for high side FET driver.
NOTE: Pin designators: I = Input, O = Output, S = Supply
3
EL7571
Typical Performance Curves
+12V Supply Sync Line Regulation
0.004
5V Supply Line Regulation
0.30
0.20
0.003
0.002
0.001
0
0.10
0.00
-0.10
-0.20
-0.30
-0.40
-0.001
-0.002
-0.003
13.5
13.0
12.5
12.0
11.5
(V)
11.0
10.5
10.0
5.50
5.25
5.00
(V)
4.75
4.50
V
V
IN
IN
+12V Supply Sync Load Regulation
VRM +5V Supply +12V Controller Sync w/o Schottky Load
Regulation
0.04
0.03
0.02
0.01
0
6.00
5.00
4.00
3.00
2.00
1.00
0
V
= 1.8V
OUT
V
= 2.1V
OUT
V
= 2.8V
OUT
V
= 2.8V
OUT
V
= 3.5V
OUT
V
= 1.3V
OUT
-0.01
-0.02
-1.00
-2.00
V
= 1.8V
OUT
0
1
3
5
I
7
9
11
13
0
1
3
5
7
9
11
13
I
(A)
(A)
OUT
OUT
+5V Supply Non-Sync Load Regulation
+12V Supply Sync Efficiency
5.00
4.00
3.00
2.00
1.00
0
1.0
0.9
0.8
0.7
0.6
0.5
V
= 1.3V
OUT
V
= 1.8V
OUT
V
= 3.5V
OUT
V
= 2.8V
OUT
V
= 2.8V
OUT
V
= 3.5V
OUT
V
= 1.8V
OUT
-1.00
-2.00
0
1
3
5
I
7
9
11
13
0
1
3
5
I
7
(A)
9
11
13
(A)
OUT
OUT
4
EL7571
Typical Performance Curves (Continued)
+5V Supply Sync with Schottky Load
2.5
+5V Supply +12V Controller Sync w/o Schottky VRM
Efficiency
1.0
0.9
0.8
0.7
0.6
0.5
V
= 3.5V
OUT
1.5
0.5
0
V
= 2.8V
OUT
V
= 3.5V
= 1.8V
OUT
V
V
= 1.8V
OUT
OUT
-0.5
-1.5
-2.5
V
= 2.8V
= 1.3V
OUT
V
= 1.3V
OUT
V
OUT
0
1
3
5
7
9
11
13
0.02
1.02
3.04
5.04
7.04
(A)
9.04
11.04 13.04
I
(A)
I
OUT
OUT
+5V Supply Non-Sync VRM Efficiency
+5V Supply Sync with Schottky VRM Efficiency
1.0
0.9
0.8
0.7
0.6
0.5
1.0
0.9
0.8
0.7
0.6
0.5
V
= 3.5V
V
= 3.5V
OUT
OUT
V
= 2.8V
= 1.8V
= 1.3V
OUT
V
= 2.8V
= 1.8V
OUT
V
V
OUT
OUT
V
= 1.3V
V
OUT
OUT
0
1
3
5
7
9
11
13
0
1
3
5
7
9
11
13
I
(A)
OUT
I
(A)
OUT
12V Transient Response
5V Non-sync Transient Response
1
1
5
EL7571
Typical Performance Curves (Continued)
5V Sync Transient Response
5V Input 12V Controller Transient Response
1
1
Efficiency vs Temperature
92.6
V
vs Temperature
REF
1.425
1.420
1.415
1.410
1.405
1.400
1.395
1.390
92.5
92.4
92.2
92.0
91.8
91.6
-45
-30
-15
0
15
30
45
60
-45
-30
-15
0
15
30
45
60
Temperature (°C)
Temperature (°C)
Frequency vs Temperature
280
270
260
250
240
230
220
210
200
-45
-30
-15
0
15
30
45
60
Temperature (°C)
6
EL7571
resulting error voltage is compared with the compensating
Applications Information
ramp and current feedback voltage. PWM duty cycle is
adjusted by the comparator output such that the combined
comparator input sums to zero. A weighted comparator
scheme enhances system operation over traditional voltage
error amplifier loops by providing cycle-by-cycle adjustment
of the PWM output voltage, eliminating the need for error
amplifier compensation. The dominant pole in the loop is
defined by the output capacitance and equivalent load
resistance, the effect of the output inductor having been
canceled due to the current feedback. An output enable
(OUTEN) input allows the regulator output to be disabled by
an external logic control signal.
Circuit Description
General
The EL7571 is a fixed frequency, current mode, pulse width
modulated (PWM) controller with an integrated high
precision reference and a 5 bit Digital-to-Analog Converter
(DAC). The device incorporates all the active circuitry
required to implement a synchronous step down (buck)
converter which conforms to the Intel Pentium® II VRM
specification. Complementary switching outputs are
provided to drive dual NMOS power FET’s in either
synchronous or non-synchronous configurations, enabling
the user to realize a variety of high efficiency and low cost
converters.
Auxiliary Comparators
The current feedback signal is monitored by two additional
comparators which set the operating limits for the main
inductor current. An over current comparator terminates the
PWM cycle independently of the main summing comparator
output whenever the voltage across the sense resistor
exceeds 154mV. For a 7.5mΩ resistor this corresponds to a
nominal 20A current limit. Since output current is
Reference
A precision, temperature compensated band gap reference
forms the basis of the EL7571. The reference is trimmed
during manufacturing and provides 1% set point accuracy for
the overall regulator. AC rejection of the reference is
optimized using an external bypass capacitor C
.
continuously monitored, cycle-by-cycle current limiting
results. A second comparator senses inductor current
reverse flow. The low side drive signal is terminated when
the sense resistor voltage is less than -5mV, corresponding
to a nominal reverse current of -0.67A, for a 7.5mΩ sense
resistor. Additionally, under fault conditions, with the
regulator output over-voltage, inductor current is prevented
from ramping to a high level in the reverse direction. This
prevents the parasitic boost action of the local power supply
when the fault is removed and potential damage to circuitry
connected to the local supply.
REF
Main Loop
A current mode PWM control loop is implemented in the
EL7571 (see block diagram). This configuration employs
dual feedback loops which provide both output voltage and
current feedback to the controller. The resulting system
offers several advantages over tradititional voltage control
systems, including simpler loop design, pulse by pulse
current limiting, rapid response to line variaion and good
load step response. Current feedback is performed by
sensing voltage across an external shunt resistor. Selection
of the shunt resistance value sets the level of current
feedback and thereby the load regulation and current limit
levels. Consequently, operation over a wide range of output
currents is possible. The reference output is fed to a 5 bit
DAC with step weighing conforming to the Intel VRM
Specification. Each DAC input includes an internal current
pull up which directly interfaces to the VID output of a
Pentium® II class microprocessor. The heart of the controller
is a triple-input direct summing differential comparator, which
sums voltage feedback, current feedback and compensating
ramp signals together. The relative gains of the comparator
input stages are weighed. The ratio of voltage feedback to
current feedback to compensating ramp defines the load
regulation and open loop voltage gain for the system,
respectively. The compensating ramp is required to maintain
large system signal system stability for PWM duty cycles
greater than 50%. Compensation ramp amplitude is user
adjustable and is set with a single external capacitor
Oscillator
A system clock is generated by an internal relaxation
oscillator. Operating frequency is simple to adjust using a
single external capacitor C
. The ratio of charge to
OSC
discharge current in the oscillator is well defined and sets the
maximum duty cycle for the system at around 96%.
Soft-start
During start-up, potentially large currents can flow into the
regulator output capacitors due to the fast rate of change of
output voltage caused during start-up, although peak inrush
current will be limited by the over current comparator.
However an additionally internal switch capacitor soft-start
circuit controls the rate of change of output voltage during
start-up by overriding the voltage feedback input of the main
summing comparator, limiting the start-up ramp to around
1ms under typical operating conditions. The soft-start ramp
is reset whenever the output enable (OUTEN) is reset or
whenever the controller supply falls below 3.5V.
(C
). The ramp voltage is ground referenced and is
SLOPE
reset to ground whenever the high side drive signal is low. In
operation, the DAC output voltage is compared to the
regulator output, which has been internally attenuated. The
Watchdog
A system watchdog monitors the condition of the controller
supply and the integrity of the generated output voltage.
7
EL7571
Modern logic level power FET’s rapidly increase in resistivity
(R ) as their gate drive is reduced below 5V. To prevent
thermal damage to the power FET’s under load, with a
reduced supply voltage, the system watchdog monitors the
level shift circuit. Each driver is capable of delivering nominal
peak output currents of 2A at 12V. To prevent shoot-through
in the external FET’s, each driver is disabled until the gate
voltage of the complementary power FET has fallen to less
than 1V. Supply connections for both drivers are
DS-ON
controller supply (V ) and disables both PWM outputs
IN
(HSD, LSD) when the supply voltage drops below 3.5V.
When the supply voltage is increased above 4V the
watchdog initiates a soft-start ramp and enables PWM
operation. The difference between enable and disable
thresholds introduces hysteresis into the circuit operation,
preventing start-up oscillation. In addition, output voltage is
also monitored by the watchdog. As called out by the Intel
Pentium® II VRM specification, the watchdog power good
output (PWRGD) is set low whenever the output voltage
differs from it’s selected value by more than ±13%. PWRGD
is an open drain output. A third watchdog function disables
PWM output switching during over-voltage fault conditions,
displaying both external FET drives, whenever the output
voltage is greater than 13% of its selected value, thereby
anticipating reverse inductor current ramping and
conforming to the VRM over-voltage specification, which
requires the regulator output to be disabled during fault
conditions. Switching is enabled after the fault condition is
removed.
independent, allowing the controller to be configured with a
boot-strapped high side drive. Employing this technique a
single supply voltage may be used for both power FET’s and
controller. Alternatively, the application may be simplified
using dual supply rails with the power FET’s connected to a
secondary supply voltage below the controller’s, typically
12V and 5V. For applications where efficiency is less
important than cost, applications can be further simplified by
replacing the low side power FET with a Schottky diode,
resulting in non-synchronous operation.
Applications Information
The EL7571 is designed to meet the Intel 5 bit VRM
specification. Refer to the VID decode table for the controller
output voltage range.
The EL7571 may be used in a number converter topologies.
The trade-off between efficiency, cost, circuit complexity, line
input noise, transient response and availability of input
supply voltages will determine which converter topology is
suitable for a given application. The following table lists some
of the differences between the various configurations:
Output Drivers
Complementary control signals developed by the PWM
control loop are fed to dual NMOS power FET drivers via a
Converter Topologies
TRANSIENT
TOPOLOGY
5V only Non-synchronous
5V only Synchronous
DIAGRAM
figure 1
EFFICIENCY
92%
COST
low
COMPLEXITY INPUT NOISE RESPONSE
low
high
high
high
high
high
good
good
good
good
best
figure 2
95%
higher
lowest
high
higher
lowest
high
5V &12V Non-synchronous
5V & 12V Synchronous
12V only Synchronous
figure 3
92%
figure 4
95%
Connection Diagram
92%
highest
highest
Circuit schematics and Bills of Material (BOMs) for the
Although many factors influence the choice of the inductor
value, including efficiency, transient response and ripple
current, one practical way of sizing the inductor is to select a
value which maintains continuous mode operation, i.e.
inductor current positive for all conditions. This is desirable to
optimize load regulation and light load transient response.
When the minimum inductor ripple current just reaches zero
various topologies are provided at the end of this data sheet.
If your application requirements differ from the included
samples, the following design guide lines should be used to
select the key component values. Refer to the front page
connection diagram for component locations.
Output Inductor, L
1
and with the mean ripple current set to I
, peak inductor
MIN
Two key converter requirements are used to determine
inductor value:
ripple current is twice I , independent of duty cycle. The
MAX
minimum inductor value is given by:
• I
MIN
- minimum output current; the current level at which
the converter enters the discontinuous mode of operation
(refer to Elantec application note #18 for a detailed
discussion of discontinuous mode)
(V – V
) × T
(V – V
) × V
OUT OUT
IN
OUT
ON
IN
L
= ------------------------------------------------------- = -----------------------------------------------------------
1MIN
1
V
× F
× 2 × I
SW MIN
PEAK
IN
• I
- maximum output current
MAX
8
EL7571
where:
current limiting. A resistor value must be selected which
guarantees operation under maximum load. That is:
I
= peak ripple current
= top switch on time
PEAK
V
OCMIN
T
R
= ----------------------
ON
1
1
MAX
V
= input voltage
IN
where:
F
= switching frequency
SW
V
= minimum over current voltage threshold
= maximum output current
MAX
V
= output voltage
= minimum load
OCMIN
OUT
I
I
MIN
Secondly, since the load current passes directly through the
sense resistor, its power rating must be sufficient to handle
the power dissipated during maximum load (current limit)
conditions. Thus:
Since inductance value tends to decrease with current,
ripple current will generally be greater than 21
output current.
at higher
MIN
Once the minimum output inductance is determined, an off
the shelf inductor with current rating greater than the
maximum DC output required can be selected. Pulse
Engineering and Coil Craft are two manufactures of high
current inductors. For converter designers who want to
design their own high current inductors, for experimental
purposes or to further reduce costs, we recommend the
Micrometals Powered Iron Cores data sheet and
applications note as a good reference and starting point.
2
P
= 1
× R
1
D
OUTMAX
where:
= power dissipated in current sense resistor
P
D
P
must be less than the power rating of the current sense
D
resistor. High current applications may require parallel sense
resistors to dissipate sufficient power. Current Sense
Resistor Table below lists some popular current sense
resistors: the WLS-2512 series of Power Metal Strip
Resistors from Dale Electronics, OARS series Iron Alloy
resistor from IRC, and Copper Magnanin (CuNi) wire resistor
from Mills Resistors. Mother board copper trace is not
recommended because of its high temperature coefficient
and low power dissipation. The trade-off between the
different types of resistors are cost, space, packaging and
performance. Although Power Metal Strip Resistors are
relatively expensive, they are available in surface mount
packaging with tighter tolerances. Consequently, less board
space is used to achieve a more accurate current sense.
Alternatively, Magnanin copper wire has looser tolerance
and higher parasitic inductance. This results in a less current
sense but at a much lower cost. Metal track on the PCB can
also be used as current sense resistor. The trade-offs are
±30% tolerance and ±4000 ppm temperature coefficient.
Ultimately, the selection of the type of current sense element
must be made on an application by application basis.
Current Sense Resistor, R
1
Inductor current is monitored indirectly via a low value
resistor R . The voltage developed across the current sense
1
resistor is used to set the maximum operating current, the
current reversal threshold and the system load regulation. To
ensure reliable system operation it is important to sense the
actual voltage drop across the resistor. Accordingly a four
wire Kelvin connection should be made to the controller
current sense inputs. There are two criteria for selecting the
resistor value and type. Firstly, the minimum value is limited
by the maximum output current. The EL7571 current limit
capacitor has a typical threshold of 154mV, 125mV
minimum. When the voltage across the sense resistor
exceeds this threshold, the conduction cycle of the top
switch terminates immediately, providing pulse by pulse
Bill of Materials
TEMPERATURE
MANUFACTURER
Dale
PART NO.
WSL 2512
TOLERANCE
±1%
COEFFICIENT
POWER RATING
1W
PHONE NO.
402-563-6506
800-472-6467
916-422-5461
FAX NO.
±75ppm
402-563-6418
800-472-3282
906-422-1409
IRC
OARS Series
MRS1367-TBA
±5%
±20ppm
1W - 5W
Mills Resistor
PCB Trace Resistor
±10%
±20ppm
1.2W
±30%
±4000ppm
50A/in (1oz Cu)
9
EL7571
(ESL) of the output capacitor in addition to the rate of change
and magnitude of the load current step. The output voltage
transient is given by:
Input Capacitor, C
1
In a buck converter, where the output current is greater than
10A, significant demand is placed on the input capacitor.
Under steady state operation, the high side FET conducts
only when it is switched “on” and conducts zero current when
it is turned “off”. The result is a current square wave drawn
from the input supply. Most of this input ripple current is
d
i
----
∆V
=
ESR
× ∆I
+ ESL ×
OUT
OUT
OUT
d
t
where:
ESR
supplied from the input capacitor C . The current flow
1
= output capacitor ESR
OUT
through C ’s equivalent series resistance (ESR) can heat up
1
the capacitor and cause premature failure. Maximum input
ripple current occurs when the duty cycle is 50%, a current
ESL = output capacitor ESL
∆I = output current step
OUT
d /d = rate of change of output current
of I
/2 RMS.
OUT
i
t
Worst case power dissipation is:
Power MOSFET, Q and Q
1
2
2
I
OUT
2
-------------
P
=
• ESR
IN
The EL7571 incorporates a boot-strap gate drive scheme to
allow the usage of N-channel MOSFETs. N-channel
MOSFETs are preferred because of their relative low cost
and low on resistance. The largest amount of the power loss
occurs in the power MOSFETs, thus low on resistance
should be the primary characteristic when selecting power
MOSFETs. In the boot-strap gate drive scheme, the gate
drive voltage can only go as high as the supply voltage,
therefore in a 5V system, the MOSFETs must be logic level
D
where:
ERS = input capacitor ESR
IN
For safe and reliable operation, P must be less than the
D
capacitor’s data sheet rating.
Input Inductor, L
2
type, V <4.5V. In addition to on resistance and gate to
GS
The input inductor (L ) isolates switching noise from the
2
source threshold, the gate to source capacitance is also very
important. In the region when the output current is low
(below 5A), switching loss is the dominant factor. Switching
loss is determined by:
input supply line by diverting buck converter input ripple
current into the input capacitor. Buck regulators generate
high levels of input ripple current because the load is
connected directly to the supply through the top switch every
cycle, chopping the input current between the load current
and zero, in proportion to the duty cycle. The input inductor
is critical in high current applications where the ripple current
is similarly high. An exclusively large input inductor degrades
the converter’s load transient response by limiting the
maximum rate of change of current at the converter input. A
1.5µH input inductor is sufficient in most applications.
2
P = C × V × F
where:
C is the gate to source capacitance of the MOSFET
V is the supply voltage
F is the switching frequency
Output Capacitor, C
2
Another undesirable reason for a large MOSFET gate to
source capacitance is that the on resistance of the MOSFET
driver can not supply the peak current required to turn the
MOSFET on and off fast. This results in additional MOSFET
conduction loss. As frequency increases, this loss also
increases which leads to more power loss and lower
efficiency.
During steady state operation, output ripple current is much
less than the input ripple current since current flow is
continuous, either via the top switch or the bottom switch.
Consequently, output capacitor power dissipation is less of a
concern than the input capacitor’s. However, low ESR is still
required for applications with very low output ripple voltage
or transient response requirements. Output ripple voltage is
given by:
Finally, the MOSFET must be able to conduct the maximum
current and handle the power dissipation.
V
= I
× ESR
RIP OUT
RIP
The EL7571 is designed to boot-strap to 12V for 12V only
input converters. In this application, logic level MOSFETs
are not required.
where:
I
= output ripple current
RIP
The following table below lists a few popular MOSFETs and
their critical specifications.
ESR
= output capacitor ESR
OUT
During a transient response, the output voltage spike is
determined by the ESR and the equivalent series inductance
10
EL7571
MANUFACTURER
MegaMos
MegaMos
Siliconix
Fuji
MODEL
Mi4410
V
R
(MAX)
C
GS
ID
VDS
30V
30V
30V
PACKAGE
SO-8
GS
ON
4.5V
4.5V
4.5V
4V
20mΩ
6.4nF
6.3nF
4.3nF
±10A
±15A
±10A
±17.5A
±98A
±75A
Mip30N03A
Si4410
22mΩ
20mΩ
37mΩ
8mΩ
TO-220
SO-8
2SK1388
TO-220
D2Pak
TO-220
IR
IRF3205S
MTB75N05HD
4
17nF (max)
7.1nF
55V
50V
Motorola
4
7mΩ
The product of forward voltage drop and condition current is
a primary source of power dissipation in the convertor. The
Schottky diode selected is the International Rectifier
Skottky Diode, D
2
In the non-synchronous scheme a flyback diode is required
to provide a current path to the output when the high side
32CTQ030 which has 0.4V of forward voltage drop at 15A.
power MOSFET, Q , is switched off. The critical criteria for
1
selecting D is that it must have low forward voltage drop.
2
Block Diagram
In Regulation
ENABLE
0.1µF
REF
1.5µH
L
C
V
OTEN
FB
C
PWRGD
V
INP
2
1
IN
S
4.5V to
12.6V
3mF
+
-
Reference
+
-
V
HI
4V
UVLO HI
+
-
HSD
Current Reversal
+
-
UVLO LOW
0.1µF
5.1µH
+
-
LX
3.5V
+
-
L
V
OUT
1
VID
(0:4)
DAC
+
-
PWM
Control Logic
∑
LSD
7.5mΩ
C
2
6mF
+
-
C
SLOPE
Soft
Start
Ramp Control
240pF
220pF
ENABLE
C
OSC
Oscillator
GND GNDP
11
EL7571
Voltage ID Code Output Voltage Settings
V
V
V
V
V
V
OUT
ID4
ID3
ID2
ID1
ID0
0
1
1
1
1
1.3
1.35
1.4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1.45
1.5
1.55
1.6
1.65
1.7
1.75
1.8
1.85
1.9
1.95
2.0
2.05
0, No CPU
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
Application Circuits
To assist the evaluation of EL7571, several VRM
applications have been developed. These are described in
the converter topologies table earlier in the data sheet. The
demo board can be configured to operate with either a 5V or
12V controller supply, using a 5V FET supply.
12
EL7571
5V Input, Boot-Strapped Non-Synchronous DC:DC Converter
5Ω
R2
D1
C6
ENABLE
1
2
3
4
5
6
7
8
9
OTEN
CSLOPE
COSC
REF
VH1 20
0.1µF
240pF
1µH
L2
HSD
19
Q1
C3
C4
C8
C1
5V
1000µF
x3
1µF
LX 18
220pF
VOUT
1.4V
V1H 17
L1
5.1µH
R1
C5
0.1µF
POWER
C7
0.1µF
C2
7.5mΩ
VINP
16
15
14
13
12
PWRGD
VIDO
1000µF
x6
D2
GOOD
LSD
GNDP
GND
CS
VID1
VID2
Voltage
LD.
(VID(0:4))
VID3
10 VID4
FB 11
EL7571 5V VRM Bill of Materials - 5V Non Sync Solution
COMPONENT
MANUFACTURER
PART NUMBER
VALUE
1000µF
1000µF
240pF
220pF
0.1µF
UNIT
C1
C2
Sanyo
6MV1000GX
3
6
1
1
2
2
1
1
1
1
2
1
1
2
Sanyo
6MV1000GX
C3
Chip Capacitors
Chip Capacitors
Chip Capacitors
Chip Capacitors
C4
C5, C6
C7, C8
D1
1µF
GI
Elantec
Schotty diode SS12GICT-ND
EL7571CM
IC1
L1
Pulse Engineering
Micrometals
DALE
PE-53700
5.1µH
1µH
L2
T30-26,7T AWG #20
WSL-2512
R1
15mΩ
5Ω
R2
Chip Resistor
IR32CTQ030
Si4410
D2
IR
Q1
Siliconix
13
EL7571
5V Input Boot-Strapped Synchronous DC:DC Converter
5Ω
R2
D1
C6
ENABLE
1
2
3
4
5
6
7
8
9
OTEN
CSLOPE
COSC
REF
VH1 20
0.1µF
240pF
1.5µH
L2
HSD
19
Q1
C3
C4
C8
C1
5V
1000µF
x3
1µF
LX 18
220pF
1.4V
V1H 17
VOUT
C2
L1
5.1µH
D2
R1
7.5mΩ
C5
0.1µF
POWER
C7
VINP
16
15
14
13
12
PWRGD
VIDO
1000µF
x6
0.1µF
GOOD
LSD
GNDP
GND
CS
Q2
VID1
VID2
Voltage
LD.
(VID(0:4))
VID3
10 VID4
FB 11
EL7571 5V VRM Bill of Materials - 5V Non Sync Solution
COMPONENT
MANUFACTURER
PART NUMBER
VALUE
1000µF
1000µF
240pF
220pF
0.1µF
UNIT
C1
C2
Sanyo
6MV1000GX
6MV1000GX
3
Sanyo
6
C3
Chip Capacitors
Chip Capacitors
Chip Capacitors
Chip Capacitors
1
C4
1
C5, C6
C7, C8
D1
2
1µF
2
GI
Elantec
Schotty diode SS12GICT-ND
EL7571CM
1
IC1
1
L1
Pulse Engineering
Micrometals
DALE
PE-53700
5.1µH
1µH
1
L2
T30-26,7T AWG #20
WSL-2512
1
R1
15mΩ
5Ω
2
R2
Chip Resistor
IR32CTQ030
Si4410
1
1
D2
IR
Q1, Q2
Siliconix
2 each
14
EL7571
5V Input, 12V Controller, Non-Sync Solution
12V
5Ω
ENABLE
1
2
3
4
5
6
7
8
9
OTEN
VH1 20
R2
220pF
1µH
L2
HSD
CSLOPE
19
Q1
C3
C4
C8
C1
5V
1000µF
x3
1µF
LX 18
COSC
REF
220pF
1.4V
V1H 17
L1
5.1µH
R1
7.5mΩ
VOUT
C2
C5
C7
0.1µF
POWER
VINP
16
15
14
13
12
PWRGD
VIDO
VID1
1000µF
x6
0.1µF
GOOD
LSD
GNDP
GND
CS
Q2
VID2
Voltage
LD.
(VID(0:4))
VID3
10 VID4
FB 11
EL7571 5V VRM Bill of Materials - 5V Non Sync Solution
COMPONENT
MANUFACTURER
PART NUMBER
VALUE
1000µF
1000µF
240pF
220pF
0.1µF
UNIT
C1
C2
Sanyo
6MV1000GX
3
6
1
1
1
2
1
1
1
2
1
1
2
Sanyo
6MV1000GX
C3
Chip Capacitors
Chip Capacitors
Chip Capacitors
Chip Capacitors
EL7571CM
C4
C5
C7, C8
IC1
L1
1µF
Elantec
Pulse Engineering
Micrometals
DALE
PE-53700
5.1µH
1µH
L2
T30-26,7T AWG #20
WSL-2512
R1
15mΩ
5Ω
R2
Chip Resistor
IR32CTQ030
Si4410
D2
IR
Q1
Siliconix
15
EL7571
5V Input, 12V Controller, Synchronous DC:DC Converter
12V
C6
0.1µF
ENABLE
1
2
3
4
5
6
7
8
9
OTEN
CSLOPE
COSC
REF
VH1 20
330pF
1.5µH
L2
HSD
19
Q1
C3
C4
C8
C1
5V
1000µF
x3
1µF
LX 18
330pF
1.4V
V1H 17
L1
5.1µH
R1
7.5mΩ
VOUT
C2
C5
C7
0.1µF
0.1µF
POWER
VINP
16
15
14
13
12
PWRGD
VIDO
1000µF
x6
GOOD
LSD
GNDP
GND
CS
D2
VID1
VID2
Voltage
LD.
(VID(0:4))
VID3
10 VID4
FB 11
EL7571 5V VRM Bill of Materials - 5V Input, 12V Controller Sync Solution
COMPONENT
MANUFACTURER
PART NUMBER
6MV1000GX
6MV1000GX
Chip Capacitors
Chip Capacitors
Chip Capacitors
Chip Capacitors
EL7571CM
VALUE
1000µF
1000µF
330pF
330pF
0.1µF
UNIT
C1
C2
Sanyo
3
Sanyo
6
C3
1
C4
1
C5, C6
C7, C8
IC1
2
1µF
2
Elantec
Pulse Engineering
Micrometals
DALE
1
L1
PE-53700
5.1µH
1µH
1
L2
T30-26,7T AWG #20
WSL-2512
1
R1
15mΩ
2
1
D2
IR
IR32CTQ030
Si4410
Q1, Q2
Siliconix
2 each
16
EL7571
in the converter and should be used as the reference
ground.
PCB Layout Considerations
1. Place the power MOSFET’s as close to the controller as
possible. Failure to do so will cause large amounts of
ringing due to the parasitic inductance of the copper
trace. Additionally, the parasitic capacitance of the trace
will weaken the effective gate drive. High frequency
switching noise may also couple to other control lines.
5. The power MOSFET’s output inductor and Schottky
diode should be grouped together to contain high
switching noise in the smallest area.
6. Current sense traces running from pin 11 and pin 12 to
the current sense resistor should run parallel and close to
each other and be Kelvin connected (no high current
flow). In high current applications performance can be
improved by connecting low Pass filter (typical values
4.7Ω, 0.1µF) between the sense resistor and the IC
inputs.
2. Always place the by-pass capacitors (0.1µF and 1µF) as
close to the EL7571 as possible. Long lead lengths will
lessen the effectiveness.
3. Separate the power ground (input capacitor ground and
ground connections of the Schottky diode and the power
MOSFET’s) and signal grounds (ground pins of the by-
pass capacitors and ground terminals of the EL7571).
This will isolate the highly noisy switching ground from the
very sensitive signal ground.
Layout Example
To demonstrate the points discussed above, below shows
two reference layouts - a synchronous 5V only VRM layout
and a synchronous 5V only PC board layout. Both layouts
can be modified to any application circuit configuration
shown on this data sheet. Gerber files of the layouts are
available from the factory.
4. Connect the power and signal grounds at the output
capacitors. Output capacitor ground is the quietest point
Top Layer Silkscreen
Bottom Layer Silkscreen
17
EL7571
Top Layer Metal
Bottom Layer Metal
Top Layer Silkscreen
18
EL7571
Top Layer Metal
Bottom Layer Metal
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
19
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