EL7584IR-T13 [INTERSIL]
4-Channel DC:DC Converter; 4通道DC ： DC转换器
| 型号： | EL7584IR-T13 |
| 厂家： | 
Intersil |
| 描述： | 4-Channel DC:DC Converter |
| 文件： | 总16页 (文件大小：805K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EL7584
®
Data Sheet
February 4, 2005
FN7317.2
4-Channel DC/DC Converter
Features
• TFT-LCD display supply
- Boost regulator
The EL7584 is a 4-channel DC/DC converter IC which is
designed primarily for use in TFT-LCD applications. The
boost converter has 2V to 14V input capability and provides
5V to 17V output, which powers the column drivers and
provides up to 370mA @ 15V. A pair of charge pump control
circuits provide outputs to allow the external generation of
- V
- V
- V
buffer
charge pump
charge pump
COM
ON
OFF
• 2V to 14V V supply
IN
V
and V
supplies at 5V to 40V and 0V to -40V,
= 15V. The
buffer provides up to 50mA continuous output current
ON
OFF
respectively, each at up to 60mA for V
BOOST
• 5V < V
• 2V < V
• 5V < V
< 17V
BOOST
V
COM
from 2V to 13V.
< 13V
COM
< 40V
ON
The EL7584 features adjustable switching frequency and on-
chip power sequence to simplify start-up operation. A
separate input is available to externally increase the default
delay of the positive charge pump. An over-temperature
feature is provided to allow the IC to be automatically
protected from excessive power dissipation.
• -40V < V
OFF
< 0V
• V
BOOST
= 15V @ 370mA
• High frequency, small inductor DC/DC boost circuit
• Over 90% efficient DC/DC boost converter capability
The EL7584 is available in a 24-pin TSSOP package and is
specified for operation over the full -40°C to +85°C
temperature range.
• Built-in power-up sequence with adjustable V
• Adjustable frequency
delay
ON
• Adjustable soft-start
Pinout
• Adjustable outputs
EL7584
(24-PIN TSSOP)
TOP VIEW
• Over-temperature protection
• Small parts count
• Pb-free available (RoHS compliant)
SS
FBB
1
2
3
4
5
6
7
8
9
24 VSSB
23 ROSC
22 VREF
21 PGND
20 PGND
19 VSSP
18 DRVP
17 VDDP
16 FBP
Applications
• TFT-LCD panels
• PDAs
EN
VDDB
LX1
Ordering Information
PART
LX2
NUMBER
PACKAGE
24-Pin TSSOP
24-Pin TSSOP
TAPE & REEL PKG. DWG. #
VSSN
DRVN
VDDN
EL7584IR
EL7584IR-T7
-
7”
13”
-
MDP0044
MDP0044
MDP0044
MDP0044
EL7584IR-T13 24-Pin TSSOP
EL7584IRZ
(See Note)
24-Pin TSSOP
(Pb-free)
FBN 10
DP 11
15 VSSC
14 VCOM
13 VDDC
EL7584IRZ-T7 24-Pin TSSOP
7”
MDP0044
MDP0044
(See Note)
(Pb-free)
INC 12
EL7584IRZ-
T13 (See Note)
24-Pin TSSOP
(Pb-free)
13”
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding
compounds/die attach materials and 100% matte tin plate termination finish, which are
RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
1
Copyright © Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc.
All other trademarks mentioned are the property of their respective owners.
EL7584
Absolute Maximum Ratings (T = 25°C)
A
LX Pin Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
V
V
, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18V
, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5V
DDB DDP DDN
DDC
Maximum Continuous V
Output Current. . . . . . . . . . . 800mA
BOOST
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T = T = T
J
C
A
Electrical Specifications
V
= 3.3V, V
= 12V, R = 62kΩ, T = 25°C, Unless Otherwise Specified.
OSC A
IN
BOOST
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
DC/DC BOOST CONVERTER
IQ1_B
IQ2_B
V(FBB)
Quiescent Current - Shut-down
Quiescent Current - Switching
Feedback Voltage
EN = 0V
0.8
4.8
10
8
µA
mA
V
EN = V
DDB
1.275
1.260
1.260
1.300
1.310
1.325
0.1
1.325
1.360
1.390
V
V
Reference Voltage
V
REF
Oscillator Set Voltage
Feedback Input Bias Current
Boost Converter Supply Range
Maximum Duty Cycle
Peak Internal FET Current
Switch On Resistance
Switch Leakage Current
Output Range
V
ROSC
I(FBB)
µA
V
V
2
17
DDB
D
85
92
%
MAX
I(LX)
1.75
0.22
A
MAX
R
at V
= 10V, I(LX) total = 350mA
Ω
DS-ON
BOOST
I
I(LX) total
1
µA
V
LEAK-SWITCH
V
V
> V + V
5
17
BOOST
BOOST
IN DIODE
∆V
∆V
/∆V
BOOST
Line Regulation
2.7V < V < 13.2V, V
IN
= 15V
BOOST
0.1
0.5
%
IN
/∆I
Load Regulation
50mA < I < 250mA
O1
%
BOOST O1
OSC-RANGE
OSC1
F
F
Frequency Range
R
range = 240kΩ to 60kΩ
= 62kΩ
200
900
1200
1100
kHz
kHz
OSC
OSC
Switching Frequency
R
1000
V
BUFFER
COM
V
Supply Voltage Range
6
15
20
V
DDC
IQ1, V
IQ2, V
V
V
Disable Current
Enable Current
V
V
= 12V, EN = 0V
5.5
1.7
µA
mA
mV
µA
Ω
DDC
DDC
DDC
DDC
DDC
= 12V, V
= V
, no load
DDB
5
DDC
EN
V
-offset
Accuracy of V
Output Voltage
2V < V
< (V
- 2V)
-10
+10
0.1
COM
I(INC)
R (V
COM
COM
DDC
V
V
Input Bias Currents
Output Impedance
Current magnitude
-0.1
0.01
0.25
COM
COM
)
V
= V
= 12V, V
< 100mA
= 6V with
COM
O
COM
DDC
BOOST
LOAD
-100mA < I
C
for V
> 0.47µF, MLCC
COM
LOAD
I
(max)
Output Current Limit
150
102
93
mA
dB
dB
COM
PSRR
CMRR
Supply Voltage Rejection
Common Mode Voltage Rejection
V
V
= V
, 9V < V
< 15V
60
60
INC
DDC/2
DDC
= 12V, 2V < V
< 10V
DDC
INC
FN7317.2
2
February 4, 2005
EL7584
Electrical Specifications
V
= 3.3V, V
BOOST
= 12V, R
OSC
= 62kΩ, T = 25°C, Unless Otherwise Specified. (Continued)
IN
DESCRIPTION
POSITIVE REGULATED CHARGE PUMP (V
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
)
ON
output depends on the magnitude of the V
Most positive V
input voltage (normally connected to V
) and the external component
ON
DDP
BOOST
configuration (doubler or tripler)
V
Supply Input for Positive Charge Pump
Quiescent Current - Shut-down
Quiescent Current - Switching
Disable Charge Current
Usually connected to V
output
BOOST
5
17
20
V
µA
DDP
IQ1(V
)
)
EN = 0V
EN = V
11.5
2.3
DDP
IQ2(V
5
mA
mA
nA
DDP
DDB
EN = 0V, DP = 0V
EN = V , DP = 5V
I
I
1.5
1.9
2.5
300
1.375
DP1
DP2
Enable Discharge Current
100
200
1.310
0.1
DDB
V(FBP)
I(FBP)
Feedback Reference Voltage
Feedback Input Bias Current
RMS DRVP Output Current
1.245
V
µA
I(DRVP)
V
V
= 12V
= 6V
60
mA
mA
%/mA
DDP
DDP
15
ILR_V
Load Regulation
5mA < I < 15mA
L
-0.5
0.03
0.5
ON
F
Charge Pump Frequency
Frequency set by R
- see boost section
0.5*F
OSC
PUMP
OSC
NEGATIVE REGULATED CHARGE PUMP (V
)
OFF
output depends on the magnitude of the V
Most negative V
input voltage (normally connected to V
) and the external component
OFF
DDN
BOOST
configuration (doubler or tripler)
V
Supply Input for Negative Charge Pump Usually connected to V
output
BOOST
5
17
20
5
V
µA
DDN
IQ1(V
IQ2(V
)
)
Quiescent Current - Shut-down
Quiescent Current - Switching
Feedback Reference Voltage
Feedback Input Bias Current
RMS DRVN Output Current
ENBN = 0V
ENBN = V
4.5
2.3
0
DDN
DDN
mA
mV
µA
DDB
V(FBN)
I(FBN)
-80
+80
Magnitude of input bias
0.1
60
I(DRVN)
V
V
= 12V
= 6V
mA
mA
%/mA
DDN
DDN
15
ILR_V
Load Regulation
-15mA < I < -5mA
L
-0.5
0.03
0.5
OFF
F
Charge Pump Frequency
Frequency set by R
- see boost section
0.5*F
OSC
PUMP
OSC
ENABLE CONTROL LOGIC
V
V
-EN
Enable Input High Threshold
Enable Input Low Threshold
Enable Input Bias Current
1.6
V
V
HI
-EN
0.5
7.5
LO
I(EN)
V
= 5V
3.7
µA
EN
OVER-TEMPERATURE PROTECTION
T
T
Over-temperature Threshold
Over-temperature Hysteresis
130
40
°C
°C
OT
HYS
FN7317.2
3
February 4, 2005
EL7584
Pin Descriptions I = Input, O = Output, S = Supply
PIN NUMBER
PIN NAME
PIN TYPE
PIN FUNCTION
Soft-Start input: a capacitor determines the current limit ramp time.
Voltage feedback input determines the value of V
1
2
3
SS
I
I
I
FBB
.
BOOST
EN
Starts internal power sequencing of V
, V
, V
and V
outputs
ON
BOOST OFF COM
(See Applications Information) ; active HIGH input.
4
VDDB
LX1
P
O
O
P
O
P
I
Positive supply for V DC/DC controller.
BOOST
5
Boost inductor saturating MOSFET #1.
Boost inductor saturating MOSFET #2.
6
LX2
7
VSSN*
DRVN
VDDN
FBN
Ground return for V
regulator.
OFF
Pump capacitor driver for V
8
regulator.
OFF
regulator.
9
Positive supply for V
OFF
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Voltage feedback input determines the value of V
.
OFF
power up delay time.
DP
I
An external capacitor increases V
ON
INC
I
V
Buffer input.
COM
Positive supply for V
VDDC
VCOM
VSSC*
FBP
P
O
P
I
Buffer.
COM
V
Buffer output.
COM
Ground return for V
Buffer.
COM
Voltage feedback input determines the value of V
.
ON
VDDP
DRVP
VSSP*
PGND*
PGND*
VREF
ROSC
VSSB*
P
O
P
P
P
O
I
Positive supply for V
regulator.
Pump capacitor driver for V regulator.
ON
ON
regulator.
Ground return for V
ON
Ground return for MOSFET #1.
Ground return for MOSFET #2.
Voltage reference for V
feedback .
OFF
An external resistor sets the DC/DC switching frequency.
Ground return for V DC/DC controller.
P
BOOST
NOTE: *VSSB, VSSC, VSSN, VSSP, and PGND (2) are shorted internally to the device substrate.
FN7317.2
February 4, 2005
4
EL7584
Typical Performance Curves
95
90
95
90
85
80
75
70
65
60
9V
5V
85
12V
9V
15V
12V
80
75
70
65
60
55
50
15V
V
=3.3V
V =5V
IN
FREQ=1MHz
IN
FREQ=1MHz
0
100 200 300 400 500 600 700 800
(mA)
0
100 200 300 400 500 600 700 800
(mA)
I
I
OUT
OUT
FIGURE 1. EFFICIENCY vs I
FIGURE 2. EFFICIENCY vs I
OUT
OUT
95
90
85
80
75
70
65
60
95
90
85
80
75
70
65
60
12V
15V
9V
5V
9V
12V
15V
V
=3.3V
V
=5V
IN
IN
FREQ=700kHz
FREQ=700kHz
0
100 200 300 400 500 600 700 800
(mA)
0
100 200 300 400 500 600 700 800
(mA)
I
I
OUT
OUT
FIGURE 3. EFFICIENCY vs I
FIGURE 4. EFFICIENCY vs I
OUT
OUT
1.27
970
R
= 61.9kΩ
969
968
967
966
965
964
963
962
OSC
1.265
1.26
1.255
1.25
-50
0
50
100
150
3
3.5
4
4.5
(V)
5
5.5
6
TEMPERATURE (°C)
V
DDB
FIGURE 6. V
vs TEMPERATURE
REF
FIGURE 5. F vs V
S
DDB
FN7317.2
February 4, 2005
5
EL7584
Typical Performance Curves (Continued)
f=675kHz, V =5.0V
IN
f=675kHz, V =3.3V
IN
1.5
1.0
1.5
1.0
0.5
0.5
0.0
0.0
-0.5
-1.0
-0.5
-1.0
-1.5
15V
12V
18V
9V
5V
12V
500
9V
600
18V
300
15V
400
(mA)
-1.5
0
100
200
700
0
100 200 300 400 500 600 700 800
(mA)
I
I
OUT
OUT
FIGURE 8. LOAD REGULATION vs I
FIGURE 7. LOAD REGULATION vs I
OUT
OUT
f=1MHz, V =3.3V
IN
f=1MHz, V =5.0V
IN
1.5
1.0
1.5
1.0
0.5
0.5
0.0
0.0
-0.5
-1.0
-1.5
-0.5
-1.0
-1.5
15V
18V
12V
9V
18V
300
12V
500
9V
5V
15V
400
(mA)
0
100
200
600
700
0
100 200 300 400 500 600 700 800
(mA)
I
I
OUT
OUT
FIGURE 9. LOAD REGULATION vs I
FIGURE 10. LOAD REGULATION vs I
OUT
OUT
6.5
20
19
V
= 15V
6
DDN
V
= 15V
DDP
V
= 12V
DDN
5.5
18
V
= 12V
DDP
5
4.5
4
17
16
15
3.5
14
0
10
20
30
40
50
60
70
80
0
10
20
30
40
50
60
70
80
I
(mA)
I
LOAD
(mA)
LOAD
FIGURE 11. V
vs I
FIGURE 12. V
vs I
ON
ON
OFF OFF
FN7317.2
6
February 4, 2005
EL7584
Typical Performance Curves (Continued)
SWITCHING PERIOD(µs)=0.0118 R
OSC
+0.378)
f(MHz)=1/(0.0118 R
OSC
+0.378)
6
5
4
3
2
1
0
1400
1200
1000
800
600
400
200
0
0
50 100 150 200 250 300 350 400 450
(kΩ)
0
50 100 150 200 250 300 350 400 450
(kΩ)
R
R
OSC
OSC
FIGURE 14. F vs R
OSC
FIGURE 13. F vs R
OSC
S
S
100K & 0.1µF DELAY NETWORK ON ENP, C =0.1µF
SS
100K & 0.1µF DELAY NETWORK ON ENP, C =0.1µF
SS
V
V
BOOST
BOOST
5V/DIV
5V/DIV
10V/DIV
V
V
V
V
ON
ON
10V/DIV
OFF
OFF
2V/DIV
2V/DIV
200ms/DIV
1ms/DIV
FIGURE 15. POWER-DOWN
FIGURE 16. POWER-UP
V
=3.3V, V
=11.3V, I =250mA
OUT
V
=3.3V, V
=11.3V, I =50mA
OUT
IN
OUT
IN
OUT
FIGURE 18. LX WAVEFORM - CONTINUOUS MODE
FIGURE 17. LX WAVEFORM - DISCONTINUOUS MODE
FN7317.2
February 4, 2005
7
EL7584
Typical Performance Curves (Continued)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
CONDUCTIVITY TEST BOARD
1.4
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.2
781mW
1.176W
1
0.8
0.6
0.4
0.2
0
0
25
50
75 85
100
125
0
25
50
75 85
100
125
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
FIGURE 19. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 20. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Functional Block Diagram
V
OUT
10µH
R
2
V
IN
R
13kΩ
110kΩ
1
49Ω
10µF
10µF
0.1µF
FBB
V
DDB
LX
MAX_DUTY
R
OSC
R
3
REFERENCE
GENERATOR
62kΩ
V
REF
PWM
PWM
COMPARATOR
V
0.22Ω
LOGIC
RAMP
EN
12µA
-
+
START-UP
OSCILLATOR
I
LOUT
7.2K
160mΩ
V
SSB
SS
PGND
0.1µF
FN7317.2
8
February 4, 2005
EL7584
Steady-State Operation
Applications Information
When the output reaches the preset voltage, the regulator
operates at steady state. Depending on the input/output
condition and component, the inductor operates at either
continuous-conduction mode or discontinuous-conduction
mode.
The EL7584 is high efficiency multiple output power solution
designed specifically for thin-film transistor (TFT) liquid
crystal display (LCD) applications. The device contains one
high current boost converter and two low power charge
pumps (V
and V
).
ON
OFF
In the continuous-conduction mode, the inductor current is a
triangular waveform and LX voltage a pulse waveform. In the
discontinuous-conduction mode, the inductor current is
completely ‘dried-out’ before the MOSFET is turned on
again. The input voltage source, the inductor, and the
MOSFET and output diode parasitic capacitors forms a
resonant circuit. Oscillation will occur in this period. This
oscillation is normal and will not affect the regulation.
The boost converter contains an integrated N-channel
MOSFET to minimize the number of external components.
The converter output voltage can be set from 5V to 18V with
external resistors. The V
and V charge pumps are
ON
OFF
independently regulated to positive and negative voltages
using external resistors. Output voltages as high as 40V can
be achieved with additional capacitors and diodes.
Boost Converter
At very low load, the MOSFET will skip pulse sometimes.
This is normal.
The boost converter operates in constant frequency pulse-
width-modulation (PWM) mode. Quiescent current for the
EL7584 is only 5mA when enabled, and since only the low
side MOSFET is used, switch drive current is minimized.
90% efficiency is achieved in most common application
operating conditions.
Current Limit
The MOSFET is current limited to <1.75Amps (nominal).
This restricts the maximum output current I
the following formula:
based on
OMAX
A functional block diagram with typical circuit configuration is
shown on previous page. Regulation is performed by the
PWM comparator which regulates the output voltage by
comparing a divided output voltage with an internal
reference voltage. The PWM comparator outputs its result to
the PWM logic. The PWM logic switches the MOSFET on
and off through the gate drive circuit. Its switching frequency
is external adjustable with a resistor from timing control pin
V
V
IN
∆L
---------
I
=
I
– ------
×
OMAX
LMT
2
O
where:
• ∆I is the inductor peak-to-peak current ripple and is
L
decided by:
V
L
D
IN
×
--------- ------
∆I
=
L
(R
) to ground. The boost converter has 200kHz to
F
S
OSC
1.2MHz operating frequency range.
• D is the MOSFET turn-on radio and is decided by:
Start-Up
After V
reaches a threshold of about 2V, the power
V
- V
IN
DDB
O
D = -----------------------
MOSFET is controlled by the start-up oscillator, which
generates fixed duty-ratio of 0.5 - 0.7 at a frequency of
several hundred kilohertz. This will boost the output voltage,
providing the initial output current load is not too great
(<250mA).
V
O
• F is the switching frequency.
S
When V
reaches about 3.7V, the PWM comparator
DDB
takes over the control. The duty ratio will be decided by the
multiple-input direct summing comparator, Max_Duty signal
(about 90% duty-ratio), and the Current Limit Comparator,
whichever is the smallest.
The soft-start is provided by the current limit comparator. As
the internal 12µA current source charges the external soft-
start capacitor, the peak MOSFET current is limited by the
voltage on the capacitor. This in turn controls the rising rate
of output voltage.
The regulator goes through the start-up sequence as well
after the EN signal is pulled to HI.
FN7317.2
9
February 4, 2005
EL7584
The following table gives typical values:
Schottky Diode
(Margins are considered 10%, 3%, 20%, 10%, and 15% on
Speed, forward voltage drop, and reverse current are the
three most critical specifications for selecting the Schottky
diode. The entire output current flows through the diode, so
the diode average current is the same as the average load
current and the peak current is the same as the inductor
peak current. When selecting the diode, one must consider
the forward voltage drop at the peak diode current. On the
Elantec demo board, MBRM120 is selected. Its forward
voltage drop is 450mV at 1A forward current.
V
, V , L, F , and I , respectively)
IN
O
S
LMT
TABLE 1. MAXIMUM CONTINUOUS OUTPUT CURRENT
V
(V)
V
(V)
L (µH)
10
F
(kHz)
I
(mA)
IN
3.3
O
S
OMAX
430
9
1000
3.3
3.3
5
12
15
9
10
1000
1000
1000
1000
1000
1000
320
250
650
470
370
830
10
10
Output Capacitor
5
12
15
18
10
The EL7584 is specially compensated to be stable with
capacitors which have a worst-case minimum value of 10µF
5
10
at the particular V
being set. Output ripple voltage
12
10
OUT
requirements also determine the minimum value and the
type of capacitors. Output ripple voltage consists of two
components - the voltage drop caused by the switching
current though the ESR of the output capacitor and the
charging and discharging of the output capacitor:
Component Considerations
Input Capacitor
It is recommended that C is larger than 10µF.
IN
Theoretically, the input capacitor has ripple current of ∆I .
L
I
V
- V
IN
OUT
OUT
Due to high-frequency noise in the circuit, the input current
ripple may exceed the theoretical value. Larger capacitor will
reduce the ripple further.
------------------------------
V
= I
× ESR + ------------------------------- ×
RIPPLE
LPK
C
× FS
V
OUT
OUT
For low ESR ceramic capacitors, the output ripple is
dominated by the charging/discharging of the output
capacitor.
Boost Inductor
The inductor has peak and average current decided by:
∆I
2
L
I
= I
+ --------
In addition to the voltage rating, the output capacitor should
also be able to handle the RMS current is given by:
LPK
LAVG
I
O
I
= -------------
LAVG
2
1 - D
∆I
1
L
------
I
=
(1 - D) × D + ------------------- ×
× I
LAVG
CORMS
2
12
The inductor should be chosen to be able to handle this
current. Furthermore, due to the fixed internal
compensation, it is recommended that maximum inductance
of 10µH and 15µH to be used in the 5V and 12V or higher
output voltage, respectively.
I
LAVG
Positive and Negative Charge Pump (V
and
ON
V
)
OFF
The EL7584 contains two independent charge pumps (see
charge pump block and connection diagram.) The negative
The output diode has average current of I , and peak current
O
the same as the inductor's peak current. Schottky diode is
recommended and it should be able to handle those currents.
charge pump inverts the V
supply voltage and provides
DDN
a regulated negative output voltage. The positive charge
pump doubles the V supply voltage and provides a
DDP
Feedback Resistor Network
regulated positive output voltage. The regulation of both the
negative and positive charge pumps is generated by the
internal comparator that senses the output voltage and
compares it with and internal reference. The switching
frequency of the charge pump is set to ½ the boost converter
switching frequency.
An external resistor divider is required to divide the output
voltage down to the nominal reference voltage. Current
drawn by the resistor network should be limited to maintain
the overall converter efficiency. The maximum value of the
resistor network is limited by the feedback input bias current
and the potential for noise being coupled into the feedback
pin. A resistor network in the order of 200kΩ is
The pumps use pulse width modulation to adjust the pump
period, depending on the load present. The pumps are short-
circuit protected to 180mA at 12V supply and can provide
15mA to 60mA for 6V to 12V supply.
recommended. The boost converter output voltage is
determined by the following relationship:
R
+ R
2
1
--------------------
V
=
× V
BOOST
FBB
R
1
where V
is 1.300V.
FBB
FN7317.2
10
February 4, 2005
EL7584
Single Stage Charge Pump
V
DDN
5V TO
17V
V
DDP
5V TO
17V
0.1µF
0.1µF
R
R
R
ONP
DRVN
ONP
DRVP
C
CPP
OSC
C
CPN
V
R
V
OFF
ONN
ONN
V
ON
C
C
OUT2
3.3µF
OUT1
V
SSP
SSN
R
2.2µF
12
R
21
FBP
FBN
+
-
-
+
+
-
V
R
FBP
11
R
IS 30 - 40Ω FOR V
6V TO 12V
ON
DD
R
22
V
REF
Positive Charge Pump Design Considerations
A single stage charge pump is shown above. The maximum
V
output voltage is determined by the following equation:
ON
1
S
1
-------------------------------------------
-----------------------------------------------
×
V
(max) ≤ 2 × V
- I
× 2 × (R
+ R
) - 2 × V
- I
×
- I
OUT
ON
DDCPP
OUT
ONN
ONP
DIODE
OUT
0.5 × F × C
0.5 × F × C
OUT1
CPP
S
where:
• R
and R resistance values depend on the V
ONP
ONN
voltage levels. For 12V supply, R
DDP
is typically 33Ω. For
ON
6V supply, R
ON
is typically 45Ω.
If additional stage is required, the LX switching signal is
recommended to drive the additional charge pump diodes.
The drive impedance at the LX switching is typically 150mΩ.
The figure below illustrates an implementation for two-stage
positive charge pump circuit.
FN7317.2
11
February 4, 2005
EL7584
Two-Stage Positive Charge Pump Circuit
V
DDP
V
BOOST
(5V-17V)
V
LX
R
ONP
C
CPP
C
DRNP
V
ON
C
CPP
C
R
V
OUT1
OUT1
ONN
SSP
R
R
12
11
FBP
-
+
+
-
1.265V
The maximum V
output voltage for N+1 stage charge pump is:
ON
1
S
-------------------------------------------
V
(max) ≤ 2 × V
- I
× 2 × (R
+ R
) - 2 × V
+ I
- I
×
- I
×
ON
DDP
OUT
ONN
ONP
DIODE
OUT
1
S
OUT
1
S
0.5 × F × C
CPP
1
-----------------------------------------------
-------------------------------------------
-----------------------------------------------
+ N × V (max) - N × 2 × V
×
+ I
×
LX
DIODE
OUT
OUT
0.5 × F × C
0.5 × F × C
0.5 × F × C
S
OUT1
CPP
OUT1
R
V
and R set the V
12
output voltage:
11
ON
R
+ R
11
12
--------------------------
= V
×
ON
FBP
R
11
where V
is 1.310V.
FBP
Negative Charge Pump Design Considerations
The criteria for the negative charge pump is similar to the
positive charge pump. For a single stage charge pump, the
maximum V
output voltage is:
OFF
1
S
1
--------------------------------------------
-----------------------------------------------
V
(max) ≥ I
× 2 × (R
+ R
) + 2 × V
- I
×
- I
×
- V
OFF
OUT
ONN
ONP
DIODE
OUT
OUT
DDN
0.5 × F × C
0.5 × F × C
OUT2
CPN
S
Similar to positive charge pump, if additional stage is
required, the LX switching signal is recommended to drive
the additional charge pump diodes. The figure on the next
page shows a two stage negative charge pump circuit.
FN7317.2
12
February 4, 2005
EL7584
Two-Stage Negative Charge Pump Circuit
V
DDN
5V-17V
V
LX
R
ONP
C
CPN
C
DRVN
V
OFF
C
CPN
C
R
OUT2
OUT2
ONN
V
SSN
R
21
22
FBN
+
-
R
V
REF
The maximum V
output voltage for N+1 stage charge pump is:
OFF
1
S
1
--------------------------------------------
-----------------------------------------------
V
(max) ≥ I
× 2 × (R
+ R
) + 2 × V
+ I
- I
×
- I
×
-
OFF
OUT
ONN
ONP
DIODE
OUT
1
OUT
1
0.5 × F × C
0.5 × F × C
CPN
S
OUT2
--------------------------------------------
-----------------------------------------------
V
- N × V (max) + N × 2 × V
×
+ I
×
DDN
LX
DIODE
OUT
OUT
0.5 × F × C
0.5 × F × C
S
CPN
S
OUT2
R
V
and R determine V
22
output voltage:
OFF
21
R
21
---------
= -V
×
OFF
REF
R
22
where V
is 1.310V.
REF
If V
exceeds 15V, V
must be protected from over-
DDC
The V
Buffer
BOOST
COM
voltage by including a zener diode between V
and
BOOST
The V
buffer is designed to control the voltage on the
COM
V
.
DDC
back plane of an LCD display. This plane is capacitively
coupled to the pixel drive voltage which alternately cycles
V
BOOST
positive and negative at the line rate for the display. Thus the
amplifier must be capable of sourcing and sinking capacitive
pulses of current, which can occasionally be quite large (a
few 100mA for typical applications).
0.1µF
R
R
32
31
INC
V
V
COM
DDC
+
-
V
COM
V
SSC
The use of the V
Buffer is illustrated in Figure 21. Here,
1µF
COM
CERAMIC
LOW ESR
a voltage, corresponding to the mid-DAC potential, is
generated by a resistive divider and buffered by the
amplifier. The amplifier's stability is designed to be
dominated by the load capacitance, thus for very short
duration pulses (< 1µs) the output capacitor supplies the
FIGURE 21. V
USED AS A VOLTAGE BUFFER
COM
As with any high performance buffer, there are several
design issues that must be considered when using the part.
These are summarized below.
current. For longer pulses the V
buffer supplies the
COM
current. By virtue of its high transconductance which
progressively increases as more current is drawn, it can
maintain regulation within 5mV as currents up to 50mA are
drawn, while consuming only 1.5mA of quiescent current.
Good Decoupling of Power Supplies
This is essential for this component and 1µF ceramic low
ESR decoupling capacitors are recommended. These
should be placed close to the pins.
Choice of Output Capacitor
A 1µF ceramic capacitor with low ESR (X5R or X7R type) is
recommended for this amplifier. This capacitor determines
the stability of the amplifier. Reducing it will make the
amplifier less stable, and should be avoided. With a 1µF
capacitor, the unity gain bandwidth of the amplifier is close to
FN7317.2
13
February 4, 2005
EL7584
500kHz when reasonable currents are being drawn. (For
lower load currents, the gain and hence bandwidth
progressively decreases.) This means the active
transconductance is:
and the current capability of these negative charge
pumps (which is rising as V
and hence V
DDN
BOOST
rises.)
2. When V
BOOST
reaches a voltage such that V(FBB)>
first reaches its required regulation
regulator is enabled and V rises
1.13V and V
OFF
2π × 1µF × 500kHz = 3.14S
voltage, the V
COM
COM
load capacitor, the load
at a rate determined by the V
COM
This high transconductance indicates why it is important to
have a low ESR capacitor.
on V
, and the current limit of the V
amplifier.
COM
COM
rises to within 100mV of V(INC), an internal
3. When V
COM
delay circuit triggers and, for V
= 12V, a default delay
DDP
If:
of approximately 3.5ms is introduced before the positive
charge pump is then enabled. This delay can be
• ESR * 3.14 > 1
increased externally by connecting a capacitor between
then the capacitor will not force the gain to roll off below
unity, and subsequent poles can affect stability. The
recommended capacitor has an ESR of 10mΩ, but to this
must be added the resistance of the board trace between the
DP and V
. A 1nF capacitor will typically increase the
SSP
delay before V
becomes enabled to 80ms.
ON
The enabled states of the on-chip functions become
independent of V , V , V , and V once each
BOOST OFF COM
ON
capacitor and the V
pin, where the sense connection is
COM
is triggered. The chip may be reset by forcing EN to logic 0
and allowing sufficient time for the various supplies to
discharge sufficiently before taking EN to 1 again.
made internally - therefore this should be kept short. Also
ground resistance between the capacitor and the base of R
must be kept to a minimum. These constraints should be
considered when laying out the PCB.
2
Over-Temperature Protection
An internal temperature sensor continuously monitors the
die temperature. In the event that die temperature exceeds
the thermal trip point, the device will shut down and disable
itself. The upper and lower trip points are typically set to
130°C and 90°C respectively.
If the capacitor is increased above 1µF, stability is generally
improved and short pulses of current will cause a smaller
“perturbation” on the V
voltage. The speed of response
COM
of the amplifier is however degraded as its bandwidth is
decreased. At capacitor values around 10µF, a subtle
interaction with internal DC gain boost circuitry will decrease
the phase margin and may give rise to some overshoot in
the response. The amplifier will remain stable, though.
PCB Layout Guidelines
Careful layout is critical in the successful operation of the
application. The following layout guidelines are
recommended to achieve optimum performance.
Response to High Current Spikes
The V
amplifier's output current is limited to 180mA.
COM
1. V
REF
and V bypass capacitors should be placed next
DDB
This limit level, which is roughly the same for sourcing and
sinking, is included to maintain reliable operation of the part.
It does not necessarily prevent a large temperature rise if the
current is maintained. (In this case the whole chip may be
shut down by the thermal trip to protect functionality.) If the
display occasionally demands current pulses higher than
this limit, the reservoir capacitor will provide the excess and
the amplifier will top the reservoir capacitor back up once the
pulse has stopped. This will happen on the µs time scale in
practical systems and for pulses 2 or 3 times the current
to the pins.
2. Place the boost converter diode and inductor close to the
LX pins.
3. Place the boost converter output capacitor close to the
PGND pins.
4. Locate feedback dividers close to their respected
feedback pins to avoid switching noise coupling into the
high impedance node.
5. Place the charge pump feedback resistor network after
the diode and output capacitor node to avoid switching
noise.
limit, the V
voltage will have settled again before the
COM
next line is processed.
6. All low-side feedback resistors should be connected
directly to V
. V
should be connected to the power
Power-Up Sequencing
With the components shown in the application diagram the
on-chip power-up sequencing operates as follows.
SSB SSB
ground at one point only.
A demo board is available to illustrate the proper layout
implementation.
When the EN pin is taken to logic 1, the following sequence
is followed by on-chip functions:
1. The boost circuit and negative charge pumps are
enabled. V
rises at a rate set by the boost load
BOOST
capacitor, the external load, and the boost’s current limit
(controlled by the SS pin input.) Similarly, V
voltage determined by the load capacitor, the V
falls in
OFF
load,
OFF
FN7317.2
February 4, 2005
14
EL7584
Typical Application Circuit
C
7
1
SS
VSSB 24
R
2
0.1µF
R
3
110kΩ
2
3
4
5
6
7
8
9
FBB
EN
ROSC 23
VREF 22
PGND 21
PGND 20
VSSP 19
DRVP 18
VDDP 17
FBP 16
R
13kΩ
61.9kΩ
1
C
8
R
4
1nF
VDDB
LX
C
49.9Ω
6
0.1µF
+
+
C
5
22µF
V
BOOST
*D
1
(12V@
LX
350mA)
L1
C
0.1µF
12
VIN
VSSN
DRVN
VDDN
C
1
10µF
**D
V
10µH
11
ON
18V
C
22
GND
C
C
R
11
0.1µF
13
12
51kΩ
0.1µF
2.2µF
C
21
0.1µF
V
R
OFF
-6V
11
3.9kΩ
R
C
26
154kΩ 3.3µF
21
10 FBN
11 DP
VSSC 15
VCOM 14
VDDC 13
C
31
1µF
V
COM
**D
21
***C
1nF
20
12 INC
C
32
0.1µF
V
COM
REFERENCE
C
33
R
22
33.2kΩ
* MBRM120LT3
** BAT54S
*** C is optional if extended V
delay is required
20
ON
FN7317.2
February 4, 2005
15
EL7584
Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at
<http://www.intersil.com/design/packages/index.asp>
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7317.2
16
February 4, 2005
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