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HA-4900 [INTERSIL]

Precision Quad Comparators; 精密四路比较器
HA-4900
型号： HA-4900
厂家： Intersil    Intersil
描述：

Precision Quad Comparators
精密四路比较器

比较器
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中文：  中文翻译
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HA-4900, HA-4902, HA-4905  
Data Sheet  
September 1998  
File Number 2855.3  
Precision Quad Comparators  
Features  
• Fast Response Time . . . . . . . . . . . . . . . . . . . . . . . . 130ns  
• Low Offset Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 2.0mV  
• Low Offset Current . . . . . . . . . . . . . . . . . . . . . . . . . . .10nA  
• Single or Dual Voltage Supply Operation  
The HA-4900 series are monolithic, quad, precision  
comparators offering fast response time, low offset voltage,  
low offset current and virtually no channel-to-channel  
crosstalk for applications requiring accurate, high speed,  
signal level detection. These comparators can sense signals  
at ground level while being operated from either a single +5V  
supply (digital systems) or from dual supplies (analog  
networks) up to ±15V. The HA-4900 series contains a unique  
current driven output stage which can be connected to logic  
• Selectable Output Logic Levels  
• Active Pull-Up/Pull-Down Output Circuit. No External  
Resistors Required  
system supplies (V  
+ and V  
-) to make the output  
LOGIC  
LOGIC  
Applications  
levels directly compatible (no external components needed)  
with any standard logic or special system logic levels. In  
combination analog/digital systems, the design employed in  
the HA-4900 series input and output stages prevents  
troublesome ground coupling of signals between analog and  
digital portions of the system.  
• Threshold Detector  
• Zero Crossing Detector  
• Window Detector  
• Analog Interfaces for Microprocessors  
• High Stability Oscillators  
• Logic System Interfaces  
These comparators’ combination of features make them  
ideal components for signal detection and processing in data  
acquisition systems, test equipment and  
microprocessor/analog signal interface networks.  
Ordering Information  
For military grade product, refer to the HA-4902/883 data  
sheet.  
PART  
TEMP RANGE  
o
NUMBER  
( C)  
PACKAGE  
PKG. NO.  
Pinout  
HA1-4900-2  
HA1-4902-2  
HA1-4905-5  
HA3-4905-5  
HA9P4905-5  
-55 to 125  
-55 to 125  
0 to 75  
16 Ld CERDIP F16.3  
16 Ld CERDIP F16.3  
16 Ld CERDIP F16.3  
HA-4900, HA-4902 (CERDIP)  
HA-4905 (PDIP, CERDIP, SOIC)  
TOP VIEW  
0 to 75  
16 Ld PDIP  
16 Ld SOIC  
E16.3  
M16.3  
V +  
L
1
2
3
4
5
6
7
8
16 OUT 4  
15 -IN 4  
14 +IN 4  
13 V+  
0 to 75  
OUT 1  
-IN 1  
+IN 1  
V-  
-
+
4
3
-
+
1
2
12 +IN 3  
11 -IN 3  
10 OUT 3  
+
-
+IN 2  
-IN 2  
OUT 2  
+
-
9
V -  
L
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999  
1
HA-4900, HA-4902, HA-4905  
Absolute Maximum Ratings  
Thermal Information  
o
o
Supply Voltage (Between V+ and V- Terminals) . . . . . . . . . . . . 33V  
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V  
Thermal Resistance (Typical, Note 3)  
CERDIP Package. . . . . . . . . . . . . . . . .  
PDIP Package . . . . . . . . . . . . . . . . . . .  
SOIC Package . . . . . . . . . . . . . . . . . . .  
θ
( C/W)  
θ
( C/W)  
JA  
JC  
85  
90  
100  
25  
N/A  
N/A  
Voltage Between V  
+ and V  
-. . . . . . . . . . . . . . . . . . .18V  
LOGIC  
LOGIC  
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA  
Power Dissipation (Notes 1, 2)  
o
Maximum Junction Temperature (Ceramic Package) . . . . . . .175 C  
Maximum Junction Temperature (Plastic Package). . . . . . . . .150 C  
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C  
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C  
o
o
o
Operating Conditions  
o
Temperature Range  
HA-4900-2, HA-4902-2. . . . . . . . . . . . . . . . . . . . . -55 C to 125 C  
HA-4905-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 75 C  
(SOIC - Lead Tips Only)  
o
o
o
o
Die Characteristics  
Back Side Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-  
Number of Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137  
Die Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 mils x 105 mils  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the  
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTES:  
o
1. Maximum power dissipation, including output load, must be designed to maintain the junction temperature below 175 C for ceramic packages,  
o
and below 150 C for plastic packages.  
2. Total Power Dissipation (T.P.D.) is the sum of individual dissipation contributions of V+, V- and V  
shown in curves of Power Dissipation  
LOGIC  
vs Supply Voltages (see Performance Curves). The calculated T.P.D. is then located on the graph of Maximum Allowable Package Dissipation  
vs Ambient Temperature to determine ambient temperature operating limits imposed by the calculated T.P.D. (See Performance Curves). For  
instance, the combination of +15V, -15V, +5V, 0V (V+, V-, V  
0V gives a T.P.D. of 450mW.  
+, V  
LOGIC  
-) gives a T.P.D. of 350mW, the combination +15V, -15V, +15V,  
LOGIC  
3. θ is measured with the component mounted on an evaluation PC board in free air.  
JA  
Electrical Specifications  
V
= 15V, V  
+ = 5V, V - = GND  
LOGIC LOGIC  
SUPPLY  
HA-4900-2  
-55 C to 125 C  
HA-4902-2  
-55 C to 125 C  
HA-4905-5  
0 C to 75 C  
o
o
o
o
o
o
TEMP  
o
PARAMETER  
INPUT CHARACTERISTICS  
Offset Voltage (Note 4)  
( C)  
MIN  
TYP  
MAX  
MIN  
TYP  
MAX  
MIN  
TYP  
MAX  
UNITS  
25  
Full  
25  
-
-
-
-
-
-
-
2
-
3
4
-
-
-
-
-
-
-
2
-
5
8
-
-
-
-
-
-
-
4
7.5  
10  
mV  
mV  
nA  
nA  
nA  
nA  
mV  
-
25  
-
Offset Current  
10  
-
25  
35  
75  
150  
10  
-
35  
45  
150  
200  
50  
Full  
25  
70  
Bias Current (Note 5)  
Input Sensitivity (Note 6)  
50  
-
50  
-
100  
-
150  
300  
Full  
25  
-
V
+
-
V
+
-
V
+
IO  
IO  
IO  
0.5  
0.3  
0.5  
Full  
Full  
25  
-
V-  
-
-
-
V
0.4  
+
-
V-  
-
-
-
V
0.6  
+
-
V-  
-
-
-
V
0.7  
+
mV  
V
IO  
IO  
IO  
Common Mode Range  
(V+) -  
2.4  
(V+) -  
2.6  
(V+) -  
2.4  
Differential Input Resistance  
TRANSFER CHARACTERISTICS  
Large Signal Voltage Gain  
250  
-
250  
-
250  
-
MΩ  
25  
25  
-
-
400  
130  
-
-
-
400  
130  
-
-
-
400  
130  
-
kV/V  
ns  
Response Time (t (0))  
PD  
200  
200  
200  
(Note 7)  
Response Time (t (1))  
PD  
25  
-
180  
215  
-
180  
215  
-
180  
215  
ns  
(Note 7)  
2
HA-4900, HA-4902, HA-4905  
Electrical Specifications  
V
= 15V, V  
+ = 5V, V  
LOGIC LOGIC  
- = GND (Continued)  
SUPPLY  
HA-4900-2  
-55 C to 125 C  
HA-4902-2  
-55 C to 125 C  
HA-4905-5  
0 C to 75 C  
o
o
o
o
o
o
TEMP  
o
PARAMETER  
( C)  
MIN  
TYP  
MAX  
MIN  
TYP  
MAX  
MIN  
TYP  
MAX  
UNITS  
OUTPUT CHARACTERISTICS  
Output Voltage Level  
Logic “Low State” (V  
(Note 8)  
)
Full  
Full  
-
0.2  
4.2  
0.4  
-
-
0.2  
4.2  
0.4  
-
-
0.2  
4.2  
0.4  
-
V
V
OL  
Logic “High State” (V  
(Note 8)  
)
3.5  
3.5  
3.5  
OH  
Output Current  
I
Full  
Full  
3.0  
3.0  
-
-
-
-
3.0  
3.0  
-
-
-
-
3.0  
3.0  
-
-
-
-
mA  
mA  
SINK  
I
SOURCE  
POWER SUPPLY CHARACTERISTICS  
Supply Current, I  
Supply Current, I  
Supply Current, I  
(+)  
25  
25  
25  
-
-
-
6.5  
4
20  
8
-
-
-
6.5  
4
20  
8
-
-
-
7
5
20  
8
mA  
mA  
mA  
PS  
PS  
PS  
(-)  
(Logic)  
3.5  
4
3.5  
4
3.5  
4
Supply Voltage Range  
V
+ (Note 2)  
- (Note 2)  
Full  
Full  
0
-
-
+15.0  
0
0
-
-
+15.0  
0
0
-
-
+15.0  
0
V
V
LOGIC  
LOGIC  
V
-15.0  
-15.0  
-15.0  
NOTES:  
4. Minimum differential input voltage required to ensure a defined output state.  
5. Input bias currents are essentially constant with differential input voltages up to ±9V. With differential input voltages from ±9V to ±15V, bias cur-  
rent on the more negative input can rise to approximately 500µA. This will also cause higher supply currents.  
6. V  
= 0V. Input sensitivity is the worst case minimum differential input voltage required to guarantee a given output logic state. This parameter  
CM  
includes the effects of offset voltage and voltage gain.  
7. For t (1); 100mV input step, -10mV overdrive. For t (0); -100mV input step, 10mV overdrive. Frequency ≈ 100Hz; Duty Cycle ≈ 50%; Invert-  
PD  
PD  
ing input driven. See Figure 1 for Test Circuit. All unused inverting inputs tied to +5V.  
8. For V  
OH  
and V : I  
OL SINK  
= I  
= 3.0mA. For other values of V  
; V  
(Min) = V + -1.5V.  
LOGIC  
SOURCE  
LOGIC OH  
Test Circuit and Waveform  
+15V  
+5V  
t
(0)  
t
(1)  
PD  
PD  
OVERDRIVE  
-
V
DUT  
+
OUT  
V
= 0V  
TH  
100mV  
100mV  
V
= 0V  
INPUT  
TH  
OVERDRIVE  
-15V  
OUTPUT  
1.5V  
1.5V  
t
(1)  
PD  
t
(0)  
PD  
t = 0  
t = 0  
FIGURE 1.  
3
HA-4900, HA-4902, HA-4905  
Schematic Diagram  
V+  
R
500Ω  
R
13kΩ  
R
1kΩ  
R
1kΩ  
R
5
1
2
3
4
360Ω  
R
R
4kΩ  
R
18  
664Ω  
PR  
200kΩ  
9
10  
4kΩ  
1
Q
Q
13  
Q
Q
15  
12  
14  
Q
Q
16  
11  
Q
Q
1
Q
2
26  
D
11A  
R
2.5kΩ  
R
2.5kΩ  
6
7
R
11  
8kΩ  
Q
Q
23  
7
3
V
+
Q
Q
25  
LOGIC  
24  
Q
4C  
D
R
8kΩ  
45  
D
D
12  
4B  
Q
29A  
4A  
Q
Q
D
Q
28  
38  
Q
37  
Q
32  
Q
Q
R
100Ω  
Q
19  
20  
22  
36  
Q
29  
Q
Q
OUT  
N6  
4
5
39  
D
D
M
29B  
35  
R
16  
540Ω  
Q
Q
21  
18  
+IN  
-IN  
R
100Ω  
M
23  
N5  
V
R
Q
24  
14kΩ  
30  
Q
Q
22  
BIAS 1  
17  
Q
Q
34  
33  
BIAS 2 BIAS 3 BIAS 4  
Q
31  
D
Q
9B  
9A  
R
15  
8kΩ  
Q
Q
Q
9D  
9C  
9A  
M
R
Q
N2  
17  
19kΩ  
10  
R
-
14  
5kΩ  
LOGIC  
R
R
R
R
R
20D  
1kΩ  
20C  
1kΩ  
20B  
1kΩ  
20A  
1kΩ  
21  
1kΩ  
M
M
N1  
N4  
M
N3  
V-  
ONE FOURTH ONLY  
Applying the HA-4900 Series Comparators  
Supply Connections  
Power Supply Decoupling  
This device is exceptionally versatile in working with most  
available power supplies. The voltage applied to the V+ and V-  
terminals determines the allowable input signal range; while the  
Decouple all power supply lines with 0.01µF ceramic capacitors  
to ground line located near the package to reduce coupling  
between channels or from external sources.  
voltage applied to the V + and V - determines the output  
swing. In systems where dual analog supplies are available,  
these would be connected to V+ and V-, while the logic supply  
L
L
Response Time  
Fast rise time (<200ns) input pulses of several volts  
amplitude may result in delay times somewhat longer than  
those illustrated for 100mV steps. Operating speed is  
optimized by limiting the maximum differential input voltage  
applied, with resistor-diode clamping networks.  
and return would be connected to V  
+ and V -. The  
LOGIC  
LOGIC  
analog and logic supply commons can be connected together  
at one point in the system, since the comparator is immune to  
noise on the logic supply ground. A negative output swing may  
be obtained by connecting V + to ground and V - to a negative  
L
L
Typical Applications  
supply. Bipolar output swings (15V , Max) may be obtained  
P-P  
using dual supplies. In systems where only a single logic supply  
Data Acquisition System  
is available (+5V to 15V), V+ and V  
together to the positive supply while V- and V  
LOGIC  
+ may be connected  
- are  
LOGIC  
In this circuit the HA-4900 series is used in conjunction with  
a D to A converter to form a simple, versatile, multi-channel  
analog input for a data acquisition system. In operation the  
processor first sends an address to the D to A, then the  
processor reads the digital word generated by the  
grounded. If an input signal could swing negative with respect  
the V- terminal, a resistor should be connected in series with  
the input to limit input current to < 5mA since the C-B junction of  
the input transistor would be forward biased.  
comparator outputs. To perform a simple comparison, the  
processor sets the D to A to a given reference level, then  
examines one or more comparator outputs to determine if  
their inputs are above or below the reference. A window  
comparison consists of two such cycles with 2 reference  
levels set by the D to A. One way to digitize the inputs would  
be for the processor to increment the D to A in steps. The D  
to A address, as each comparator switches, is the digitized  
level of the input. While stairstepping the D to A is slower  
than successive approximation, all channels are digitized  
during one staircase ramp.  
Unused Inputs  
Inputs of unused comparator sections should be tied to a  
differential voltage source to prevent output “chatter.”  
Crosstalk  
Simultaneous high frequency operation of all other channels  
in the package will not affect the output logic state of a given  
channel, provided that its differential input voltage is  
sufficient to define a given logic state (∆V ≥ ±V ). Low  
level or high impedance input lines should be shielded from  
other signal sources to reduce crosstalk and interference.  
IN  
OS  
4
HA-4900, HA-4902, HA-4905  
Window Detector  
The high switching speed, low offset current and low offset  
voltage of the HA-4900 series makes this window detector  
circuit extremely well suited to applications requiring fast,  
accurate, decision-making. The circuit above is ideal for  
industrial process system feedback controllers or “out-of-  
limit” alarm indicators.  
D/A  
MEMORY  
+15V  
V +  
L
MICRO-  
PROCESSOR  
+
INPUT  
COMPARATORS  
HIGH  
HIGH REF  
-
+5.0V  
ANALOG INPUT MODULE  
PROCESSOR  
Logic Level Translators  
IN  
-15V  
WINDOW  
The HA-4900 series comparators can be used as versatile  
logic interface devices as shown in the circuits above.  
Negative logic devices may also be interfaced with  
appropriate supply connections. If separate supplies are  
1/4 HD-74C02  
LOW  
+
LOW REF  
used for V- and V  
-, these logic level translators will  
tolerate several volts of ground line differential noise.  
LOGIC  
-
V+  
+5.0V  
1/2 HA-4900  
+5V TO +15V  
V +  
L
+5.0V  
Oscillator/Clock Generator  
4.7kΩ  
10kΩ  
This self-starting fixed frequency oscillator circuit gives  
excellent frequency stability. R and C comprise the  
+
+
1/4  
HA-4900  
-
1/4  
HA-4900  
-
1
1
frequency determining network while R provides the  
2
regenerative feedback. Diode D enhances the stability by  
1
compensating for the difference between V  
and  
OH  
10kΩ  
1N914s  
V
. In applications where a precision clock generator  
SUPPLY  
up to 100kHz is required, such as in automatic test  
equipment, C may be replaced by a crystal.  
1
+
+
1/4  
HA-4900  
-
1/4  
HA-4900  
-
R
2
V+  
150kΩ  
TTL TO CMOS  
CMOS TO TTL  
1N914  
D
1
V+  
RS-232 To CMOS Line Receiver  
150kΩ  
This RS-232 type line receiver to drive CMOS logic uses a  
Schmitt trigger feedback network to give about 1V input  
hysteresis for added noise immunity. A possible problem in  
an interface which connects two equipments, each plugged  
into a different AC receptacle, is that the power line voltage  
may appear at the receiver input when the interface  
+
1/4  
HA-4900  
-
150kΩ  
1
-----------------------  
2.1R C  
f ≈  
1
1
connection is made or broken. The two diodes and a 3W  
input resistor will protect the inputs under these conditions.  
R
1
50kΩ  
C
1
+10V  
4.7kΩ  
3W  
-
Schmitt Trigger (Zero Crossing Detector With Hysteresis)  
This circuit has a 100mV hysteresis which can be used in  
applications where very fast transition times are required at  
the output even though the signal input is very slow. The  
hysteresis loop also reduces false triggering due to noise on  
the input. The waveforms below show the trip points  
developed by the hysteresis loop.  
1/4  
HA-4900  
+
1kΩ  
56kΩ  
51kΩ  
1kΩ  
1N4001s  
5
HA-4900, HA-4902, HA-4905  
+15V  
+5V  
V
OH  
-
1/4  
HA-4900  
V
≈ 4.2V  
OH  
+
R
2kΩ  
V
+
2
TRIP  
0V  
-15V  
R
3
13kΩ  
V
-
R
1
100Ω  
TRIP  
-15V  
INPUT TO OUTPUT WAVEFORM SHOWING HYSTERESIS TRIP  
POINTS  
o
Typical Performance Curves T = 25 C, V = ±15V, V  
+ = 5V, V - = 0V, Unless Otherwise Specified  
LOGIC  
A
S
LOGIC  
100  
80  
60  
40  
20  
0
15  
10  
5
0
-55  
-25  
0
25  
50  
o
75  
100  
125  
-55  
-25  
0
25  
50  
o
75  
100  
125  
TEMPERATURE ( C)  
TEMPERATURE ( C)  
FIGURE 2. INPUT BIAS CURRENT vs TEMPERATURE  
FIGURE 3. INPUT OFFSET CURRENT vs TEMPERATURE  
80  
60  
40  
20  
0
-15 -12  
-9  
-6  
-3  
0
+3  
+6  
+9  
+12 +15  
COMMON MODE INPUT VOLTAGE  
FIGURE 4. INPUT BIAS CURRENT vs COMMON MODE INPUT VOLTAGE (V  
= 0V)  
DIFF  
6
HA-4900, HA-4902, HA-4905  
o
Typical Performance Curves T = 25 C, V = ±15V, V  
+ = 5V, V - = 0V, Unless Otherwise Specified (Continued)  
LOGIC  
A
S
LOGIC  
7
6
5
4
3
2
1
0
12  
10  
8
V
V
V
= ±15V  
I
L, V  
= H  
= H  
S
PS  
OUT  
+ = 5V  
- = GND  
LOGIC  
LOGIC  
I
I
+, V  
= L  
OUT  
PS  
+, V = H  
OUT  
I
+, V  
PS  
PS  
OUT  
I
I
+, V  
L, V  
= L  
= L  
6
PS  
OUT  
I
I
-, V  
-, V  
= L  
PS  
OUT  
4
= H  
75  
PS  
OUT  
PS  
OUT  
I
L, V  
= L  
= H  
PS  
OUT  
2
V+ = 5V, V- = GND  
V
V
+ = 5V  
- = GND  
LOGIC  
LOGIC  
I
L, V  
PS  
OUT  
0
-50  
-25  
0
25  
50  
o
100  
125  
-50  
-25  
0
25  
50  
o
75  
100  
125  
TEMPERATURE ( C)  
TEMPERATURE ( C)  
FIGURE 5. SUPPLY CURRENT vs TEMPERATURE (FOR ±15V  
FIGURE 6. SUPPLY CURRENT vs TEMPERATURE (FOR SINGLE  
+5V OPERATION)  
SUPPLIES AND +5V LOGIC SUPPLY)  
5
5
OVERDRIVE = 20mV  
OVERDRIVE = 5mV  
OVERDRIVE = 2mV  
4
3
2
1
0
0
4
OVERDRIVE = 20mV  
3
OVERDRIVE = 5mV  
2
1
OVERDRIVE = 2mV  
0
+100mV  
-100mV  
0
0
100  
200  
TIME (ns)  
300  
400  
0
100  
200  
TIME (ns)  
300  
400  
FIGURE 7. RESPONSE TIME FOR VARIOUS INPUT OVERDRIVES  
250  
2.0  
1.75  
1.50  
1.25  
1.0  
CERDIP  
200  
150  
100  
50  
V+  
PDIP  
V-  
0.75  
0.50  
0.25  
0
SOIC  
V
+
LOGIC  
0
0
2
4
6
8
10  
12  
14  
0
25  
50  
75  
100  
125  
o
SUPPLY VOLTAGE (V)  
TEMPERATURE ( C)  
FIGURE 8. MAXIMUM PACKAGE DISSIPATION vs AMBIENT  
TEMPERATURE  
FIGURE 9. POWER DISSIPATION vs SUPPLY VOLTAGE (NO  
LOAD CONDITION)  
7
HA-4900, HA-4902, HA-4905  
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.  
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-  
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and  
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result  
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see web site www.intersil.com  
Sales Office Headquarters  
NORTH AMERICA  
EUROPE  
ASIA  
Intersil Corporation  
Intersil SA  
Mercure Center  
100, Rue de la Fusee  
1130 Brussels, Belgium  
TEL: (32) 2.724.2111  
FAX: (32) 2.724.22.05  
Intersil (Taiwan) Ltd.  
7F-6, No. 101 Fu Hsing North Road  
Taipei, Taiwan  
Republic of China  
TEL: (886) 2 2716 9310  
FAX: (886) 2 2715 3029  
P. O. Box 883, Mail Stop 53-204  
Melbourne, FL 32902  
TEL: (321) 724-7000  
FAX: (321) 724-7240  
8

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