HA3-5320-5 [INTERSIL]
1 Microsecond Precision Sample and Hold Amplifier; 1微秒级精度采样保持放大器
| 型号： | HA3-5320-5 |
| 厂家： | 
Intersil |
| 描述： | 1 Microsecond Precision Sample and Hold Amplifier |
| 文件： | 总7页 (文件大小：88K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HA-5320
Data Sheet
April 1999
File Number 2857.4
1 Microsecond Precision Sample and
Hold Amplifier
Features
6
• Gain, DC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 x 10 V/V
The HA-5320 was designed for use in precision, high speed
data acquisition systems.
• Acquisition Time. . . . . . . . . . . . . . . . . . . . . 1.0µs (0.01%)
o
• Droop Rate. . . . . . . . . . . . . . . . . . . . . . 0.08µV/µs (25 C)
The circuit consists of an input transconductance amplifier
capable of providing large amounts of charging current, a low
leakage analog switch, and an output integrating amplifier. The
analog switch sees virtual ground as its load; therefore, charge
injection on the hold capacitor is constant over the entire
input/output voltage range. The pedestal voltage resulting from
this charge injection can be adjusted to zero by use of the offset
adjust inputs. The device includes a hold capacitor. However, if
improved droop rate is required at the expense of acquisition
time, additional hold capacitance may be added externally.
17µV/µs (Full Temperature)
• Aperture Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns
• Hold Step Error (See Glossary) . . . . . . . . . . . . . . . . . 5mV
• Internal Hold Capacitor
• Fully Differential Input
• TTL Compatible
Applications
This monolithic device is manufactured using the Intersil
Dielectric Isolation Process, minimizing stray capacitance
and eliminating SCRs. This allows higher speed and latch-
free operation. For further information, please see
Application Note AN538.
• Precision Data Acquisition Systems
• Digital to Analog Converter Deglitcher
• Auto Zero Circuits
• Peak Detector
Pinouts
Ordering Information
HA-5320
(PDIP, CERDIP)
TOP VIEW
TEMP.
PKG.
NO.
o
PART NUMBER RANGE ( C)
PACKAGE
14 Ld CERDIP
14 Ld CERDIP
14 Ld PDIP
HA1-5320-2
HA1-5320-5
HA3-5320-5
HA9P5320-5
HA9P5320-9
-55 to 25
0 to 75
F14.3
-INPUT
+INPUT
1
2
3
4
5
6
7
14 S/H CONTROL
13 SUPPLY GND
12 NC
F14.3
E14.3
M16.3
M16.3
0 to 75
OFFSET ADJUST
OFFSET ADJUST
V-
0 to 75
16 Ld SOIC
11
C
EXT
-40 to 85
16 Ld SOIC
10 NC
Functional Diagram
SIG. GND
9
8
V+
INTEGRATOR
BANDWIDTH
OFFSET
ADJUST
OUTPUT
V+
9
3
4
HA-5320
(SOIC)
TOP VIEW
100pF
HA-5320
1
2
-INPUT
+INPUT
-
7
OUTPUT
-INPUT
+INPUT
1
16 S/H CONTROL
15 SUPPLY GND
14 NC
+
2
3
4
5
6
7
8
OFFSET ADJUST
OFFSET ADJUST
V-
C
13
EXT
S/H
CONTROL
14
12 NC
11 V+
SIG. GND
OUTPUT
INTEGRATOR
INTEGRATOR
BANDWIDTH
10
9
5
6
8
13
BANDWIDTH
SUPPLY
GND
V-
SIG.
GND
NC
NC
11
C
EXT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1
HA-5320
Absolute Maximum Ratings
Thermal Information
o
o
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24V
Digital Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8V, -15V
Output Current, Continuous (Note 1). . . . . . . . . . . . . . . . . . . ±20mA
Thermal Resistance (Typical, Note 3)
θ
( C/W)
θ
( C/W)
JA
JC
CERDIP Package. . . . . . . . . . . . . . . . .
PDIP Package . . . . . . . . . . . . . . . . . . .
SOIC Package . . . . . . . . . . . . . . . . . . .
70
75
90
18
N/A
N/A
o
Maximum Junction Temperature (Ceramic Package) . . . . . . . . .175 C
Maximum Junction Temperature (Plastic Package) . . . . . . . .150 C
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C
o
Operating Conditions
o
o
Temperature Range
HA-5320-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
HA-5320-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 75 C
HA-5320-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C
o
o
o
(SOIC - Lead Tips Only)
o
o
o
o
Supply Voltage Range (Typical, Note 2) . . . . . . . . . ±13.5V to ±20V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Internal Power Dissipation may limit Output Current below 20mA.
2. Specification based on a one time characterization. This parameter is not guaranteed.
3. θ is measured with the component mounted on an evaluation PC board in free air.
JA
Electrical Specifications
V
= ±5.0V; C = Internal; Digital Input: V = +0.8V (Sample), V = +2.0V (Hold),
IL IH
SUPPLY
H
Unity Gain Configuration (Output tied to -Input), Unless Otherwise Specified
HA-5320-2/-9
HA-5320-5
TYP
TEST
CONDITIONS
TEMP.
( C)
o
PARAMETER
INPUT CHARACTERISTICS
Input Voltage Range
Input Resistance
MIN
TYP
MAX
MIN
MAX
UNITS
Full
25
±10
-
5
-
-
±10
-
5
-
-
V
MΩ
pF
mV
mV
nA
nA
nA
nA
V
1
1
Input Capacitance
25
-
-
5
-
-
5
Offset Voltage
25
-
0.2
-
-
-
0.5
-
-
Full
25
-
2.0
200
200
100
100
-
-
1.5
300
300
300
300
-
Bias Current
-
70
-
-
100
-
Full
25
-
-
-
-
Offset Current
30
-
30
-
Full
Full
25
-
-
Common Mode Range
CMRR
±10
80
-
-
±10
72
-
-
V
= ±5V
90
5
-
90
5
-
dB
CM
o
Offset Voltage Temperature Coefficient
TRANSFER CHARACTERISTICS
Gain
Full
15
20
µV/ C
6
6
5
6
DC, (Note 12)
25
25
25
10
2 x 10
-
-
-
3 x 10
2 x 10
-
-
-
V/V
MHz
MHz
Gain Bandwidth Product
(A = +1, Note 5)
V
C
C
= 100pF
-
-
2.0
-
-
2.0
H
H
= 1000pF
0.18
0.18
OUTPUT CHARACTERISTICS
Output Voltage
Full
25
25
25
25
25
±10
-
-
±10
-
-
V
mA
kHz
Ω
Output Current
±10
-
-
-
±10
-
-
-
Full Power Bandwidth
Output Resistance
Note 4
-
-
-
-
600
1.0
125
125
-
-
-
-
600
1.0
125
125
Hold Mode
Sample
Hold
-
-
Total Output Noise (DC to 10MHz)
200
200
200
200
µV
µV
RMS
RMS
2
HA-5320
Electrical Specifications
V
= ±5.0V; C = Internal; Digital Input: V = +0.8V (Sample), V = +2.0V (Hold),
SUPPLY
H
IL
IH
Unity Gain Configuration (Output tied to -Input), Unless Otherwise Specified (Continued)
HA-5320-2/-9
TYP
HA-5320-5
TYP
TEST
CONDITIONS
TEMP.
( C)
o
PARAMETER
TRANSIENT RESPONSE
Rise Time
MIN
MAX
MIN
MAX
UNITS
Note 5
25
25
25
-
-
-
100
15
-
-
-
-
-
-
100
15
-
-
-
ns
%
Overshoot
Note 5
Note 6
Slew Rate
45
45
V/µs
DIGITAL INPUT CHARACTERISTICS
Input Voltage
V
V
V
Full
Full
25
2.0
-
-
-
-
-
-
2.0
-
-
-
-
-
-
V
IH
IL
IL
-
-
-
-
0.8
4
-
-
-
-
0.8
4
V
Input Current
= 0V
µA
µA
µA
Full
Full
10
0.1
10
0.1
V
= +5V
IH
SAMPLE AND HOLD CHARACTERISTICS
Acquisition Time (Note 7)
To 0.1%
To 0.01%
25
25
-
0.8
1.0
25
1.2
1.5
-
-
0.8
1.0
25
1.2
1.5
-
µs
µs
-
-
Aperture Time (Note 8)
Effective Aperture Delay Time
Aperture Uncertainty
Droop Rate
25
-
-
ns
25
-50
-25
0.3
0.08
17
0
-50
-25
0.3
0.08
1.2
8
0
ns
25
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
25
0.5
100
50
10
1.1
11
350
-
0.5
100
50
10
1.1
11
350
-
µV/µs
µV/µs
pA
Full
25
Drift Current
Note 9
8
Full
25
1.7
0.5
5
0.12
0.5
5
nA
Charge Transfer
Note 9
pC
Hold Step Error
Note 9
25
mV
ns
Hold Mode Settling Time
Hold Mode Feedthrough
POWER SUPPLY CHARACTERISTICS
Positive Supply Current
Negative Supply Current
Supply Voltage Range
Power Supply Rejection
To 0.01%
Full
Full
165
2
165
2
10V
P-P
, 100kHz
mV
Note 10
25
25
-
-
11
-11
−
13
-13
±20
-
-
-
11
13
-13
±20
-
mA
mA
V
Note 10
-11
Note 2
±13.5
80
±13.5
80
-
-
-
V+, Note 11
V-, Note 11
Full
Full
-
dB
dB
65
-
-
65
-
NOTES:
4. V = 20V
; R = 2kΩ; C = 50pF; unattenuated output.
P-P
O
L
L
5. V = 200mV
; R = 2kΩ; C = 50pF.
P-P
O
L
L
6. V = 20V Step; R = 2kΩ; C = 50pF.
O
L
L
7. V = 10V Step; R = 2kΩ; C = 50pF.
O
L
L
8. Derived from computer simulation only; not tested.
9. V = 0V, V = +3.5V, t < 20ns (V to V ).
IN IH IL IH
R
10. Specified for a zero differential input voltage between +IN and -IN. Supply current will increase with differential input (as may occur in the Hold
mode) to approximately ±46mA at 20V.
11. Based on a 1V delta in each supply, i.e. 15V ±0.5V
.
DC
12. R = 1kΩ, C = 30pF.
L
L
3
HA-5320
Test Circuits and Waveforms
1
2
7
-INPUT
+INPUT
V
OUTPUT
O
8
NC
NC
S/H
14
11
S/H CONTROL
CONTROL
INPUT
HA-5320
(C = 100pF)
H
FIGURE 1. CHARGE TRANSFER AND DRIFT CURRENT
HOLD (+3.5V)
SAMPLE (0V)
HOLD (+3.5V)
S/H CONTROL
SAMPLE (0V)
S/H CONTROL
V
O
∆V
V
O
O
∆t
V
P
NOTES:
NOTES:
13. Observe the “hold step” voltage V .
15. Observe the voltage “droop”, ∆V /∆t.
O
P
16. Measure the slope of the output during hold, ∆V /∆t, and
O
14. Compute charge transfer: Q = V C .
P
H
compute drift current: I = C ∆V /∆t.
D
H
O
FIGURE 2. CHARGE TRANSFER TEST
FIGURE 3. DRIFT CURRENT TEST
V+
V-
HA-5320
ANALOG
MUX OR
SWITCH
NOTE:
V
9
5
IN
Feedthrough in
1
2
-IN
V
OUT
V
10V
100kHz
SINE WAVE
OUT
P-P
7
--------------
+IN
dB = 20log
where:
OUT
V
IN
S/H CONTROL
SUPPLY
GND
13
14
A
IN
REF
COM COMP.
INT.
V
= V , Hold Mode, V = V
P-P IN
.
P-P
OUT
C
EXT
S/H CONTROL
INPUT
11
NC
6
8
TO
TO
SIGNAL
GND
NC
SUPPLY
COMMON
FIGURE 4. HOLD MODE FEEDTHROUGH ATTENUATION
Hold Capacitor
Application Information
The HA-5320 includes a 100pF MOS hold capacitor,
sufficient for most high speed applications (the Electrical
Specifications section is based on this internal capacitor).
The HA-5320 has the uncommitted differential inputs of an
op amp, allowing the Sample and Hold function to be
combined with many conventional op amp circuits. See the
Intersil Application Note AN517 for a collection of circuit
ideas.
Additional capacitance may be added between pins 7 and
11. This external hold capacitance will reduce droop rate at
the expense of acquisition time, and provide other trade-offs
as shown in the Performance Curves.
Layout
A printed circuit board with ground plane is recommended
for best performance. Bypass capacitors (0.01µF to 0.1µF,
ceramic) should be provided from each power supply
terminal to the Supply Ground terminal on pin 13.
If an external hold capacitor C
EXT
bandwidth capacitor of value 0.1C
is used, then a noise
should be connected
EXT
from pin 8 to ground. Exact value and type are not critical.
The ideal ground connections are pin 6 (SIG. Ground)
directly to the system Signal Ground, and pin 13 (Supply
Ground) directly to the system Supply Common.
The hold capacitor C should have high insulation
resistance and low dielectric absorption, to minimize droop
EXT
errors. Polystyrene dielectric is a good choice for operating
o
temperatures up to 85 C. Teflon® and glass dielectrics offer
o
good performance to 125 C and above.
®Teflon is a registered Trademark of Dupont Corporation.
4
HA-5320
The hold capacitor terminal (pin 11) remains at virtual
ground potential. Any PC connection to this terminal should
be kept short and “guarded” by the ground plane, since
nearby signal lines or power supply voltages will introduce
errors due to drift current.
Aperture Time
The time required for the sample-and-hold switch to open,
independent of delays through the switch driver and input
amplifier circuitry. The switch opening time is the interval
between the conditions of 10% open and 90% open.
Typical Application
Hold Step Error
Figure 5 shows the HA-5320 connected as a unity gain
noninverting amplifier - its most widely used configuration.
As an input device for a fast successive - approximation A/D
converter, it offers very high throughput rate for a monolithic
IC sample/hold amplifier. Also, the HA-5320’s hold step error
is adjustable to zero using the Offset Adjust potentiometer,
to deliver a 12-bit accurate output from the converter.
Hold Step Error is the output error due to Charge Transfer (see
above). It may be calculated from the specified parameter,
Charge Transfer, using the following relationship:
Charge Transfer (pC)
Hold Step (V) = -----------------------------------------------------------
Hold Capacitance (pF)
See Performance Curves.
The application may call for an external hold capacitor C
shown. As mentioned earlier, 0.1C
EXT
pin 8 to reduce output noise in the Hold mode.
as
is then recommended at
EXT
Effective Aperture Delay Time (EADT)
The difference between the digital delay time from the Hold
command to the opening of the S/H switch, and the
propagation time from the analog input to the switch.
The HA-5320 output circuit does not include short circuit
protection, and consequently its output impedance remains
low at high frequencies. Thus, the step changes in load
current which occur during an A/D conversion are absorbed
at the S/H output with minimum voltage error. A momentary
short circuit to ground is permissible, but the output is not
designed to tolerate a short of indefinite duration.
EADT may be positive, negative or zero. If zero, the S/H
amplifier will output a voltage equal to V at the instant the
IN
Hold command was received. For negative EADT, the output in
Hold (exclusive of pedestal and droop errors) will correspond to
a value of V that occurred before the Hold command.
IN
Aperture Uncertainty
Glossary of Terms
The range of variation in Effective Aperture Delay Time.
Aperture Uncertainty (also called Aperture Delay Uncertainty,
Aperture Time Jitter, etc.) sets a limit on the accuracy with
which a waveform can be reconstructed from sample data.
Acquisition Time
The time required following a “sample” command, for the
output to reach its final value within ±0.1% or ±0.01%. This is
the minimum sample time required to obtain a given accuracy,
and includes switch delay time, slewing time and settling time.
Drift Current
The net leakage current from the hold capacitor during the
hold mode. Drift current can be calculated from the droop
rate using the formula:
Charge Transfer
The small charge transferred to the holding capacitor from
the inter-electrode capacitance of the switch when the unit is
switched to the HOLD mode. Charge transfer is directly
proportional to sample-to-hold offset pedestal error, where:
∆V
∆t
-------
(V/s)
I
(pA) = C (pF) ×
D
H
Charge Transfer (pC) = C (pF) x Hold Step Error (V)
H
10kΩ
-15V +15V
OFFSET
ADJUST
±15mV
HI-574A
3
4
5
9
11
C
EXT
1
2
100pF
+
-
-
13
7
V
IN
INPUT
DIGITAL
OUTPUT
+
14
S/H CONTROL
CONVERT
HA-5320
H
S
5
9
13
6
8
R/C
0.1C
EXT
ANALOG
COMMON
NOTE: Pin Numbers Refer to
DIP Package Only.
SYSTEM POWER
GROUND
SYSTEM SIGNAL
GROUND
FIGURE 5. TYPICAL HA-5320 CONNECTIONS; NONINVERTING UNITY GAIN MODE
5
HA-5320
Typical Performance Curves
C
= 100pF, INTERNAL
H
10
ACQUISITION TIME FOR
5
10V STEP TO +0.01% (µs)
1000
100
10
1
VOLTAGE DROOP DURING
HOLD MODE, (mV/100ms)
1.0
0.5
0.1
SAMPLE-TO-HOLD OFFSET
(HOLD STEP) ERROR, (mV)
0.05
0.01
0
100
1000
10K
100K
-25
0
25
50
75
100
125
o
C
VALUE (pF)
TEMPERATURE ( C)
H
FIGURE 6. TYPICAL SAMPLE AND HOLD PERFORMANCE
AS A FUNCTION OF HOLD CAPACITOR
FIGURE 7. DRIFT CURRENT vs TEMPERATURE
120
100
80
0
45
PHASE
90
60
(C = 100pF)
H
GAIN
GAIN
40
135
180
(C = 1100pF)
H
20
0
0
10
100
1K
10K
100K
1M
10M
FREQUENCY (Hz)
FIGURE 8. OPEN LOOP GAIN AND PHASE RESPONSE
C
= 100pF
H
o
75 C
HOLD STEP VOLTAGE (mV)
o
T
= 25 C
A
5.0
0.5
C
C
C
= 100pF
= 1000pF
= 0.01µF
H
o
H
H
25 C
0.05
-10
-8
-6
-4
-2
2
4
6
8
10
2
3
4
5
DC INPUT (V)
LOGIC LEVEL HIGH (V)
FIGURE 9A. HOLD STEP vs INPUT VOLTAGE
FIGURE 9B. HOLD STEP vs LOGIC (V ) VOLTAGE
IH
FIGURE 9. TYPICAL SAMPLE-TO-HOLD OFFSET (HOLD STEP) ERROR
6
HA-5320
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
Type: Nitride (Si N ) over Silox (SiO , 5% Phos)
92 mils x 152 mils x 19 mils
3
4
2
Silox Thickness: 12kÅ ±2kÅ
METALLIZATION:
Nitride Thickness: 3.5kÅ ±1.5kÅ
Type: Al, 1% Cu
Thickness: 16kÅ ±2kÅ
TRANSISTOR COUNT:
184
SUBSTRATE POTENTIAL:
V-
Metallization Mask Layout
HA-5320
C
SUPPLY GND
(13)
V+
(9)
EXT
(11)
S/H CTRL (14)
-INPUT (1)
(8) INT BW
(7) OUTPUT
(6) SIG GND
+INPUT (2)
(3)
ADJ
(4)
ADJ
(5)
V-
V
V
IO
IO
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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7
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