HA5023IBZ [INTERSIL]
Dual 125MHz Video Current Feedback Amplifier; 双125MHz的视频电流反馈放大器
| 型号： | HA5023IBZ |
| 厂家： | 
Intersil |
| 描述： | Dual 125MHz Video Current Feedback Amplifier |
| 文件： | 总16页 (文件大小：361K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HA5023
®
Data Sheet
June 2, 2006
FN3393.8
Dual 125MHz Video Current
Feedback Amplifier
Features
• Wide Unity Gain Bandwidth . . . . . . . . . . . . . . . . . 125MHz
• Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475V/µs
• Input Offset Voltage . . . . . . . . . . . . . . . . . . . . . . . . 800µV
• Differential Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.03%
• Differential Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . 0.03°
• Supply Current (per Amplifier) . . . . . . . . . . . . . . . . 7.5mA
• ESD Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4000V
• Guaranteed Specifications at ±5V Supplies
The HA5023 is a wide bandwidth high slew rate dual
amplifier optimized for video applications and gains between
1 and 10. It is a current feedback amplifier and thus yields
less bandwidth degradation at high closed loop gains than
voltage feedback amplifiers.
The low differential gain and phase, 0.1dB gain flatness, and
ability to drive two back terminated 75Ω cables, make this
amplifier ideal for demanding video applications.
The current feedback design allows the user to take
advantage of the amplifier’s bandwidth dependency on the
• Pb-Free Plus Anneal Available (RoHS Compliant)
feedback resistor. By reducing R , the bandwidth can be
F
increased to compensate for decreases at higher closed
loop gains or heavy output loads.
Applications
• Video Gain Block
The performance of the HA5023 is very similar to the
popular Intersil HA-5020.
• Video Distribution Amplifier/RGB Amplifier
• Flash A/D Driver
Ordering Information
• Current to Voltage Converter
• Medical Imaging
PART
PART
TEMP.
PKG.
NUMBER
MARKING RANGE (°C) PACKAGE DWG. #
• Radar and Imaging Systems
• Video Switching and Routing
HA5023IP
HA5023IP
-40 to 85 8 Ld PDIP
E8.3
E8.3
HA5023IPZ
(Note)
HA5023IPZ
-40 to 85 8 Ld PDIP*
(Pb-free)
Pinout
HA5023IB
5023I
-40 to 85 8 Ld SOIC
M8.15
M8.15
HA5023
(PDIP, SOIC)
TOP VIEW
HA5023IB96 5023I
-40 to 85 8 Ld SOIC
Tape and Reel
HA5023IBZ
(Note)
5023IBZ
-40 to 85 8 Ld SOIC
(Pb-free)
M8.15
M8.15
OUT1
-IN1
+IN1
V-
1
2
3
4
8
7
6
5
V+
OUT2
-IN2
+IN2
+
-
HA5023IBZ96 5023IBZ
(Note)
-40 to 85 8 Ld SOIC
TapeandReel
(Pb-free)
+
-
HA5023EVAL High Speed Op Amp DIP Evaluation Board
*Pb-free PDIPs can be used for through hole wave solder processing
only. They are not intended for use in Reflow solder processing
applications.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 1998, 2005-2006. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
HA5023
Absolute Maximum Ratings
Thermal Information
Voltage Between V+ and V- Terminals. . . . . . . . . . . . . . . . . . . . .36V
DC Input Voltage (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . ±V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10V
Output Current (Note 4) . . . . . . . . . . . . . . . . .Short Circuit Protected
ESD Rating (Note 3)
Thermal Resistance (Typical, Note 2)
θJA (°C/W)
SUPPLY
PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
130
160
Maximum Junction Temperature (Note 1) . . . . . . . . . . . . . . . . . 175°C
Maximum Junction Temperature (Plastic Package, Note 1) . . 150°C
Maximum Storage Temperature Range. . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
(SOIC - Lead Tips Only)
*Pb-free PDIPs can be used for through hole wave solder process-
ing only. They are not intended for use in Reflow solder processing
applications.
Human Body Model (Per MIL-STD-883 Method 3015.7). . . 2000V
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C
Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . ±4.5V to ±15V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Maximum power dissipation, including output load, must be designed to maintain junction temperature below 175°C for die, and below 150°C
for plastic packages. See Application Information section for safe operating area information.
2. θ is measured with the component mounted on an evaluation PC board in free air.
JA
3. The non-inverting input of unused amplifiers must be connected to GND.
4. Output is protected for short circuits to ground. Brief short circuits to ground will not degrade reliability, however, continuous (100% duty cycle)
output current should not exceed 15mA for maximum reliability.
Electrical Specifications
V
= ±5V, R = 1kΩ, A = +1, R = 400Ω, C ≤ 10pF, Unless Otherwise Specified
SUPPLY
F
V
L
L
(NOTE 9)
TEST
LEVEL
TEMP.
(°C)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
INPUT CHARACTERISTICS
Input Offset Voltage (V
)
A
A
A
B
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
25
Full
Full
Full
25
-
0.8
-
3
5
mV
mV
mV
µV/°C
dB
IO
-
Delta V Between Channels
IO
-
1.2
5
-
3.5
-
Average Input Offset Voltage Drift
-
V
V
Common Mode Rejection Ratio
Note 5
53
-
IO
IO
Full
25
50
-
-
dB
Power Supply Rejection Ratio
±3.5V ≤ V ≤ ±6.5V
60
-
-
dB
S
Full
Full
25
55
-
-
dB
Input Common Mode Range
Note 5
Note 5
±2.5
-
-
V
Non-Inverting Input (+IN) Current
-
-
-
-
-
-
-
-
-
-
3
-
8
µA
Full
25
20
0.15
0.5
0.1
0.3
12
30
15
30
µA
+IN Common Mode Rejection
1
-
µA/V
µA/V
µA/V
µA/V
µA
(+I
=
)
BCMR
Full
25
-
+R
IN
+IN Power Supply Rejection
Inverting Input (-IN) Current
±3.5V ≤ V ≤ ±6.5V
-
S
Full
25, 85
-40
-
4
10
6
10
µA
Delta -IN BIAS Current Between Channels
25, 85
-40
µA
µA
FN3393.8
June 2, 2006
2
HA5023
Electrical Specifications
V
= ±5V, R = 1kΩ, A = +1, R = 400Ω, C ≤ 10pF, Unless Otherwise Specified (Continued)
SUPPLY
F
V
L
L
(NOTE 9)
TEST
LEVEL
TEMP.
(°C)
PARAMETER
TEST CONDITIONS
Note 5
MIN
TYP
MAX
0.4
1.0
0.2
0.5
-
UNITS
µA/V
-IN Common Mode Rejection
A
A
A
A
B
B
B
25
Full
25
-
-
-
-
-
-
-
-
-
µA/V
-IN Power Supply Rejection
±3.5V ≤ V ≤ ±6.5V
-
µA/V
S
Full
25
-
µA/V
Input Noise Voltage
f = 1kHz
f = 1kHz
f = 1kHz
4.5
2.5
25.0
nV/√Hz
pA/√Hz
pA/√Hz
+Input Noise Current
-Input Noise Current
25
-
25
-
TRANSFER CHARACTERISTICS
Transimpedence
Note 11
A
A
A
A
A
A
25
Full
25
1.0
0.85
70
-
-
-
-
-
-
-
-
-
-
-
-
MΩ
MΩ
dB
Open Loop DC Voltage Gain
Open Loop DC Voltage Gain
R
R
= 400Ω, V
= 100Ω, V
= ±2.5V
= ±2.5V
L
L
OUT
OUT
Full
25
65
dB
50
dB
Full
45
dB
OUTPUT CHARACTERISTICS
Output Voltage Swing
R
R
= 150Ω
= 150Ω
A
A
B
A
25
±2.5
±2.5
±16.6
±40
±3.0
±3.0
±20.0
±60
-
-
-
-
V
V
L
Full
Full
Full
Output Current
mA
mA
L
Output Current, Short Circuit
V
= ±2.5V, V
= 0V
OUT
IN
POWER SUPPLY CHARACTERISTICS
Supply Voltage Range
A
A
25
5
-
-
15
10
V
Quiescent Supply Current
Full
7.5
mA/Op Amp
AC CHARACTERISTICS (A = +1)
V
Slew Rate
Note 6
Note 7
Note 8
Note 8
Note 8
B
B
B
B
B
B
B
B
B
25
25
25
25
25
25
25
25
25
275
350
28
6
-
-
-
-
-
-
-
-
-
V/µs
MHz
ns
Full Power Bandwidth
Rise Time
22
-
Fall Time
-
6
ns
Propagation Delay
Overshoot
-
6
ns
-
4.5
125
50
75
%
-3dB Bandwidth
Settling Time to 1%
Settling Time to 0.25%
V
= 100mV
-
MHz
ns
OUT
2V Output Step
2V Output Step
-
-
ns
FN3393.8
June 2, 2006
3
HA5023
Electrical Specifications
V
= ±5V, R = 1kΩ, A = +1, R = 400Ω, C ≤ 10pF, Unless Otherwise Specified (Continued)
SUPPLY
F
V
L
L
(NOTE 9)
TEST
LEVEL
TEMP.
(°C)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
AC CHARACTERISTICS (A = +2, R = 681Ω)
V
F
Slew Rate
Note 6
B
B
B
B
B
B
B
B
B
B
B
25
25
25
25
25
25
25
25
25
25
25
-
-
-
-
-
-
-
-
-
-
-
475
26
-
-
-
-
-
-
-
-
-
-
-
V/µs
MHz
ns
Full Power Bandwidth
Rise Time
Note 7
Note 8
Note 8
Note 8
6
Fall Time
6
ns
Propagation Delay
Overshoot
6
ns
12
%
-3dB Bandwidth
Settling Time to 1%
Settling Time to 0.25%
Gain Flatness
V
= 100mV
95
MHz
ns
OUT
2V Output Step
2V Output Step
5MHz
50
100
0.02
0.07
ns
dB
dB
20MHz
AC CHARACTERISTICS (A = +10, R = 383Ω)
V
F
Slew Rate
Note 6
Note 7
Note 8
Note 8
Note 8
B
B
B
B
B
B
B
B
B
25
25
25
25
25
25
25
25
25
350
475
38
8
-
-
-
-
-
-
-
-
-
V/µs
MHz
ns
Full Power Bandwidth
Rise Time
28
-
Fall Time
-
9
ns
Propagation Delay
Overshoot
-
9
ns
-
1.8
65
75
130
%
-3dB Bandwidth
Settling Time to 1%
Settling Time to 0.1%
V
= 100mV
-
MHz
ns
OUT
2V Output Step
2V Output Step
-
-
ns
VIDEO CHARACTERISTICS
Differential Gain (Note 10)
Differential Phase (Note 10)
NOTES:
R
R
= 150Ω
= 150Ω
B
B
25
25
-
-
0.03
0.03
-
-
%
°
L
L
5. V
6. V
= ±2.5V. At -40°C Product is tested at V
= ±2.25V because Short Test Duration does not allow self heating.
CM
CM
switches from -2V to +2V, or from +2V to -2V. Specification is from the 25% to 75% points.
OUT
Slew Rate
7.
----------------------------
.
= 2V
FPBW =
; V
PEAK
2πV
PEAK
8. R = 100Ω, V
= 1V. Measured from 10% to 90% points for rise/fall times; from 50% points of input and output for propagation delay.
OUT
L
9. A. Production Tested; B. Typical or Guaranteed Limit based on characterization; C. Design Typical for information only.
10. Measured with a VM700A video tester using an NTC-7 composite VITS.
11. V
OUT
= ±2.5V. At -40°C Product is tested at V
= ±2.25V because Short Test Duration does not allow self heating.
OUT
FN3393.8
June 2, 2006
4
HA5023
Test Circuits and Waveforms
+
-
DUT
50Ω
HP4195
NETWORK
ANALYZER
50Ω
FIGURE 1. TEST CIRCUIT FOR TRANSIMPEDANCE MEASUREMENTS
(NOTE 12)
100Ω
(NOTE 12)
100Ω
DUT
V
+
-
IN
DUT
V
OUT
V
+
-
IN
V
OUT
50Ω
R
L
400Ω
50Ω
R
L
R , 681Ω
F
R
I
681Ω
100Ω
R , 1kΩ
F
FIGURE 2. SMALL SIGNAL PULSE RESPONSE CIRCUIT
FIGURE 3. LARGE SIGNAL PULSE RESPONSE CIRCUIT
NOTE:
12. A series input resistor of ≥100Ω is recommended to limit input currents in case input signals are present before the HA5023 is powered up.
Vertical Scale: V = 100mV/Div., V
IN
Horizontal Scale: 20ns/Div.
= 100mV/Div.
Vertical Scale: V = 1V/Div., V
IN
Horizontal Scale: 50ns/Div.
= 1V/Div.
OUT
OUT
FIGURE 4. SMALL SIGNAL RESPONSE
FIGURE 5. LARGE SIGNAL RESPONSE
FN3393.8
June 2, 2006
5
Schematic Diagram (One Amplifier of Two)
V+
R
800
R
5
2.5K
2
R
10
820
R
R
R
15
400
19
400
Q
Q
P9
29
9.5
P8
R
27
200
Q
Q
P19
Q
P11
P14
R
5
Q
31
Q
P1
P5
R
1K
11
R
R
18
17
280 280
R
24
140
Q
Q
P16
N5
Q
P20
Q
P10
R
20
140
Q
Q
P15
N12
P12
C
1
Q
N8
1.4pF
Q
P2
Q
R
20
28
Q
R
60K
P6
1
Q
Q
-IN
N6
R
280
12
Q
P17
Q
N1
Q
Q
N13
P13
+IN
P4
Q
N17
R
25
R
6K
3
C
2
1.4pF
20
Q
N15
Q
N2
R
21
140
Q
Q
R
N10
N21
Q
R
R
280
R
P7
D
1
14
280
22
25
140
Q
N4
32
5
Q
N18
R
1K
Q
Q
N19
Q
13
N14
N3
Q
Q
N7
N16
R
7
30
R
R
16
400
23
400
R
26
200
OUT
R
800
R
R
9
820
4
33
800
Q
Q
N11
N9
V-
HA5023
traces connected to -IN, and that connections to -IN be kept
as short as possible to minimize the capacitance from this
node to ground.
Application Information
Optimum Feedback Resistor
The plots of inverting and non-inverting frequency response,
see Figure 8 and Figure 9 in the typical performance section,
illustrate the performance of the HA5023 in various closed
loop gain configurations. Although the bandwidth
dependency on closed loop gain isn’t as severe as that of a
voltage feedback amplifier, there can be an appreciable
decrease in bandwidth at higher gains. This decrease may
be minimized by taking advantage of the current feedback
Driving Capacitive Loads
Capacitive loads will degrade the amplifier’s phase margin
resulting in frequency response peaking and possible
oscillations. In most cases the oscillation can be avoided by
placing an isolation resistor (R) in series with the output as
shown in Figure 6.
amplifier’s unique relationship between bandwidth and R .
All current feedback amplifiers require a feedback resistor,
100Ω
F
R
V
+
-
IN
V
OUT
even for unity gain applications, and R , in conjunction with
F
R
T
C
the internal compensation capacitor, sets the dominant pole
of the frequency response. Thus, the amplifier’s bandwidth is
L
R
F
R
I
inversely proportional to R . The HA5023 design is
F
optimized for a 1000Ω R at a gain of +1. Decreasing R in
a unity gain application decreases stability, resulting in
excessive peaking and overshoot. At higher gains the
F
F
FIGURE 6. PLACEMENT OF THE OUTPUT ISOLATION
RESISTOR, R
amplifier is more stable, so R can be decreased in a trade-
off of stability for bandwidth.
F
The selection criteria for the isolation resistor is highly
dependent on the load, but 27Ω has been determined to be
a good starting value.
The table below lists recommended R values for various
F
gains, and the expected bandwidth.
Power Dissipation Considerations
Due to the high supply current inherent in dual amplifiers, care
must be taken to insure that the maximum junction
GAIN
(A
BANDWIDTH
(MHz)
)
R (Ω)
F
CL
-1
+1
750
1000
681
100
125
95
temperature (T , see Absolute Maximum Ratings) is not
exceeded. Figure 7 shows the maximum ambient
temperature versus supply voltage for the available package
J
+2
styles (Plastic DIP, SOIC). At ±5V quiescent operation both
DC
+5
1000
383
52
package styles may be operated over the full industrial range
of -40°C to 85°C. It is recommended that thermal calculations,
which take into account output power, be performed by the
designer.
+10
-10
65
750
22
PC Board Layout
140
130
The frequency response of this amplifier depends greatly on
the amount of care taken in designing the PC board. The use
of low inductance components such as chip resistors and
chip capacitors is strongly recommended. If leaded
components are used the leads must be kept short
especially for the power supply decoupling components and
those components connected to the inverting input.
120
110
100
90
PDIP
SOIC
80
70
Attention must be given to decoupling the power supplies. A
large value (10µF) tantalum or electrolytic capacitor in
parallel with a small value (0.1µF) chip capacitor works well
in most cases.
60
50
5
7
9
11
13
15
SUPPLY VOLTAGE (±V)
A ground plane is strongly recommended to control noise.
Care must also be taken to minimize the capacitance to
ground seen by the amplifier’s inverting input (-IN). The
larger this capacitance, the worse the gain peaking, resulting
in pulse overshoot and possible instability. It is
FIGURE 7. MAXIMUM OPERATING AMBIENT TEMPERATURE
vs SUPPLY VOLTAGE
recommended that the ground plane be removed under
FN3393.8
June 2, 2006
7
HA5023
Typical Performance Curves V
= ±5V, A = +1, R = 1kΩ, R = 400Ω, T = 25°C,
SUPPLY
V
F
L
A
Unless Otherwise Specified
5
5
4
V
C
= 0.2V
P-P
V
= 0.2V
P-P
OUT
= 10pF
OUT
A
= +1, R = 1kΩ
4
3
V
F
C
= 10pF
L
L
A
= 2, R = 681Ω
R = 750Ω
F
3
2
V
F
A
= -1
= -2
V
2
A
= 5, R = 1kΩ
F
V
1
1
A
V
0
0
-1
-1
-2
-3
-4
-2
-3
-4
A
= -10
V
A
= 10, R = 383Ω
F
V
A
= -5
V
-5
-5
2
10
FREQUENCY (MHz)
100
200
2
10
FREQUENCY (MHz)
100
200
FIGURE 8. NON-INVERTING FREQENCY RESPONSE
FIGURE 9. INVERTING FREQUENCY RESPONSE
140
130
120
V
= 0.2V
P-P
180
135
90
OUT
= 10pF
0
-45
-90
A
= +1, R = 1kΩ
F
V
C
L
A
= +1
V
A
= -1, R = 750Ω
F
V
45
0
-135
-100
-225
A
= +10, R = 383Ω
F
V
10
-3dB BANDWIDTH
-45
-90
-270
A
= -10, R = 750Ω
F
5
0
V
-135
-180
-315
-360
V
= 0.2V
P-P
OUT
= 10pF
GAIN PEAKING
700 900
C
L
500
1100
1300
1500
2
10
FREQUENCY (MHz)
100
200
FEEDBACK RESISTOR (Ω)
FIGURE 11. BANDWIDTH AND GAIN PEAKING vs FEEDBACK
RESISTANCE
FIGURE 10. PHASE RESPONSE AS A FUNCTION OF
FREQUENCY
100
130
V
C
= 0.2V
P-P
OUT
= 10pF
L
A
= +2
V
120
95
90
-3dB BANDWIDTH
110
100
6
-3dB BANDWIDTH
10
4
2
5
0
V
C
= 0.2V
P-P
90
80
OUT
= 10pF
GAIN PEAKING
L
A
= +1
V
GAIN PEAKING
0
0
200
400
600
800
1000
350
500
650
800
950
1100
LOAD RESISTOR (Ω)
FEEDBACK RESISTOR (Ω)
FIGURE 13. BANDWIDTH AND GAIN PEAKING vs LOAD
RESISTANCE
FIGURE 12. BANDWIDTH AND GAIN PEAKING vs FEEDBACK
RESISTANCE
FN3393.8
June 2, 2006
8
HA5023
Typical Performance Curves V
= ±5V, A = +1, R = 1kΩ, R = 400Ω, T = 25°C,
SUPPLY
V
F
L
A
Unless Otherwise Specified (Continued)
80
60
16
V
C
= 0.1V
P-P
V
= 0.2V
P-P
OUT
= 10pF
OUT
= 10pF
C
A
L
L
= +10
V
= ±5V, A = +2
V
V
SUPPLY
12
6
40
20
0
V
= ±15V, A = +2
V
SUPPLY
V
= ±5V, A = +1
SUPPLY
V
V
= ±15V, A = +1
V
SUPPLY
0
0
200
400
600
800
1000
200
350
500
650
800
950
LOAD RESISTANCE (Ω)
FEEDBACK RESISTOR (Ω)
FIGURE 15. SMALL SIGNAL OVERSHOOT vs LOAD
RESISTANCE
FIGURE 14. BANDWIDTH vs FEEDBACK RESISTANCE
0.08
0.10
FREQUENCY = 3.58MHz
FREQUENCY = 3.58MHz
0.08
0.06
0.04
R
= 75Ω
L
0.06
0.04
R
= 150Ω
L
R
= 150Ω
L
R
= 75Ω
L
0.02
0.00
0.02
0.00
R
= 1kΩ
L
R
= 1kΩ
L
3
5
7
9
11
13
15
3
5
7
9
11
13
15
SUPPLY VOLTAGE (±V)
SUPPLY VOLTAGE (±V)
FIGURE 17. DIFFERENTIAL PHASE vs SUPPLY VOLTAGE
FIGURE 16. DIFFERENTIAL GAIN vs SUPPLY VOLTAGE
-40
A
= +1
V
V
C
= 2.0V
OUT
= 30pF
P-P
0
-10
-20
-30
L
-50
-60
HD
2
3RD ORDER IMD
-40
-50
CMRR
-70
-80
-90
HD2
HD
3
-60
-70
-80
NEGATIVE PSRR
POSITIVE PSRR
0.1
HD
3
0.3
1
10
0.001
0.01
1
10
30
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 18. DISTORTION vs FREQUENCY
FIGURE 19. REJECTION RATIOS vs FREQUENCY
FN3393.8
June 2, 2006
9
HA5023
Typical Performance Curves V
= ±5V, A = +1, R = 1kΩ, R = 400Ω, T = 25°C,
SUPPLY
V
F
L
A
Unless Otherwise Specified (Continued)
12
8.0
R
V
= 100Ω
L
R
= 100Ω
LOAD
= 1.0V
V
= 1.0V
P-P
OUT
P-P
OUT
A
= +1
V
10
8
7.5
A
= +10, R = 383Ω
F
V
7.0
6.5
6.0
A
= +2, R = 681Ω
F
V
6
A
= +1, R = 1kΩ
F
V
4
-50
-25
0
25
50
75
100
125
3
5
7
9
11
13
15
SUPPLY VOLTAGE (±V)
TEMPERATURE (C)
FIGURE 20. PROPAGATION DELAY vs TEMPERATURE
FIGURE 21. PROPAGATION DELAY vs SUPPLY VOLTAGE
500
0.8
V
= 2V
P-P
OUT
V
C
= 0.2V
P-P
OUT
= 10pF
0.6
0.4
0.2
0
450
400
350
300
250
L
+ SLEW RATE
A
= +2, R = 681Ω
F
V
- SLEW RATE
-0.2
-0.4
-0.6
A
= +5, R = 1kΩ
V
F
A
= +1, R = 1kΩ
F
200
150
100
V
-0.8
-1.0
-1.2
A
= +10, R = 383Ω
V
F
-50
-25
0
25
50
75
100
125
5
10
15
20
25
30
TEMPERATURE (°C)
FREQUENCY (MHz)
FIGURE 22. FIGURE 22. SLEW RATE vs TEMPERATURE
0.8
FIGURE 23. NON-INVERTING GAIN FLATNESS vs FREQUENCY
100
80
1000
800
V
= 0.2V
OUT
P-P
0.6
0.4
A
= +10, R = 383Ω
F
V
C
R
= 10pF
= 750Ω
L
F
-INPUT NOISE CURRENT
0.2
0
A
= -1
600
V
60
-0.2
-0.4
-0.6
-0.8
-1.0
-1.2
+INPUT NOISE CURRENT
400
40
A
= -5
INPUT NOISE VOLTAGE
V
200
0
20
0
A
= -2
V
A
= -10
V
5
10
15
20
25
30
0.01
0.1
1
10
100
FREQUENCY (MHz)
FREQUENCY (kHz)
FIGURE 24. INVERTING GAIN FLATNESS vs FREQUENCY
FIGURE 25. INPUT NOISE CHARACTERISTICS
FN3393.8
June 2, 2006
10
HA5023
Typical Performance Curves V
= ±5V, A = +1, R = 1kΩ, R = 400Ω, T = 25°C,
SUPPLY
V
F
L
A
Unless Otherwise Specified (Continued)
1.5
2
1.0
0
0.5
0.0
-2
-4
-60 -40 -20
0
20
40
60
80
100 120 140
-60 -40 -20
0
20
40
60
80
100 120 140
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 27. +INPUT BIAS CURRENT vs TEMPERATURE
4000
FIGURE 26. INPUT OFFSET VOLTAGE vs TEMPERATURE
22
3000
20
2000
1000
18
16
-60 -40 -20
0
20
40
60
80
100 120 140
-60 -40 -20
0
20
40
60
80
100 120 140
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 28. -INPUT BIAS CURRENT vs TEMPERATURE
FIGURE 29. TRANSIMPEDANCE vs TEMPERATURE
74
25
+PSRR
-PSRR
72
70
68
66
64
62
60
125°C
20
15
55°C
10
5
CMRR
25°C
58
-100
3
4
5
6
7
8
9
10 11 12
13 14 15
-50
0
50
100
150
200
250
SUPPLY VOLTAGE (±V)
TEMPERATURE (°C)
FIGURE 31. REJECTION RATIO vs TEMPERATURE
FIGURE 30. SUPPLY CURRENT vs SUPPLY VOLTAGE
FN3393.8
June 2, 2006
11
HA5023
Typical Performance Curves V
= ±5V, A = +1, R = 1kΩ, R = 400Ω, T = 25°C,
SUPPLY
V
F
L
A
Unless Otherwise Specified (Continued)
4.0
40
+15V
+10V
30
20
+5V
3.8
10
0
3.6
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
-60 -40 -20
0
20
40
60
80
100 120 140
DISABLE INPUT VOLTAGE (V)
TEMPERATURE (°C)
FIGURE 32. SUPPLY CURRENT vs DISABLE INPUT VOLTAGE
30
FIGURE 33. OUTPUT SWING vs TEMPERATURE
1.2
1.1
V
= ±15V
CC
20
10
1.0
V
= ±10V
CC
0.9
0.8
V
= ±4.5V
CC
0
0.01
0.10
1.00
10.00
-60 -40 -20
0
20
40
60
80
100 120 140
LOAD RESISTANCE (kΩ)
TEMPERATURE (°C)
FIGURE 34. OUTPUT SWING vs LOAD RESISTANCE
FIGURE 35. INPUT OFFSET VOLTAGE CHANGE BETWEEN
CHANNELS vs TEMPERATURE
-30
1.5
A
= +1
= 2V
V
V
OUT
P-P
-40
-50
-60
-70
-80
1.0
0.5
0.0
-60 -40 -20
20
40
60
80 100 120 140
0
0.1
1
10
30
TEMPERATURE (°C)
FREQUENCY (MHz)
FIGURE 36. INPUT BIAS CURRENT CHANGE BETWEEN
CHANNELS vs TEMPERATURE
FIGURE 37. CHANNEL SEPARATION vs FREQUENCY
FN3393.8
June 2, 2006
12
HA5023
Typical Performance Curves V
= ±5V, A = +1, R = 1kΩ, R = 400Ω, T = 25°C,
SUPPLY
V
F
L
A
Unless Otherwise Specified (Continued)
10
1
DISABLE = 0V
0
R
= 100Ω
V
= 5V
P-P
L
IN
R
= 750Ω
F
-10
-20
-30
0.1
0.01
180
135
90
0.001
-40
-50
-60
-70
-80
45
0
-45
-90
-135
0.1
1
10
20
0.001
0.01
0.1
1
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 38. DISABLE FEEDTHROUGH vs FREQUENCY
FIGURE 39. TRANSIMPEDANCE vs FREQUENCY
10
1
R
= 400Ω
L
0.1
180
135
90
0.01
0.001
45
0
-45
-90
-135
0.001
0.01
0.1
1
10
100
FREQUENCY (MHz)
FIGURE 40. TRANSIMPEDENCE vs FREQUENCY
FN3393.8
June 2, 2006
13
HA5023
SUBSTRATE POTENTIAL (Powered Up):
Die Characteristics
V-
DIE DIMENSIONS:
PASSIVATION:
1650µm x 2540µm x 483µm
Type: Nitride
Thickness: 4kÅ ±0.4kÅ
METALLIZATION:
Type: Metal 1: AlCu (1%)
TRANSISTOR COUNT:
Thickness: Metal 1: 8kÅ ±0.4kÅ
124
Type: Metal 2: AlCu (1%)
Thickness: Metal 2: 16kÅ ±0.8kÅ
PROCESS:
High Frequency Bipolar Dielectric Isolation
Metallization Mask Layout
HA5023
OUT
NC
V+
-IN1
+IN1
NC
OUT2
NC
V-
+IN
-IN
FN3393.8
June 2, 2006
14
HA5023
Dual-In-Line Plastic Packages (PDIP)
E8.3 (JEDEC MS-001-BA ISSUE D)
N
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
INCHES
MILLIMETERS
1
2
3
N/2
SYMBOL
MIN
MAX
0.210
-
MIN
-
MAX
5.33
-
NOTES
-B-
-C-
A
A1
A2
B
-
4
-A-
D
E
0.015
0.115
0.014
0.045
0.008
0.355
0.005
0.300
0.240
0.39
2.93
0.356
1.15
0.204
9.01
0.13
7.62
6.10
4
BASE
PLANE
0.195
0.022
0.070
0.014
0.400
-
4.95
0.558
1.77
0.355
10.16
-
-
A2
A
-
SEATING
PLANE
L
C
L
B1
C
8, 10
D1
B1
eA
-
A
A
1
D1
e
D
5
eC
C
B
eB
D1
E
5
0.010 (0.25) M
C
B S
0.325
0.280
8.25
7.11
6
NOTES:
E1
e
5
1. Controlling Dimensions: INCH. In case of conflict between
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
-
English and Metric dimensions, the inch dimensions control.
e
e
6
A
B
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
-
0.430
0.150
-
10.92
3.81
7
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
L
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated
N
8
8
in JEDEC seating plane gauge GS-3.
Rev. 0 12/93
5. D, D1, and E1 dimensions do not include mold flash or protru-
sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
e
6. E and
pendicular to datum
7. e and e are measured at the lead tips with the leads uncon-
are measured with the leads constrained to be per-
A
-C-
.
B
C
strained. e must be zero or greater.
C
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
FN3393.8
June 2, 2006
15
HA5023
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
N
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
NOTES
-B-
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
-
1
2
3
L
9
SEATING PLANE
A
0.0075
0.1890
0.1497
0.0098
0.1968
0.1574
-
-A-
3
h x 45°
D
4
-C-
0.050 BSC
1.27 BSC
-
α
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C
A M B S
N
α
8
8
7
NOTES:
0°
8°
0°
8°
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN3393.8
June 2, 2006
16
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