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HA5024_06 [INTERSIL]

Quad 125MHz Video Current Feedback Amplifier with Disable; 四路125MHz的视频电流反馈放大器具有禁用
HA5024_06
型号： HA5024_06
厂家： Intersil    Intersil
描述：

Quad 125MHz Video Current Feedback Amplifier with Disable
四路125MHz的视频电流反馈放大器具有禁用

放大器
文件： 总16页 (文件大小：415K)
中文：  中文翻译
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HA5024  
®
Data Sheet  
February 8, 2006  
FN3550.6  
Quad 125MHz Video Current  
Features  
Feedback Amplifier with Dis able  
• Quad Version of HA-5020  
The HA5024 is a quad version of the popular Intersil  
HA5020. It features wide bandwidth and high slew rate, and  
is optimized for video applications and gains between 1 and  
10. It is a current feedback amplifier and thus yields less  
bandwidth degradation at high closed loop gains than  
voltage feedback amplifiers.  
• Individual Output Enable/Disable  
• Input Offset Voltage . . . . . . . . . . . . . . . . . . . . . . . . 800µV  
• Wide Unity Gain Bandwidth . . . . . . . . . . . . . . . . . 125MHz  
• Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475V/µs  
• Differential Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.03%  
• Differential Phase. . . . . . . . . . . . . . . . . . . . . 0.03 Degrees  
• Supply Current (per Amplifier) . . . . . . . . . . . . . . . . 7.5mA  
• ESD Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4000V  
• Guaranteed Specifications at ±5V Supplies  
The low differential gain and phase, 0.1dB gain flatness, and  
ability to drive two back terminated 75Ω cables, make this  
amplifier ideal for demanding video applications.  
The HA5024 also features a disable function that  
significantly reduces supply current while forcing the output  
to a true high impedance state. This functionality allows 2:1  
and 4:1 video multiplexers to be implemented with a single IC.  
• Pb-Free Plus Anneal Available (RoHS Compliant)  
The current feedback design allows the user to take  
advantage of the amplifier’s bandwidth dependency on the  
Applications  
• Video Multiplexers; Video Switching and Routing  
• Video Gain Block  
feedback resistor. By reducing R , the bandwidth can be  
increased to compensate for decreases at higher closed  
loop gains or heavy output loads.  
F
• Video Distribution Amplifier/RGB Amplifier  
• Flash A/D Driver  
Ordering Information  
PART  
NUMBER  
PART  
TEMP.  
PKG.  
DWG. #  
• Current to Voltage Converter  
• Medical Imaging  
MARKING RANGE (°C)  
PACKAGE  
HA5024IP  
HA5024IP  
-40 to 85  
-40 to 85  
20 Ld PDIP  
E20.3  
E20.3  
• Radar and Imaging Systems  
HA5024IPZ  
(Note)  
HA5024IPZ  
20 Ld PDIP*  
(Pb-free)  
Pinout  
HA5024IB  
HA5024IB  
-40 to 85  
-40 to 85  
20 Ld SOIC  
M20.3  
M20.3  
HA5024  
(PDIP, SOIC)  
TOP VIEW  
HA5024IBZ  
(Note)  
HA5024IBZ  
20 Ld SOIC  
(Pb-free)  
HA5024IBZ96 HA5024IBZ  
(See Note)  
-40 to 85  
20 Ld SOIC  
Tape and Reel  
(Pb-free)  
M20.3  
1
2
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OUT4  
-IN4  
+IN4  
DIS4  
NC  
OUT1  
-IN1  
+IN1  
DIS1  
NC  
-
-
+
+
3
HA5024EVAL  
High Speed Op Amp DIP Evaluation  
Board  
4
5
*Pb-free PDIPs can be used for through hole wave solder processing  
only. They are not intended for use in Reflow solder processing  
applications.  
NOTE: Intersil Pb-free plus anneal products employ special Pb-free ma-  
terial sets; molding compounds/die attach materials and 100% matte tin  
plate termination finish, which are RoHS compliant and compatible with  
both SnPb and Pb-free soldering operations. Intersil Pb-free products  
are MSL classified at Pb-free peak reflow temperatures that meet or ex-  
ceed the Pb-free requirements of IPC/JEDEC J STD-020.  
6
V+  
V-  
7
DIS3  
+IN3  
DIS2  
+IN2  
-IN2  
OUT2  
8
+
+
-
-
9
-IN3  
10  
OUT3  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
Copyright Intersil Americas Inc. 1998, 2005, 2006. All Rights Reserved  
1
All other trademarks mentioned are the property of their respective owners.  
HA5024  
Absolute Maximum Ratings  
Thermal Information  
Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . 36V  
DC Input Voltage (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . ±V  
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10V  
Output Current (Note 4) . . . . . . . . . . . . . . . . Short Circuit Protected  
ESD Rating (Note 3)  
Thermal Resistance (Typical, Note 2)  
θJA (°C/W)  
SUPPLY  
PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  
75  
90  
Maximum Junction Temperature (Note 1) . . . . . . . . . . . . . . . . . 175°C  
Maximum Junction Temperature (Plastic Package, Note 1) . . . 150°C  
Maximum Storage Temperature Range . . . . . . . . . -65°C to 150°C  
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C  
(SOIC - Lead Tips Only)  
Human Body Model (Per MIL-STD-883 Method 3015.7) . . .2000V  
Operating Conditions  
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C  
Supply Voltage Range (Typical) . . . . . . . . . . . . . . . . ±4.5V to ±15V  
*Pb-free PDIPs can be used for through hole wave solder processing  
only. They are not intended for use in Reflow solder processing  
applications.  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the  
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
NOTES:  
1. Maximum power dissipation, including output load, must be designed to maintain junction temperature below 175°C for die, and below 150°C  
for plastic packages. See Application Information section for safe operating area information.  
2. θ is measured with the component mounted on an evaluation PC board in free air.  
JA  
3. The non-inverting input of unused amplifiers must be connected to GND.  
4. Output is protected for short circuits to ground. Brief short circuits to ground will not degrade reliability, however, continuous (100% duty cycle)  
output current should not exceed 15mA for maximum reliability.  
Electrical Specifications  
V
= ±5V, R = 1kΩ, A = +1, R = 400Ω, C ≤ 10pF,Unless Otherwise Specified  
SUPPLY  
F
V
L
L
(NOTE 11)  
TEST  
LEVEL  
TEMP.  
(°C)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
INPUT CHARACTERISTICS  
Input Offset Voltage (V  
)
A
A
A
B
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
25  
Full  
Full  
Full  
25  
-
0.8  
-
3
5
mV  
mV  
mV  
µV/°C  
dB  
IO  
-
Delta V Between Channels  
IO  
-
1.2  
5
-
3.5  
-
Average Input Offset Voltage Drift  
-
V
V
Common Mode Rejection Ratio  
Note 5  
53  
-
IO  
IO  
Full  
25  
50  
-
-
dB  
Power Supply Rejection Ratio  
±3.5V ≤ V ≤ ±6.5V  
60  
-
-
dB  
S
Full  
Full  
25  
55  
-
-
dB  
Input Common Mode Range  
Note 5  
Note 5  
±2.5  
-
-
V
Non-Inverting Input (+IN) Current  
-
-
-
-
-
-
-
-
-
-
-
-
3
-
8
µA  
Full  
25  
20  
0.15  
0.5  
0.1  
0.3  
12  
30  
15  
30  
0.4  
1.0  
µA  
+IN Common Mode Rejection  
1
-
µA/V  
µA/V  
µA/V  
µA/V  
µA  
(+I  
=
)
---------  
BCMR  
Full  
25  
-
R
IN  
+IN Power Supply Rejection  
±3.5V ≤ V ≤ ±6.5V  
-
S
Full  
25,85  
-40  
25,85  
-40  
25  
-
Inverting Input (-IN) Current  
4
10  
6
10  
-
µA  
Delta -IN BIAS Current Between Channels  
-IN Common Mode Rejection  
µA  
µA  
Note 5  
µA/V  
µA/V  
Full  
-
3550.6  
February 8, 2006  
2
HA5024  
Electrical Specifications  
V
= ±5V, R = 1kΩ, A = +1, R = 400Ω, C ≤ 10pF,Unless Otherwise Specified (Continued)  
SUPPLY  
F
V
L
L
(NOTE 11)  
TEST  
LEVEL  
TEMP.  
(°C)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
-
MAX  
UNITS  
µA/V  
-IN Power Supply Rejection  
±3.5V ≤ V ≤ ±6.5V  
A
A
B
B
B
25  
Full  
25  
-
-
-
-
-
0.2  
S
-
0.5  
µA/V  
Input Noise Voltage  
f = 1kHz  
f = 1kHz  
f = 1kHz  
4.5  
2.5  
25.0  
-
-
-
nV/√Hz  
pA/√Hz  
pA/√Hz  
+Input Noise Current  
-Input Noise Current  
25  
25  
TRANSFER CHARACTERISTICS  
Transimpedence  
Note 16  
A
A
25  
Full  
25  
1.0  
0.85  
70  
-
-
-
-
-
-
-
-
-
-
-
-
MΩ  
MΩ  
dB  
Open Loop DC Voltage Gain  
Open Loop DC Voltage Gain  
R
R
= 400Ω, V  
= 100Ω, V  
= ±2.5V  
25A  
A
L
L
OUT  
OUT  
Full  
25  
65  
dB  
= ±2.5V  
A
50  
dB  
A
Full  
45  
dB  
OUTPUT CHARACTERISTICS  
Output Voltage Swing  
R
R
= 150Ω  
= 150Ω  
A
A
B
A
A
25  
±2.5  
±2.5  
±16.6  
±40  
-
±3.0  
±3.0  
±20.0  
±60  
-
-
-
V
L
Full  
Full  
Full  
Full  
V
Output Current  
-
mA  
mA  
µA  
L
Output Current, Short Circuit  
Output Current, Disabled (Note 5)  
V
= ±2.5V, V  
= 0V  
OUT  
-
IN  
DISABLE = 0V,  
= ±2.5V, V = 0V  
2
V
OUT  
IN  
Output Disable Time  
Note 12  
Note 13  
Note 14  
B
B
B
25  
25  
25  
-
-
-
40  
40  
15  
-
-
-
µs  
ns  
pF  
Output Enable Time  
Output Capacitance Disabled  
POWER SUPPLY CHARACTERISTICS  
Supply Voltage Range  
A
A
A
A
25  
5
-
-
15  
10  
V
Quiescent Supply Current  
Full  
Full  
Full  
7.5  
5
mA/Op Amp  
mA/Op Amp  
mA  
Supply Current, Disabled  
DISABLE = 0V  
DISABLE = 0V  
-
7.5  
1.5  
-
1.0  
Disable Pin Input Current  
Minimum Pin 8 Current to Disable  
Maximum Pin 8 Current to Enable  
Note 6  
Note 7  
A
A
Full  
Full  
350  
-
-
-
-
µA  
µA  
20  
AC CHARACTERISTICS (A = +1)  
V
Slew Rate  
Note 8  
B
B
B
B
B
B
B
B
B
25  
25  
25  
25  
25  
25  
25  
25  
25  
275  
350  
28  
6
-
-
-
-
-
-
-
-
-
V/µs  
MHz  
ns  
Full Power Bandwidth  
Rise Time  
Note 9  
22  
-
Note 10  
Note 10  
Note 10  
Fall Time  
-
6
ns  
Propagation Delay  
Overshoot  
-
6
ns  
-
4.5  
125  
50  
75  
%
-3dB Bandwidth  
Settling Time to 1%  
Settling Time to 0.25%  
V
= 100mV  
-
MHz  
ns  
OUT  
2V Output Step  
2V Output Step  
-
-
ns  
3550.6  
3
February 8, 2006  
HA5024  
Electrical Specifications  
V
= ±5V, R = 1kΩ, A = +1, R = 400Ω, C ≤ 10pF,Unless Otherwise Specified (Continued)  
SUPPLY  
F
V
L
L
(NOTE 11)  
TEST  
LEVEL  
TEMP.  
(°C)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
AC CHARACTERISTICS (A = +2, R = 681Ω)  
V
F
Slew Rate  
Note 8  
B
B
B
B
B
B
B
B
B
B
B
25  
25  
25  
25  
25  
25  
25  
25  
25  
25  
25  
-
-
-
-
-
-
-
-
-
-
-
475  
26  
-
-
-
-
-
-
-
-
-
-
-
V/µs  
MHz  
ns  
Full Power Bandwidth  
Rise Time  
Note 9  
Note 10  
Note 10  
Note 10  
6
Fall Time  
6
ns  
Propagation Delay  
Overshoot  
6
ns  
12  
%
-3dB Bandwidth  
Settling Time to 1%  
Settling Time to 0.25%  
Gain Flatness  
V
= 100mV  
95  
MHz  
ns  
OUT  
2V Output Step  
2V Output Step  
5MHz  
50  
100  
0.02  
0.07  
ns  
dB  
dB  
20MHz  
AC CHARACTERISTICS (A = +10, R = 383Ω)  
V
F
Slew Rate  
Note 8  
B
B
B
B
B
B
B
B
B
25  
25  
25  
25  
25  
25  
25  
25  
25  
350  
475  
38  
8
-
-
-
-
-
-
-
-
-
V/µs  
MHz  
ns  
Full Power Bandwidth  
Rise Time  
Note 9  
28  
-
Note 10  
Note 10  
Note 10  
Fall Time  
-
9
ns  
Propagation Delay  
Overshoot  
-
9
ns  
-
1.8  
65  
75  
130  
%
-3dB Bandwidth  
Settling Time to 1%  
Settling Time to 0.1%  
V
= 100mV  
-
MHz  
ns  
OUT  
2V Output Step  
2V Output Step  
-
-
ns  
VIDEO CHARACTERISTICS  
Differential Gain (Note 15)  
Differential Phase (Note 15)  
NOTES:  
R
R
= 150Ω  
= 150Ω  
B
B
25  
25  
-
-
0.03  
0.03  
-
-
%
L
L
Degrees  
5. V  
= ±2.5V. At -40°C Product is tested at V  
= ±2.25V because short test duration does not allow self heating.  
CM  
CM  
6. R = 100Ω, V = 2.5V. This is the minimum current which must be pulled out of the Disable pin in order to disable the output. The output is  
L
IN  
considered disabled when -10mV ≤ V  
≤ +10mV.  
OUT  
7. V = 0V. This is the maximum current that can be pulled out of the Disable pin with the HA5024 remaining enabled. The HA5024 is  
IN  
considered disabled when the supply current has decreased by at least 0.5mA.  
8. V  
switches from -2V to +2V, or from +2V to -2V. Specification is from the 25% to 75% points.  
OUT  
Slew Rate  
.
9.  
----------------------------  
FPBW =  
; V  
= 2V  
PEAK  
2πV  
PEAK  
10. R = 100Ω, V  
= 1V. Measured from 10% to 90% points for rise/fall times; from 50% points of input and output for propagation delay.  
L
OUT  
11. A. Production Tested; B. Typical or Guaranteed Limit based on characterization; C. Design Typical for information only.  
12. V = +2V, DISABLE = +5V to 0V. Measured from the 50% point of DISABLE to V  
IN  
= 0V.  
= 2V.  
OUT  
OUT  
13. V = +2V, DISABLE = 0V to +5V. Measured from the 50% point of DISABLE to V  
IN  
14. V = 0V, Force V  
IN  
from 0V to ±2.5V, t = t = 50ns, DISABLE = 0V.  
R F  
OUT  
15. Measured with a VM700A video tester using an NTC-7 composite VITS.  
16. V  
= ±2.5V. At -40°C Product is tested at V  
= ±2.25V because short test duration does not allow self heating.  
OUT  
OUT  
3550.6  
4
February 8, 2006  
HA5024  
Tes t Circuits and Waveforms  
+
-
DUT  
50Ω  
HP4195  
NETWORK  
ANALYZER  
50Ω  
FIGURE 1. TEST CIRCUIT FOR TRANSIMPEDANCE MEASUREMENTS  
(NOTE 17)  
100Ω  
(NOTE 17)  
100Ω  
DUT  
V
+
-
IN  
DUT  
V
OUT  
V
+
-
IN  
V
OUT  
50Ω  
R
L
400Ω  
50Ω  
R
L
R , 681Ω  
F
R
681Ω  
I
100Ω  
R , 1kΩ  
F
FIGURE 3. LARGE SIGNAL PULSE RESPONSE CIRCUIT  
FIGURE 2. SMALL SIGNAL PULSE RESPONSE CIRCUIT  
NOTE:  
17. A series input resistor of ≥100Ω is recommended to limit input currents in case input signals are present before the HA5024 is powered up.  
Vertical Scale: V = 1V/Div., V  
= 1V/Div.  
Horizontal Scale: 50ns/Div.  
Vertical Scale: V = 100mV/Div., V  
IN  
=
IN OUT  
OUT  
100mV/Div.  
FIGURE 5. LARGE SIGNAL RESPONSE  
FIGURE 4. SMALL SIGNAL RESPONSE  
3550.6  
February 8, 2006  
5
Schematic (One Amplifier of Four)  
V+  
R
800  
R
2.5K  
R
15K  
R
2
5
6
10  
820  
R
R
R
2K  
R
15  
400  
19  
400  
D
Q
Q
P9  
33  
29  
9.5  
2
P8  
R
27  
200  
Q
P19  
Q
Q
P14  
P11  
Q
P18  
R
Q
31  
Q
P1  
P5  
R
1K  
5
11  
R
R
18  
17  
280 280  
R
24  
140  
Q
Q
P16  
N5  
Q
P20  
Q
P10  
R
20  
140  
Q
P15  
Q
N12  
P12  
R
8
1.25K  
C
1
Q
N8  
1.4pF  
Q
P2  
Q
R
20  
Q
28  
P3  
Q
R
60K  
1
Q
P6  
-IN  
N6  
R
15K  
7
R
280  
12  
Q
P17  
Q
N1  
Q
Q
N13  
P13  
Q
+IN  
P4  
Q
N17  
DIS  
R
25  
R
3
6K  
C
2
1.4pF  
20  
Q
N15  
Q
N2  
R
21  
140  
Q
Q
R
N10  
N21  
R
R
R
D
1
Q
P7  
14  
280  
22  
280  
25  
140  
Q
N4  
32  
5
Q
N16  
Q
N18  
Q
R
1K  
N14  
Q
13  
Q
N19  
N20  
Q
Q
N3  
N7  
R
7
30  
R
23  
400  
R
R
R
26  
200  
16  
400  
26  
200  
OUT  
R
800  
R
R
9
820  
4
33  
800  
Q
Q
N11  
N9  
V-  
HA5024  
Driving Capacitive Loads  
Application Information  
Capacitive loads will degrade the amplifier’s phase margin  
resulting in frequency response peaking and possible  
oscillations. In most cases the oscillation can be avoided by  
placing an isolation resistor (R) in series with the output as  
shown in Figure 6.  
Optimum Feedback Res is tor  
The plots of inverting and non-inverting frequency response,  
see Figure 11 and Figure 12 in the Typical Performance  
Curves section, illustrate the performance of the HA5024 in  
various closed loop gain configurations. Although the  
bandwidth dependency on closed loop gain isn’t as severe  
as that of a voltage feedback amplifier, there can be an  
appreciable decrease in bandwidth at higher gains. This  
decrease may be minimized by taking advantage of the  
current feedback amplifier’s unique relationship between  
100Ω  
R
V
+
-
IN  
V
OUT  
R
T
C
L
R
F
bandwidth and R . All current feedback amplifiers require a  
F
R
I
feedback resistor, even for unity gain applications, and R ,  
F
in conjunction with the internal compensation capacitor, sets  
the dominant pole of the frequency response. Thus, the  
FIGURE 6. PLACEMENT OF THE OUTPUT ISOLATION  
RESISTOR, R  
amplifier’s bandwidth is inversely proportional to R . The  
F
HA5024 design is optimized for a 1000Ω R at a gain of +1.  
F
The selection criteria for the isolation resister is highly  
dependent on the load, but 27Ω has been determined to be  
a good starting value.  
Decreasing R in a unity gain application decreases stability,  
F
resulting in excessive peaking and overshoot. At higher  
gains the amplifier is more stable, so R can be decreased  
F
in a trade-off of stability for bandwidth.  
Power Dis s ipation Cons iderations  
Due to the high supply current inherent in quad amplifiers, care  
must be taken to insure that the maximum junction temperature  
The table below lists recommended R values for various  
F
gains, and the expected bandwidth.  
(T see Absolute Maximum Ratings) is not exceeded. Figure 7  
shows the maximum ambient temperature versus supply  
voltage for the available package styles (Plastic DIP, SOIC). At  
J,  
GAIN (A  
-1  
)
R
(Ω)  
BANDWIDTH (MHz)  
CL  
F
750  
1000  
681  
100  
125  
95  
+1  
±5V quiescent operation both package styles may be  
DC  
operated over the full industrial range of -40°C to 85°C. It is  
recommended that thermal calculations, which take into  
account output power, be performed by the designer.  
130  
+2  
+5  
1000  
383  
52  
+10  
-10  
65  
750  
22  
120  
110  
PC Board Layout  
PDIP  
The frequency response of this amplifier depends greatly on  
the amount of care taken in designing the PC board. The  
use of low inductance components such as chip resistors  
and chip capacitors is strongly recommended. If leaded  
components are used the leads must be kept short  
especially for the power supply decoupling components and  
those components connected to the inverting input.  
100  
90  
80  
70  
SOIC  
60  
50  
Attention must be given to decoupling the power supplies. A  
large value (10µF) tantalum or electrolytic capacitor in  
parallel with a small value (0.1µF) chip capacitor works well  
in most cases.  
5
7
9
11  
13  
15  
SUPPLY VOLTAGE (±V)  
FIGURE 7. MAXIMUM OPERATING AMBIENT TEMPERA-  
TURE vs SUPPLY VOLTAGE  
A ground plane is strongly recommended to control noise.  
Care must also be taken to minimize the capacitance to  
ground seen by the amplifier’s inverting input (-IN). The  
larger this capacitance, the worse the gain peaking, resulting  
in pulse overshoot and possible instability. It is  
recommended that the ground plane be removed under  
traces connected to -IN, and that connections to -IN be kept  
as short as possible to minimize the capacitance from this  
node to ground.  
Enable/Dis able Function  
When enabled the amplifier functions as a normal current  
feedback amplifier with all of the data in the electrical  
specifications table being valid and applicable. When  
disabled the amplifier output assumes a true high  
impedance state and the supply current is reduced  
significantly.  
3550.6  
February 8, 2006  
7
HA5024  
The circuit shown in Figure 8 is a simplified schematic of the  
enable/disable function. The large value resistors in series with  
the DISABLE pin makes it appear as a current source to the  
driver. When the driver pulls this pin low current flows out of the  
pin and into the driver. This current, which may be as large as  
350µA when external circuit and process variables are at their  
extremes, is required to insure that point “A” achieves the  
proper potential to disable the output.The driver must have the  
compliance and capability of sinking all of this current.  
When the plus supply rail is 5V the disable pin can be driven by  
a dedicated TTL gate as discussed earlier. If a multiplexer IC or  
its equivalent is used to select channels its logic must be break  
before make. When these conditions are satisfied the  
HA5024IP is often used as a remote video multiplexer, and the  
multiplexer may be extended by adding more amplifier ICs.  
Low Impedance Multiplexer  
Two common problems surface when you try to multiplex  
multiple high speed signals into a low impedance source such  
as an A/D converter. The first problem is the low source  
impedance which tends to make amplifiers oscillate and  
causes gain errors. The second problem is the multiplexer  
which supplies no gain, introduces all kinds of distortion and  
limits the frequency response. Using op amps which have an  
enable/disable function, such as the HA5024, eliminates the  
multiplexer problems because the external mux chip is not  
needed, and the HA5024 can drive low impedance (large  
capacitance) loads if a series isolation resistor is used.  
When V  
is +5V the DISABLE pin may be driven with a  
CC  
dedicated TTL gate. The maximum low level output voltage  
of the TTL gate, 0.4V, has enough compliance to insure that  
the amplifier will always be disabled even though D will not  
1
turn on, and the TTL gate will sink enough current to keep  
point “A” at its proper voltage. When V  
is greater than +5V  
CC  
the DISABLE pin should be driven with an open collector  
device that has a breakdown rating greater than V  
.
CC  
Referring to Figure 8, it can be seen that R will act as a pull-up  
6
(NOTE 17)  
VIDEO  
resistor to +V if the DISABLE pin is left open. In those cases  
CC  
R
75  
VIDEO OUTPUT  
100Ω  
4
INPUT  
#1  
3
where the enable/disable function is not required on all circuits  
some circuits can be permanently enabled by letting the  
DISABLE pin float. If a driver is used to set the enable/disable  
level, be sure that the driver does not sink more than 20µA  
when the DISABLE pin is at a high level. TTL gates, especially  
CMOS versions, do not violate this criteria so it is permissible to  
control the enable/disable function with TTL.  
TO 75Ω LOAD  
1
+
2
-
R
75  
U
4
2
1
1A  
R
5
R
681  
R
3
2000  
681  
R
21  
100  
1
R
75  
9
(NOTE 17)100Ω  
8
9
+5V  
10  
+
-
+V  
2
3
4
CC  
S
1
U
R
6
7
1B  
R
15K  
R
75  
6
33  
R
R
ALL  
OFF  
10  
R
10  
R
7
2000  
R
8
681  
Q
P18  
681  
D
1
-5V  
8
R
15K  
7
A
(NOTE 17)  
VIDEO  
INPUT  
#3  
R
14  
75  
15  
100Ω  
13  
Q
P3  
11  
+
-
12  
ENABLE/DISABLE INPUT  
R
14  
U
11  
75  
1C  
FIGURE 8. SIMPLIFIED SCHEMATIC OF ENABLE/DISABLE  
FUNCTION  
R
15  
2000  
R
12  
681  
R
13  
681  
Typical Applications  
Four Channel Video Multiplexer  
+5V  
(NOTE 17)  
VIDEO  
INPUT  
#4  
R
19  
75  
100Ω  
6
18  
20  
+
-
Referring to the amplifier U in Figure 9, R terminates the  
19  
1D  
1A  
1
R
U
17  
16  
75  
cable in its characteristic impedance of 75Ω, and R back  
4
terminates the cable in its characteristic impedance. The  
amplifier is set up in a gain configuration of +2 to yield an  
overall network gain of +1 when driving a double terminated  
R
20  
2000  
R
17  
681  
R
18  
681  
cable. The value of R can be changed if a different network  
3
+5V IN  
+5V -5V IN  
10µF 0.1µF  
-5V  
10µF  
gain is desired. R holds the disable pin at ground thus  
5
inhibiting the amplifier until the switch, S , is thrown to  
1
0.1µF  
position 1. At position 1 the switch pulls the disable pin up to  
the plus supply rail thereby enabling the amplifier. Since all  
of the actual signal switching takes place within the amplifier,  
its differential gain and phase parameters, which are 0.03%  
and 0.03 degrees respectively, determine the circuit’s  
NOTES:  
18. U is HA5024IP.  
1
19. All resistors in Ω.  
20. S is break before make.  
1
21. Use ground plane.  
performance. The other three circuits, U through U  
,
1B  
1D  
FIGURE 9. FOUR CHANNEL VIDEO MULTIPLEXER  
operate in a similar manner.  
3550.6  
February 8, 2006  
8
HA5024  
Referring to Figure 10, both inputs are terminated in their  
characteristic impedance; 75Ω is typical for video  
to be break before make. R is enclosed in the feedback  
loop of the amplifier so that the large open loop amplifier  
4
applications. Since the drivers usually are terminated in their  
characteristic impedance the input gain is 0.5, thus the  
gain of U will present the load with a small closed loop  
output impedance while keeping the amplifier stable for all  
values of load capacitance.  
2
amplifiers, U , are configured in a gain of +2 to set the circuit  
2
gain equal to one. Resistors R and R determine the amplifier  
2
3
The circuit shown in Figure 10 was tested for the full range of  
capacitor values with no oscillations being observed; thus,  
problem one has been solved.The frequency and gain  
characteristics of the circuit are now those of the amplifier  
independent of any multiplexing action; thus, problem two  
has been solved. The multiplexer transition time is  
gain, and if a different gain is desired R should be changed  
2
according to the equation G = (1 + R /R ). R sets the  
3
2
3
frequency response of the amplifier so you should refer to the  
manufacturers data sheet before changing its value. R , C  
5
1
and D are an asymmetrical charge/discharge time circuit  
1
which configures U as a break before make switch to prevent  
1
approximately 15µs with the component values shown.  
both amplifiers from being active simultaneously. If this design  
is extended to more channels the drive logic must be designed  
R
3A  
681  
INPUT B  
R
681  
1A  
R
R
1A  
75  
4A  
27  
U
2A  
16  
-
1
2
+
4
INPUT A  
-5V  
0.01µF  
100Ω  
(NOTE 17)  
3
D
R
1B  
75  
1A  
1N4148  
R
5A  
2000  
R
3B  
681  
U
1C  
C
1A  
0.047µF  
R
681  
2B  
R
4B  
27  
U
2B  
CHANNEL  
SWITCH  
7
6
10  
-
OUTPUT  
+
13  
5
+5V  
0.01µF  
100Ω  
(NOTE 17)  
R
5B  
2000  
U
1D  
U
1B  
U
C
NOTES:  
22. U : HA5022/24.  
1A  
1B  
0.047µF  
INHIBIT  
2
D
1B  
1N4148  
R
6
23. U : CD4011.  
100K  
1
FIGURE 10. LOW IMPEDANCE MULTIPLEXER  
3550.6  
9
February 8, 2006  
HA5024  
Typical Performance Curves  
V
= ±5V, A = +1, R = 1kΩ, R = 400Ω, T = 25°C,  
SUPPLY  
V
F
L
A
Unless Otherwise Specified  
5
5
4
3
2
1
0
V
C
= 0.2V  
P-P  
OUT  
= 10pF  
V
C
= 0.2V  
P-P  
OUT  
= 10pF  
A
= +1, R = 1kΩ  
F
4
3
V
L
L
R
= 750Ω  
A
= 2, R = 681Ω  
F
V
F
A
= -1  
= -2  
V
2
1
A
= 5, R = 1kΩ  
V
F
A
V
0
-1  
-1  
-2  
-3  
-4  
-2  
-3  
-4  
A
= -10  
V
A
= 10, R = 383Ω  
F
V
A
= -5  
V
-5  
-5  
2
10  
100  
200  
2
10  
FREQUENCY (MHz)  
100  
200  
FREQUENCY (MHz)  
FIGURE 12. INVERTING FREQUENCY RESPONSE  
FIGURE 11. NON-INVERTING FREQUENCY RESPONSE  
140  
V
C
A
= 0.2V  
P-P  
= 10pF  
= +1  
OUT  
180  
135  
90  
0
-45  
A
= +1, R = 1kΩ  
F
V
L
V
130  
120  
-90  
A
= -1, R = 750Ω  
F
V
45  
0
-135  
-100  
-225  
A
= +10, R = 383Ω  
F
V
-3dB BANDWIDTH  
10  
-45  
-90  
-270  
A
= -10, R = 750Ω  
F
V
5
0
-135  
-180  
-315  
-360  
V
C
= 0.2V  
P-P  
OUT  
= 10pF  
GAIN PEAKING  
L
2
10  
FREQUENCY (MHz)  
100  
200  
500  
700  
900  
1100  
1300  
1500  
FEEDBACK RESISTOR (Ω)  
FIGURE 14. BANDWIDTH AND GAIN PEAKING vs FEEDBACK  
RESISTANCE  
FIGURE 13. PHASE RESPONSE AS A FUNCTION OF  
FREQUENCY  
100  
130  
V
= 0.2V  
P-P  
OUT  
C
A
= 10pF  
= +2  
L
V
120  
-3dB BANDWIDTH  
95  
90  
110  
100  
6
-3dB BANDWIDTH  
10  
4
2
GAIN PEAKING  
= 0.2V  
5
0
V
OUT  
P-P  
90  
80  
C
A
= 10pF  
= +1  
L
V
GAIN PEAKING  
0
0
200  
400  
600  
800  
1000  
350  
500  
650  
800  
950  
1100  
LOAD RESISTOR (Ω)  
FEEDBACK RESISTOR (Ω)  
FIGURE 15. BANDWIDTH AND GAIN PEAKING vs FEEDBACK  
RESISTANCE  
FIGURE 16. BANDWIDTH AND GAIN PEAKING vs LOAD  
RESISTANCE  
3550.6  
February 8, 2006  
10  
HA5024  
Typical Performance Curves  
V
= ±5V, A = +1, R = 1kΩ, R = 400Ω, T = 25°C,  
SUPPLY  
V
F
L
A
Unless Otherwise Specified (Continued)  
16  
80  
V
C
= 0.1V  
P-P  
OUT  
= 10pF  
V
C
A
= 0.2V  
P-P  
= 10pF  
= +10  
OUT  
L
L
V
V
= ±5V, A = +2  
V
SUPPLY  
60  
12  
40  
20  
0
6
V
= ±15V, A = +2  
V
SUPPLY  
V
= ±5V, A = +1  
SUPPLY  
V
V
= ±15V, A = +1  
V
SUPPLY  
0
200  
350  
500  
650  
800  
950  
0
200  
400  
600  
800  
1000  
FEEDBACK RESISTOR (Ω)  
LOAD RESISTANCE (Ω)  
FIGURE 17. BANDWIDTH vs FEEDBACK RESISTANCE  
FIGURE 18. SMALL SIGNAL OVERSHOOT vs LOAD  
RESISTANCE  
0.08  
0.10  
FREQUENCY = 3.58MHz  
FREQUENCY = 3.58MHz  
0.08  
0.06  
0.04  
R
= 75Ω  
L
0.06  
0.04  
R
= 150Ω  
L
R
= 150Ω  
L
R
= 75Ω  
L
0.02  
0.00  
0.02  
0.00  
R
= 1kΩ  
L
R
= 1kΩ  
L
3
5
7
9
11  
13  
15  
3
5
7
9
11  
13  
15  
SUPPLY VOLTAGE (±V)  
SUPPLY VOLTAGE (±V)  
FIGURE 20. DIFFERENTIAL PHASE vs SUPPLY VOLTAGE  
FIGURE 19. DIFFERENTIAL GAIN vs SUPPLY VOLTAGE  
-40  
A
= +1  
V
V
C
= 2.0V  
OUT  
= 30pF  
P-P  
0
-10  
-20  
-30  
L
-50  
-60  
HD  
2
3RD ORDER IMD  
-40  
-50  
CMRR  
-70  
HD  
2
HD  
3
-60  
-70  
-80  
NEGATIVE PSRR  
-80  
-90  
POSITIVE PSRR  
0.1  
HD  
3
0.3  
1
10  
0.001  
0.01  
1
10  
30  
FREQUENCY (MHz)  
FREQUENCY (MHz)  
FIGURE 22. REJECTION RATIOS vs FREQUENCY  
FIGURE 21. DISTORTION vs FREQUENCY  
3550.6  
11  
February 8, 2006  
HA5024  
Typical Performance Curves  
V
= ±5V, A = +1, R = 1kΩ, R = 400Ω, T = 25°C,  
SUPPLY  
V
F
L
A
Unless Otherwise Specified (Continued)  
12  
8.0  
R
= 100Ω  
= 1.0V  
L
R
= 100Ω  
LOAD  
V
OUT  
= +1  
P-P  
V
= 1.0V  
OUT  
P-P  
A
V
10  
7.5  
7.0  
A
A
= +10, R = 383Ω  
F
V
V
8
= +2, R = 681Ω  
F
6
4
6.5  
6.0  
A
= +1, R = 1kΩ  
F
V
3
5
7
9
11  
13  
15  
-50  
-25  
0
25  
50  
75  
100  
125  
SUPPLY VOLTAGE (±V)  
TEMPERATURE (°C)  
FIGURE 23. PROPAGATION DELAY vs TEMPERATURE  
FIGURE 24. PROPAGATION DELAY vs SUPPLY VOLTAGE  
500  
0.8  
V
= 2V  
P-P  
OUT  
V
C
= 0.2V  
P-P  
OUT  
= 10pF  
0.6  
0.4  
0.2  
0
450  
400  
350  
300  
L
+ SLEW RATE  
A = +2, R = 681Ω  
V
F
- SLEW RATE  
-0.2  
-0.4  
-0.6  
250  
A = +5, R = 1kΩ  
V
F
A
= +1, R = 1kΩ  
F
200  
150  
100  
V
-0.8  
-1.0  
-1.2  
A
= +10, R = 383Ω  
V
F
-50  
-25  
0
25  
50  
75  
100  
125  
5
10  
15  
20  
25  
30  
TEMPERATURE (°C)  
FREQUENCY (MHz)  
FIGURE 26. NON-INVERTING GAIN FLATNESS vs FRE-  
QUENCY  
FIGURE 25. SLEW RATE vs TEMPERATURE  
0.8  
100  
1000  
800  
V
C
R
= 0.2V  
P-P  
OUT  
L
F
A
= +10, R = 383Ω  
F
0.6  
0.4  
V
= 10pF  
= 750Ω  
-INPUT NOISE CURRENT  
80  
60  
40  
0.2  
A
A
= -1  
= -5  
V
V
600  
0
-0.2  
-0.4  
-0.6  
-0.8  
-1.0  
-1.2  
+INPUT NOISE CURRENT  
400  
INPUT NOISE VOLTAGE  
200  
0
20  
0
A
= -2  
V
A
= -10  
V
0.01  
0.1  
1
10  
100  
5
10  
15  
20  
25  
30  
FREQUENCY (kHz)  
FREQUENCY (MHz)  
FIGURE 28. INPUT NOISE CHARACTERISTICS  
FIGURE 27. INVERTING GAIN FLATNESS vs FREQUENCY  
3550.6  
February 8, 2006  
12  
HA5024  
Typical Performance Curves  
V
= ±5V, A = +1, R = 1kΩ, R = 400Ω, T = 25°C,  
SUPPLY  
V
F
L
A
Unless Otherwise Specified (Continued)  
1.5  
2
1.0  
0
-2  
-4  
0.5  
0.0  
-60 -40 -20  
0
20  
40  
60  
80  
100 120 140  
-60 -40 -20  
0
20  
40  
60  
80  
100 120 140  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
FIGURE 30. +INPUT BIAS CURRENT vs TEMPERATURE  
4000  
FIGURE 29. INPUT OFFSET VOLTAGE vs TEMPERATURE  
22  
3000  
20  
2000  
1000  
18  
16  
-60  
-40 -20  
0
20  
40  
60  
80  
100 120 140  
-60 -40 -20  
0
20  
40  
60  
80  
100 120 140  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
FIGURE 32. TRANSIMPEDANCE vs TEMPERATURE  
FIGURE 31. -INPUT BIAS CURRENT vs TEMPERATURE  
74  
25  
72  
70  
68  
66  
64  
62  
60  
+PSRR  
55°C  
20  
125°C  
-PSRR  
15  
10  
CMRR  
25°C  
5
58  
-100  
3
4
5
6
7
8
9
10 11 12  
13 14 15  
-50  
0
50  
100  
150  
200  
250  
TEMPERATURE (°C)  
SUPPLY VOLTAGE (±V)  
FIGURE 34. REJECTION RATIO vs TEMPERATURE  
FIGURE 33. SUPPLY CURRENT vs SUPPLY VOLTAGE  
3550.6  
13  
February 8, 2006  
HA5024  
Typical Performance Curves  
V
= ±5V, A = +1, R = 1kΩ, R = 400Ω, T = 25°C,  
SUPPLY  
V
F
L
A
Unless Otherwise Specified (Continued)  
40  
4.0  
+10V  
+15V  
30  
20  
+5V  
3.8  
10  
0
3.6  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15  
-60 -40 -20  
0
20  
40  
60  
80  
100 120 140  
DISABLE INPUT VOLTAGE (V)  
TEMPERATURE (°C)  
FIGURE 35. SUPPLY CURRENT vs DISABLE INPUT VOLTAGE  
30  
FIGURE 36. OUTPUT SWING vs TEMPERATURE  
1.2  
1.1  
V
= ±15V  
S
20  
10  
V
= ±10V  
S
1.0  
0.9  
0.8  
V
= ±4.5V  
S
0
0.01  
0.10  
1.00  
10.00  
-60 -40 -20  
0
20  
40  
60  
80  
100 120 140  
LOAD RESISTANCE (kΩ)  
TEMPERATURE (°C)  
FIGURE 37. OUTPUT SWING vs LOAD RESISTANCE  
FIGURE 38. INPUT OFFSET VOLTAGE CHANGE BETWEEN  
CHANNELS vs TEMPERATURE  
1.5  
30  
25  
20  
-55°C  
1.0  
25°C  
15  
10  
5
0.5  
0.0  
125°C  
-60 -40 -20  
20  
40  
60  
80 100 120 140  
3
4
5
6
7
8
9
10 11 12 13 14 15  
0
SUPPLY VOLTAGE (±V)  
TEMPERATURE (°C)  
FIGURE 39. INPUT BIAS CURRENT CHANGE BETWEEN  
CHANNELS vs TEMPERATURE  
FIGURE 40. DISABLE SUPPLY CURRENT vs SUPPLY  
VOLTAGE  
3550.6  
February 8, 2006  
14  
HA5024  
Typical Performance Curves  
V
= ±5V, A = +1, R = 1kΩ, R = 400Ω, T = 25°C,  
SUPPLY  
V
F
L
A
Unless Otherwise Specified (Continued)  
-30  
32  
30  
20  
18  
A
= +1  
= 2V  
V
V
OUT  
P-P  
ENABLE  
-40  
-50  
-60  
-70  
-80  
28  
26  
24  
22  
16  
14  
12  
10  
ENABLE  
20  
18  
8
6
4
2
0
DISABLE  
16  
14  
12  
DISABLE  
-2.5 -2.0 -1.5 -1.0 -0.5  
0
0.5 1.0 1.5 2.0 2.5  
0.1  
1
10  
30  
FREQUENCY (MHz)  
OUTPUT VOLTAGE (V)  
FIGURE 41. CHANNEL SEPARATION vs FREQUENCY  
FIGURE 42. ENABLE/DISABLE TIME vs OUTPUT VOLTAGE  
10  
DISABLE = 0V  
0
R
= 100Ω  
L
1
V
= 5V  
P-P  
IN  
R
= 750Ω  
F
-10  
-20  
-30  
0.1  
0.01  
180  
135  
90  
0.001  
-40  
-50  
-60  
-70  
-80  
45  
0
-45  
-90  
-135  
0.001  
0.01  
0.1  
1
10  
100  
0.1  
1
10  
20  
FREQUENCY (MHz)  
FREQUENCY (MHz)  
FIGURE 44. TRANSIMPEDANCE vs FREQUENCY  
FIGURE 43. DISABLE FEEDTHROUGH vs FREQUENCY  
10  
1
R
= 400Ω  
L
0.1  
180  
135  
0.01  
0.001  
90  
45  
0
-45  
-90  
-135  
0.001  
0.01  
0.1  
1
10  
100  
FREQUENCY (MHz)  
FIGURE 45. TRANSIMPEDENCE vs FREQUENCY  
3550.6  
February 8, 2006  
15  
HA5024  
Die Characteris tics  
DIE DIMENSIONS:  
PASSIVATION:  
2680µm x 2600µm x 483µm  
Type: Nitride  
Thickness: 4kÅ ±0.4kÅ  
METALLIZATION:  
TRANSISTOR COUNT:  
Type: Metal 1: AlCu (1%)  
Thickness: Metal 1: 8kÅ ±0.4kÅ  
248  
Type: Metal 2: AlCu (1%)  
Thickness: Metal 2: 16kÅ ±0.8kÅ  
PROCESS:  
High Frequency Bipolar Dielectric Isolation  
SUBSTRATE POTENTIAL (Powered Up):  
V-  
Metallization Mas k Layout  
HA5024  
-IN1  
OUT1  
1
OUT4  
-IN4  
19  
2
20  
18  
17  
+IN1  
DIS1  
V+  
3
4
+IN4  
DIS4  
V-  
6
15  
DIS2  
+IN2  
7
8
DIS3  
+IN3  
14  
13  
9
10  
11  
12  
-IN2  
OUT2  
OUT3  
-IN3  
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.  
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality  
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without  
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and  
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result  
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see www.intersil.com  
3550.6  
16  
February 8, 2006  

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