HCS166HMSR_技术文档

HCS166MS

Radiation Hardened 8-Bit

Parallel-Input/Serial Output Shift Register

September 1995

Features

Pinouts

16 LEAD CERAMIC DUAL-IN-LINE

METAL SEAL PACKAGE (SBDIP)

MIL-STD-1835 CDIP2-T16, LEAD FINISH C

TOP VIEW

• 3 Micron Radiation Hardened CMOS SOS

• Total Dose 200K RAD (Si)

• SEP Effective LET No Upsets: >100 MEV-cm²/mg

• Single Event Upset (SEU) Immunity < 2 x 10^-9Errors/

Bit-Day (Typ)

• Dose Rate Survivability: >1 x 10¹²RAD (Si)/s

• Dose Rate Upset >10¹⁰RAD s(Si)/s 20ns Pulse

• Latch-Up Free Under Any Conditions

VCC

PE

DS

D0

16

15

14

13

1

2

3

4

5

6

7

8

D1

D7

D2

Q7

D3

12 D6

D5

• Fanout (Over Temperature Range)

- Standard Outputs - 10 LSTTL Loads

• Military Temperature Range: -55^oC to +125^oC

• Signiﬁcant Power Reduction Compared to LSTTL ICs

• DC Operating Voltage Range: 4.5V to 5.5V

CE

11

10 D4

MR

CP

GND

9

• Input Logic Levels

- VIL = 0.3 VCC Max

- VIH = 0.7 VCC Min

16 LEAD CERAMIC METAL SEAL

FLATPACK PACKAGE (FLATPACK)

MIL-STD-1835 CDFP4-F16, LEAD FINISH C

TOP VIEW

• Input Current Levels Ii ≤ 5µA at VOL, VOH

VCC

PE

D7

DS

D0

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

Description

The Intersil HCS166MS is an 8-bit shift register that has fully

synchronous serial or parallel data entry selected by an

active LOW Parallel Enable (PE) input. When the PE is LOW

one setup time before the LOW-to-HIGH clock transition,

parallel data is entered into the register. When PE is HIGH,

data is entered into internal bit position Q0 from Serial Data

Input (DS), and the remaining bits are shifted one place to

the right (Q0 → Q1 → Q2m etc.) with each positive-going

clock transition. For expansion of the register in parallel to

serial converters, the Q7 output is connected to the DS input

of the succeeding stage.

D1

Q7

D6

D2

D3

D5

CE

D4

CP

MR

GND

Ordering Information

The clock input is a gated OR structure which allows one

input to be used as an active LOW Clock Enable (CE) input.

The pin assignment for the CP and CE inputs is arbitrary and

con be reversed for layout convenience. The LOW-to-HIGH

transition of CE input should only take place while the CP is

HIGH for predictable operation.

PART

NUMBER

TEMPERATURE SCREENING

RANGE LEVEL

PACKAGE

o

HCS166DMSR -55 C to +125 C Intersil Class S 16 Lead

Equivalent SBDIP

o

HCS166KMSR -55 C to +125 C Intersil Class S 16 Lead

Equivalent

Ceramic

Flatpack

A LOW on the Master Reset (MR) input overrides all other

inputs and clears the register asynchronously, forcing all bit

positions to a LOW state.

o

HCS166D/

Sample

+25 C

Sample

16 Lead

SBDIP

The HCS166MS utilizes advanced CMOS/SOS technology

to achieve high-speed operation. This device is a member of

radiation hardened, high-speed, CMOS/SOS Logic Family.

o

HCS166K/

Sample

+25 C

Sample

16 Lead

Ceramic

Flatpack

The HCS166MS is supplied in a 16 lead Ceramic ﬂatpack

(K sufﬁx) or a SBDIP Package (D sufﬁx).

o

HCS166HMSR

+25 C

Die

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Spec Number 518758

File Number 2482.2

250

HCS166MS

Functional Diagram

D0

D1

D2

D3

D4

D5

D6

D7

CP

CE

DS

PE

MR

Q7

TRUTH TABLE

INPUTS

PARALLEL

INTERNAL Q STATES

Q0 Q1

MASTER

RESET

PARALLEL

ENABLE

CLOCK

ENABLE

OUTPUT

Q7

CLOCK

SERIAL

D0 - D7

L

X

L

X

L

H

X

L

X

H

L

X

L

Q00

a

L

H

X

Q10

b

Q0

h

a . . . h

H

X

H

Q0n

Q10

Q6n

Q70

L

X

Q00

H = High Level

L = Low Level

X = Immaterial

a . . . h = The level of steady state input at inputs D0 thru D7, respectively.

Q00, Q10, Q70 = The level of Q0, Q1, or Q7, respectively, before the indicated steady

state input conditions were established.

= Transition from low to high level

Q0n, Q6n = the level of Q0 or Q6, respectively, before the most recent transition of the

clock.

Spec Number 518758

251

Speciﬁcations HCS166MS

Absolute Maximum Ratings

Reliability Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V

Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VCC +0.5V

DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA

DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .±25mA

(All Voltage Reference to the VSS Terminal)

Thermal Resistance

SBDIP Package. . . . . . . . . . . . . . . . . . . .

Ceramic Flatpack Package . . . . . . . . . . . 114 C/W

Maximum Package Power Dissipation at +125 C Ambient

SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.68W

Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 0.44W

If device power exceeds package dissipation capability, provide heat

sinking or derate linearly at the following rate:

SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.7mW/ C

Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . 8.8mW/ C

θ

JA

JC

o

73 C/W

24 C/W

o

29 C/W

o

Storage Temperature Range (TSTG) . . . . . . . . . . . -65 C to +150 C

o

Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . . +265 C

o

Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C

o

ESD Classiﬁcation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

o

CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent

damage. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed

under “Electrical Performance Characteristics” are the only conditions recommended for satisfactory device operation.

Operating Conditions

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V

Input Rise and Fall Times at 4.5V VCC (TR, TF) . . . . . . .500ns Max

Input Low Voltage (VIL). . . . . . . . . . . . . . . . . . . 0.0V to 30% of VCC

Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . 70% of VCC to VCC

o

Operating Temperature Range (T ) . . . . . . . . . . . . -55 C to +125 C

A

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

GROUP

A SUB-

LIMITS

(NOTE 1)

PARAMETER

SYMBOL

CONDITIONS

GROUPS

TEMPERATURE

MIN

MAX

UNITS

µA

o

Quiescent Current

ICC

VCC = 5.5V,

VIN = VCC or GND

1

2, 3

1

+25 C

-

40

o

+125 C, -55 C

-

750

µA

o

Output Current

(Sink)

IOL

IOH

VOL

VCC = 4.5V, VIH = 4.5V,

VOUT = 0.4V, VIL = 0V

+25 C

4.8

4.0

-4.8

-4.0

-

mA

V

o

2, 3

1

+125 C, -55 C

-

o

Output Current

(Source)

VCC = 4.5V, VIH = 4.5V,

VOUT = VCC -0.4V,

VIL = 0V

+25 C

o

2, 3

1, 2, 3

+125 C, -55 C

-

o

Output Voltage Low

VCC = 4.5V, VIH = 3.15V,

+25 C, +125 C, -55 C

0.1

IOL = 50µA, VIL = 1.35V

o

VCC = 5.5V, VIH = 3.85V,

IOL = 50µA, VIL = 1.65V

1, 2, 3

+25 C, +125 C, -55 C

-

0.1

V

o

Output Voltage High

VOH

VCC = 4.5V, VIH = 3.15V,

IOH = -50µA, VIL = 1.35V

+25 C, +125 C, -55 C

VCC

-0.1

-

o

VCC = 5.5V, VIH = 3.85V,

IOH = -50µA, VIL = 1.65V

+25 C, +125 C, -55 C

VCC

-0.1

o

Input Leakage

Current

IIN

FN

VCC = 5.5V, VIN = VCC or

GND

1

+25 C

-

±0.5

±5.0

-

µA

-

o

2, 3

+125 C, -55 C

o

Noise Immunity

Functional Test

VCC = 4.5V,

VIH = 0.70(VCC),

VIL = 0.30(VCC), (Note 2)

7, 8A, 8B

+25 C, +125 C, -55 C

NOTES:

1. All voltages reference to device GND.

2. For functional tests, VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.

Spec Number 518758

252

Speciﬁcations HCS166MS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

GROUP

LIMITS

(NOTES 1, 2)

A SUB-

PARAMETER

SYMBOL

CONDITIONS

GROUPS

TEMPERATURE

MIN

MAX

32

UNITS

ns

o

CP or CE to Q7

TPHL

TPLH

VCC = 4.5V

9

+25 C

2

o

10, 11

9

+125 C, -55 C

37

ns

o

MR to Q7

NOTES:

TPHL

VCC = 4.5V

+25 C

31

ns

o

10, 11

+125 C, -55 C

36

ns

1. All voltages referenced to device GND.

2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC.

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS

(NOTE 1)

PARAMETER

SYMBOL

CONDITIONS

TEMPERATURE

MIN

-

MAX

UNITS

pF

ns

o

Capacitance Power Dissipation

CPD

VCC = 5.0V, f = 1MHz

+25 C

65

81

10

15

22

-

o

+125 C, -55 C

-

o

Input Capacitance

CIN

VCC = 5.0V, f = 1MHz

VCC = 4.5V

+25 C

-

o

+125 C

-

o

Output Transition Time

(Figure 1)

TTHL

TTLH

+25 C

-

o

+125 C, -55 C

-

ns

o

Clock Frequency (Figure 1)

MR Pulse Width (Figure 2)

Clock Pulse Width (Figure 1)

fmax

tw

+25 C

30

20

30

16

24

16

24

1

MHz

ns

o

-55 C to +125 C

-

o

+25 C

-

o

-55 C to +125 C

-

ns

o

tw

+25 C

-

ns

o

-55 C to +125 C

-

ns

o

Set-up Time Data and CE to

Clock, (Figure 3, 4)

tSU

tH

+25 C

-

ns

o

-55 C to +125 C

-

ns

o

Hold Time Data to Clock

(Figure 4)

+25 C

-

ns

o

-55 C to +125 C

1

-

ns

o

Removal Time MR to Clock

(Figure 3)

tREM

tSU

tH

+25 C

0

-

ns

o

-55 C to +125 C

0

-

ns

o

Set-up Time PE to CP (Figure 4)

+25 C

29

44

0

-

ns

o

-55 C to +125 C

-

ns

o

Hold Time PE to CP or CE

(Figure 4)

+25 C

-

ns

o

-55 C to +125 C

0

-

ns

NOTE:

1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly

tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics.

Spec Number 518758

253

Speciﬁcations HCS166MS

TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

200K RAD

LIMITS

(NOTES 1, 2)

PARAMETER

Quiescent Current

Output Current (Sink)

SYMBOL

ICC

CONDITIONS

TEMPERATURE

MIN

MAX

0.75

-

UNITS

mA

o

VCC = 5.5V, VIN = VCC or GND

+25 C

-

o

IOL

VCC = 4.5V, VIN = VCC or GND,

VOUT = 0.4V

+25 C

4.0

mA

o

Output Current

(Source)

IOH

VOL

VOH

VCC = 4.5V, VIN = VCC or GND,

VOUT = VCC -0.4V

+25 C

-4.0

-

0.1

-

mA

V

o

Output Voltage Low

Output Voltage High

Input Leakage Current

VCC = 4.5V and 5.5V, VIH = 0.70(VCC),

VIL = 0.30(VCC), IOL = 50µA

+25 C

o

VCC = 4.5V and 5.5V, VIH = 0.70(VCC),

VIL = 0.30(VCC), IOH = -50µA

+25 C

VCC

-0.1

V

o

IIN

FN

VCC = 5.5V, VIN = VCC or GND

+25 C

-

±5

µA

o

Noise Immunity

Functional Test

VCC = 4.5V, VIH = 0.70(VCC),

VIL = 0.30(VCC), (Note 3)

+25 C

-

o

CP or CE to Q7

TPHL

TPLH

TPHL

VCC = 4.5V

+25 C

2

37

36

ns

o

+25 C

o

MR to Q7

NOTES:

+25 C

1. All voltages referenced to device GND.

2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = VCC.

3. For functional tests, VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.

o

TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25 C)

GROUP B

PARAMETER

SUBGROUP

DELTA LIMIT

12µA

ICC

IOL/IOH

5

-15% of 0 Hour

Spec Number 518758

254

Speciﬁcations HCS166MS

TABLE 6. APPLICABLE SUBGROUPS

CONFORMANCE GROUPS

Initial Test (Preburn-In)

METHOD

100%/5004

Sample/5005

GROUP A SUBGROUPS

READ AND RECORD

ICC, IOL/H

1, 7, 9

Interim Test I (Postburn-In)

Interim Test II (Postburn-In)

PDA

ICC, IOL/H

1, 7, 9

1, 7, 9, Deltas

Interim Test III (Postburn-In)

PDA

1, 7, 9

ICC, IOL/H

1, 7, 9, Deltas

Final Test

2, 3, 8A, 8B, 10, 11

1, 2, 3, 7, 8A, 8B, 9, 10, 11

1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas

Group A (Note 1)

Group B

Subgroup B-5

Subgroups 1, 2, 3, 9, 10, 11,

(Note 2)

Subgroup B-6

Sample/5005

1, 7, 9

Group D

NOTES:

1. Alternate Group A testing in accordance with Method 5005 of Mil-Std-883 may be exercised.

2. Table 5 parameters only.

TABLE 7. TOTAL DOSE IRRADIATION

TEST

READ AND RECORD

CONFORMANCE

GROUPS

Group E Subgroup 2

NOTE:

METHOD

PRE RAD

POST RAD

PRE RAD

1, 9

POST RAD

5005

1, 7, 9

Table 4

Table 4 (Note 1)

1. Except FN test which will be performed 100% Go/No-Go.

TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS

OSCILLATOR

OPEN

GROUND

1 - 12, 14 - 15

8

1/2 VCC = 3V ± 0.5V

VCC = 6V ± 0.5V

16

50kHz

25kHz

STATIC I BURN-IN (Note 1)

13

-

STATIC II BURN-IN (Note 1)

13

1 - 7, 9 - 12, 14 - 16

3, 5, 9, 11, 14 - 16

DYNAMIC BURN-IN (Note 2)

-

2, 4, 6, 8, 10, 12

13

7

1

NOTES:

1. Each pin except VCC and GND will have a resistor of 10KΩ ± 5% for static burn-in

2. Each pin except VCC and GND will have a resistor of 1KΩ ± 5% for dynamic burn-in

TABLE 9. IRRADIATION TEST CONNECTIONS

OPEN

GROUND

VCC = 5V ± 0.5V

13

8

1 - 7, 9 - 12, 14 - 16

NOTE: Each pin except VCC and GND will have a resistor of 47KΩ ± 5% for irradiation testing.

Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures.

Spec Number 518758

255

HCS166MS

Intersil Space Level Product Flow - ‘MS’

Wafer Lot Acceptance (All Lots) Method 5007

(Includes SEM)

100% Interim Electrical Test 1 (T1)

100% Delta Calculation (T0-T1)

GAMMA Radiation Veriﬁcation (Each Wafer) Method 1019,

4 Samples/Wafer, 0 Rejects

100% Static Burn-In 2, Condition A or B, 24 hrs. min.,

+125^oC min., Method 1015

100% Nondestructive Bond Pull, Method 2023

Sample - Wire Bond Pull Monitor, Method 2011

Sample - Die Shear Monitor, Method 2019 or 2027

100% Internal Visual Inspection, Method 2010, Condition A

100% Interim Electrical Test 2 (T2)

100% Delta Calculation (T0-T2)

100% PDA 1, Method 5004 (Notes 1and 2)

100% Dynamic Burn-In, Condition D, 240 hrs., +125^oC or

100% Temperature Cycle, Method 1010, Condition C,

10 Cycles

Equivalent, Method 1015

100% Interim Electrical Test 3 (T3)

100% Delta Calculation (T0-T3)

100% Constant Acceleration, Method 2001, Condition per

Method 5004

100% PDA 2, Method 5004 (Note 2)

100% Final Electrical Test

100% PIND, Method 2020, Condition A

100% External Visual

100% Fine/Gross Leak, Method 1014

100% Radiographic, Method 2012 (Note 3)

100% External Visual, Method 2009

Sample - Group A, Method 5005 (Note 4)

100% Data Package Generation (Note 5)

100% Serialization

100% Initial Electrical Test (T0)

100% Static Burn-In 1, Condition A or B, 24 hrs. min.,

+125^oC min., Method 1015

NOTES:

1. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1.

2. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the

failures from subgroup 7.

3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004.

4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005.

5. Data Package Contents:

• Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number,

Quantity).

• Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage.

• GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Speciﬁcation Numbers, Test

equipment, etc. Radiation Read and Record data on ﬁle at Intersil.

• X-Ray report and ﬁlm. Includes penetrometer measurements.

• Screening, Electrical, and Group A attributes (Screening attributes begin after package seal).

• Lot Serial Number Sheet (Good units serial number and lot number).

• Variables Data (All Delta operations). Data is identiﬁed by serial number. Data header includes lot number and date of test.

• The Certiﬁcate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certiﬁcate of Conformance is signed

by an authorized Quality Representative.

Spec Number 518758

256

HCS166MS

AC Timing Diagrams and AC Load Circuit

INPUT

LEVEL

tr

t/f MAX

VS

tf

MR

VS

INPUT

LEVEL

GND

tW

50

VS

tREM

INPUT

LEVEL

GND

tW

VS

tPHL

tPLH

VS

CP

GND

tPHL

VS

Q7

VS

tTHL

tTLH

FIGURE 1. CLOCK PRE-REQUISITE TIMES AND PROPAGA-

TION AND OUTPUT TRANSITION TIMES

FIGURE 2. MASTER RESIT PRE-REQUISITE TIMES AND

PROPAGATION DELAYS.

VALID

INPUT

LEVEL

VALID

INPUT

LEVEL

PE OR CE

DATA

VS

GND

tSU

tH

INPUT

LEVEL

INPUT

LEVEL

VS

GND

CP

GND

FIGURE 3. DATA PRE-REQUISITE TIMES

FIGURE 4. PARALLEL ENABLE OR CLOCK ENABLE PRE-

REQUISITE TIMES

AC VOLTAGE LEVELS

PARAMETER

HCS

4.50

2.25

0

UNITS

DUT

TEST

POINT

VCC

VIH

VS

V

CL

RL

VIL

CL = 50pF

RL = 500Ω

GND

0

FIGURE 5. AC LOAD CIRCUIT

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or speciﬁcations at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate

and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which

may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

Spec Number 518758

257

HCS166MS

Die Characteristics

DIE DIMENSIONS:

94 x 94 mils

METALLIZATION:

Type: AlSi

Metal Thickness: 11kÅ ± 1kÅ

GLASSIVATION:

Type: SiO₂

Thickness: 13kÅ ± 2.6kÅ

WORST CASE CURRENT DENSITY:

< 2.0 x 10⁵A/cm²

BOND PAD SIZE:

100µm x 100µm

4 mils x 4 mils

Metallization Mask Layout

HCS166MS

D1

(3)

D0

(2)

DS

(1)

VCC

(16)

PE

(15)

D2 (4)

D3 (5)

CE (6)

(14) D7

(13) Q7

(12) D6

(7)

(8)

(9)

(10)

D4

(11)

D5

CP

GND

MR

NOTE: The die diagram is a generic plot from a similar HCS device. It is intended to indicate approximate die size and bond pad location.

The mask series for the HCS166 is TA14386A.

Spec Number 518758

258


型号：	HCS166HMSR
厂家：	Intersil
描述：	Radiation Hardened 8-Bit Parallel-Input/Serial Output Shift Register 抗辐射的8位并行输入/串行输出移位寄存器移位寄存器触发器逻辑集成电路
文件：	总9页 (文件大小：229K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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