HD-15531_02_技术文档

TM

HD-15531

March 1997

CMOS Manchester Encoder-Decoder

Features

Description

• Support of MIL-STD-1553

The Intersil HD-15531 is a high performance CMOS device

intended to service the requirements of MIL-STD-1553 and

similar Manchester II encoded, time division multiplexed

serial data protocols. This LSI chip is divided into two sec-

tions, an Encoder and a Decoder. These sections operate

independently of each other, except for the master reset and

word length functions. This circuit provides many of the

requirements of MIL-STD-1553. The Encoder produces the

sync pulse and the parity bit as well as the encoding of the

data bits. The Decoder recognizes the sync pulse and identi-

fies it as well as decoding the data bits and checking parity.

• Data Rate (15531B) . . . . . . . . . . . . . . . .2.5 Megabit/Sec

• Data Rate (15531). . . . . . . . . . . . . . . . .1.25 Megabit/Sec

• Variable Frame Length to 32 Bits

• Sync Identification and Lock-In

• Separate Manchester II Encode, Decode

• Low Operating Power . . . . . . . . . . . . . . . . . 50mW at 5V

The HD-15531 also surpasses the requirements of MIL-

STD-1553 by allowing the word length to be programmable

(from 2 to 28 data bits). A frame consists of three bits for

sync followed by the data word (2 to 28 data bits) followed by

one bit of parity, thus, the frame length will vary from 6 to 32

bit periods. This chip also allows selection of either even or

odd parity for the Encoder and Decoder separately.

Ordering Information

TEMP. RANGE

1.25MBIT

/SEC

2.5MBIT

/SEC

PKG.

NO.

o

PACKAGE

PDIP

( C)

HD3-15531B-9

HD1-15531B-9

HD1-15531B-8

HD1-15531

-40 to 85

-55 to 125

-

E40.6

F40.6

This integrated circuit is fully guaranteed to support the

1MHz data rate of MIL-STD-1553 over both temperature and

voltage. For high speed applications the 15531B will support

a 2.5 Megabit/sec data rate.

CERDIP

HD1-15531-9

HD1-15531-8

DESC

(CERDIP)

5962-

9054901MQA

The HD-15531 can also be used in many party line digital

data communications applications, such as a local area net-

work or an environmental control system driven from a single

twisted pair of fiber optic cable throughout a building.

5962-

9054902MQA

HD1-15531B

-55 to 125

F40.6

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.

FN2961.1

1

HD-15531

Pinout

HD-15531 (CERDIP, PDIP)

TOP VIEW

V

1

2

40

39

38

COUNT C

CC

1

VALID WORD

TAKE DATA’

TAKE DATA

4

3

DATA SYNC

4

37 ENCODER CLK

5

36 COUNT C

3

SERIAL DATA OUT

SYNCHR DATA

6

35 NC

7

SYNCHR DATA SEL

SYNCHR CLK

34

ENCODER SHIFT CLK

8

33 SEND CLK IN

9

DECODER CLK

32

31

30

SEND DATA

10

11

12

SYNCHR CLK SEL

BIPOLAR ZERO IN

BIPOLAR ONE IN

UNIPOLAR DATA IN

DECODER SHIFT CLK

ENCODER PARITY SEL

SYNC SEL

29 ENCODER ENABLE

13

14

15

16

17

18

19

SERIAL DATA IN

28

27

BIPOLAR ONE OUT

26 OUTPUT INHIBIT

TRANSITION SEL

NC

25 BIPOLAR ZERO OUT

24

23

÷ 6 OUT

COMMAND SYNC

DECODER PARITY SEL

DECODER RESET

COUNT C2

22 MASTER RESET

21

COUNT C 20

0

GND

Block Diagrams

ENDODER

GND

V

CC

21

22

33

24

1

MASTER RESET

SEND CLK IN

÷ 6 OUT

OUTPUT

INHIBIT

26

27

25

BIPOLAR

÷ 2

ONE OUT

CHARACTER

FORMER

÷ 6

BIPOLAR

ZERO OUT

ENCODER

CLK

37

BIT

COUNTER

34

28

29

30

31

32

20 40 23 36 39

SEND

DATA

SERIAL

DATA IN

SYNC

SELECT

C

4

0

1

2

3

ENCODER

ENCODER ENCODER

SHIFT

CLK

ENABLE

PARITY

SELECT

2

HD-15531

DECODER

7

8

SYNCHRONOUS

DATA SELECT

SYNCHRONOUS

DATA

13

UNIPOLAR

DATA IN

4

TAKE DATA

DATA

SELECT

GATE

12

11

17

TRANSITION

FINDER

CHARACTER

IDENTIFIER

BIPOLAR

ONE IN

COMMAND SYNC

BIPOLAR

ONE IN

DATA SYNC

5

SERIAL

DATA OUT

9

2

DECODER

CLK

VALID WORD

CLOCK

SELECT

DATA

BIT

RATE

CLK

PARITY

SYNCHRONIZER

16

CHECK

PARITY

SELECT

15

DECODER

CLK SELECT

8

SYNCHRONOUS

CLK

14

DECODER

SHIFT CLK

10

22

SYNCHRONOUS

CLK SELECT

MASTER

RESET

19

3

BIT

COUNTER

DECODER

RESET

TAKE DATA’

20 40 23 36 39

C

4

0

1

2

3

Pin Description

NUMBER TYPE

NAME

SECTION

DESCRIPTION

1

V

Both

Positive supply pin. A 0.1µF decoupling capacitor from V

(pin 1) to GROUND

CC

(pin 21) is recommended.

2

3

O

VALID WORD

TAKE DATA’

Decoder Output high indicates receipt of a valid word, (valid parity and no Manchester

errors).

Decoder A continuous, free running signal provided for host timing or data handling. When

data is present on the bus, this signal will be synchronized to the incoming data

and will be identical to TAKE DATA.

4

O

TAKE DATA

Decoder Output is high during receipt of data after identification of a valid sync pulse and

two valid Manchester bits.

5

6

O

I

SERIAL DATA OUT

Decoder Delivers received data in correct NRZ format.

SYNCHRONOUS

DATA

Decoder Input presents Manchester data directly to character identification logic.

SYNCHRONOUS DATA SELECT must be held high to use this input. If not

used, this pin must be held high.

7

I

SYNCHRONOUS

DATA SELECT

Decoder In high state allows the synchronous data to enter the character identification

logic. Tie this input low for asynchronous data.

8

SYNCHRONOUS

CLOCK

Decoder Input provides externally synchronized clock to the decoder, for use when re-

ceiving synchronous data. This input must be tied high when not in use.

9

DECODER CLOCK

Decoder Input drives the transition finder, and the synchronizer which in turn supplies the

clock to the balance of the decoder. Input a frequency equal to 12X the data rate.

10

11

12

13

SYNCHRONOUS

CLOCK SELCT

Decoder In high state directs the SYNCHRONOUS CLOCK to control the decoder char-

acter identification logic. A low state selects the DECODER CLOCK.

BIPOLAR ZERO IN

BIPOLAR ONE IN

UNIPOLAR DATA IN

Decoder A high input should be applied when the bus is in its negative state. This pin must

be held high when the unipolar input is used.

Decoder A high input should be applied when the bus is in its positive state. This pin must

he held low when the unipolar input is used.

Decoder With pin 11 high and pin 12 low, this pin enters unipolar data into the transition

finder circuit. If not used this input must be held low.

3

HD-15531

Pin Description (Continued)

NUMBER TYPE

NAME

SECTION

DESCRIPTION

14

15

O

DECODER SHIFT

CLOCK

Decoder Output which delivers a frequency (DECODER CLOCK + 1 2), synchronous by

the recovered serial data stream.

I

TRANSITION SE-

LECT

Decoder A high input to this pin causes the transition finder to synchronize on every tran-

sition of input data. A low input causes the transition finder to synchronize only

on mid-bit transitions.

16

17

NC

Blank

Not connected.

O

I

COMMAND SYNC

Decoder Output of a high from this pin occurs during output of decoded data which was

preceded by a Command (or Status) synchronizing character.

18

19

20

DECODER PARITY

SELECT

Decoder An input for parity sense, calling for even parity with input high and odd parity

with input low.

I

DECODER RESET

Decoder A high input to this pin during a rising edge of DECODER SHIFT CLOCK resets

the decoder bit counting logic to a condition ready for a new word.

I

COUNT C0

Both

One of five binary inputs which establish the total bit count to be encoded or de-

coded.

21

22

GROUND

Both

Supply pin.

I

MASTER RESET

A high on this pin clears 2:1 counters in both encoder and decoder, and resets

the ÷ 6 circuit.

23

24

25

I

COUNT C2

Both

See pin 20.

O

÷ 6 OUT

Encoder Output from 6:1 divider which is driven by the ENCODER CLOCK.

BIPOLAR ZERO

OUT

Encoder An active low output designed to drive the zero or negative sense of a bipolar

line driver.

26

27

I

OUTPUT INHIBIT

Encoder A low on this pin forces pin 25 and 27 high, the inactive states.

O

BIPOLAR ONE OUT

Encoder An active low output designed to drive the one or positive sense of a bipolar line

driver.

28

29

I

SERIAL DATA IN

Encoder Accepts a serial data stream at a data rate equal to ENCODER SHIFT CLOCK.

ENCODER ENABLE

Encoder A high on this pin initiates the encode cycle. (Subject to the preceding cycle be-

ing complete).

30

31

I

SYNC SELECT

Encoder Actuates a Command sync for an input high and Data sync for an input low.

Encoder Sets transmit parity odd for a high input, even for a low input.

ENCODER PARITY

SELECT

32

33

34

O

I

SEND DATA

Encoder Is an active high output which enables the external source of serial data.

SEND CLOCK IN

Encoder Clock input at a frequency equal to the data rate X2, usually driven by ÷ 6 output.

O

ENCODER SHIFT

CLOCK

Encoder Output for shifting data into the Encoder. The Encoder samples SDI pin-28 on

the low-to-high transition of ESC.

35

36

37

NC

Blank

Both

Not connected.

See pin 20.

I

COUNT C3

ENCODER CLOCK

Encoder Input to the 6:1 divider, a frequency equal to 12 times the data rate is usually

input here.

38

O

DATA SYNC

Decoder Output of a high from this pin occurs during output of decoded data which was

preceded by a data synchronizing character.

39

40

I

COUNT C4

COUNT C1

Both

See pin 20.

See pill 20.

4

HD-15531

Encoder Operation

The Encoder requires a single clock with a frequency of be clocked into the SERIAL DATA input with every high-to-

twice the desired data rate applied at the SEND CLOCK low transition of the ENCODER SHIFT CLOCK 3 - 4 so it

input. An auxiliary divide by six counter is provided on chip can be sampled on the low-to-high transition. After the sync

which can be utilized to produce the SEND CLOCK by divid- and Manchester II encoded data are transmitted through the

ing the DECODER CLOCK. The frame length is set by pro- BIPOLAR ONE and BIPOLAR ZERO outputs, the Encoder

gramming the COUNT inputs. Parity is selected by adds on an additional bit with the parity for that word 5 . If

programming ENCODER PARITY SELECT high for odd par- ENCODER ENABLE is held high continuously, consecutive

ity or low for even parity.

words will be encoded without an interframe gap.

ENCODER ENABLE must go low by time 5 (as shown) to

prevent a consecutive word from being encoded. At any time

a low on OUTPUT INHIBIT input will force both bipolar out-

puts to a high state but will not affect the Encoder in any

other way.

The Encoder’s cycle begins when ENCODER ENABLE is

high during a falling edge of ENCODER SHIFT CLOCK 1 .

This cycle lasts for one word length or K + 4 ENCODER

SHIFT CLOCK periods, where K is the number of bits to be

sent. At the next low-to-high transition of the ENCODER

SHIFT CLOCK, a high SYNC SELECT input actuates a To abort the Encoder transmission, a positive pulse must be

Command sync or a low will produce a Data sync for the applied at MASTER RESET. Any time after or during this

word 2 . When the Encoder is ready to accept data, the pulse, a low-to-high transition on SEND CLOCK clears the

SEND DATA output will go high for K ENCODER SHIFT internal counters and initializes the Encoder for a new word.

CLOCK periods 4 . During these K periods the data should

TIMING

0

1

2

3

4

5

6

7

N-4

N-3

N-2

N-1

N

SEND CLOCK

ENCODER

SHIFT CLOCK

ENCODER

ENABLE

DON’T CARE

SYNC

SELECT

VALID

SEND

DATA

SERIAL

DATA IN

MSB BIT K-1BIT K-2 BIT K-3 BIT K-4 BIT K-5 BIT 4 BIT 3 BIT 2 BIT 1

BIPOLAR

ONE OUT

1ST HALF 2ND HALF MSB BIT K-1 BIT K-2 BIT K-3 BIT K-4

BIT 4 BIT 3 BIT 2 BIT 1 PARITY

BIPOLAR

ZERO OUT

SYNC

3

MSB BIT K-1 BIT K-2 BIT K-3 BIT K-4

1

2

4

5

FIGURE 1. ENCODER

Decoder Operation

To operate the Decoder asynchronously requires a single OUT on an Encoder through an inverter to Unipolar Data

clock with a frequency of 12 times the desired data rate Input).

applied at the DECODER CLOCK input. To operate the

The Decoder is free running and continuously monitors its

Decoder synchronously requires

a

SYNCHRONOUS

data input lines for a valid sync character and two valid

Manchester data bits to start an output cycle. When a valid

sync is recognized 1 , the type of sync is indicated by a high

level at either COMMAND SYNC or DATA SYNC output. If

the sync character was a command sync the COMMAND

CLOCK at a frequency 2 times the data rate which is syn-

chronized with the data at every high-to-low transition

applied to the SYNCHRONOUS CLK input. The Manchester

II coded data can be presented to the Decoder asynchro-

nously in one of two ways. The BIPOLAR ONE and

BIPOLAR ZERO inputs will accept data from a comparator

sensed transformer coupled bus as specified in Military Spec

1553. The UNIPOLAR DATA input can only accept nonin-

verted Manchester II coded data. (e.g., from BIPOLAR ONE

SYNC output will go high

2 and remain high for K SHIFT

CLOCK periods 3 , where K is the number of bits to be

received. If the sync character was a data sync, the DATA

SYNC output will go high. The TAKE DATA output will go

2

3

while the Decoder is transmit-

high and remain high

-

5

HD-15531

ting the decoded data through SERIAL DATA OUT. The on VALID WORD output 4 indicates a successful reception

decoded data available at SERIAL DATA OUT is in NRZ of a word without any Manchester or parity errors. At this

format. The DECODER SHIFT CLOCK is provided so that time the Decoder is looking for a new sync character to start

the decoded bits can get shifted into an external register on another output sequence. VALID WORD will go low approx-

every low-to-high transition of this clock

DECODER SHIFT CLOCK may adjust its phase up until the goes high, if not reset low sooner by a valid sync and two

time that TAKE DATA goes high. valid Manchester bits as shown 1 .

2 - 3 . Note that imately K + 4 DECODER SHIFT CLOCK periods after it

After all K decoded bits have been transmitted 3 the data is At any time in the above sequence a high input on

checked for parity. A high input on DECODER PARITY DECODER RESET during low-to-high transition of

a

SELECT will set the Decoder to check for even parity or a DECODER SHIFT CLOCK will abort transmission and ini-

low input will set the Decoder to check for odd parity. A high tialize the Decoder to start looking for a new sync character.

TIMING

0

1

2

3

4

5

6

7

8

N-3

N-2

N-1

N

SYNCHRONOUS

CLOCK

DECODER

SHIFT

CLOCK

BIPOLAR

ONE IN

1ST HALF

SYNC

BITK-1

BITK-5

BIT 3 BIT 2 BIT 1 PARITY

2ND HALF

SYNC

BITK-2

BITK-4

MSB

BITK-3

BIPOLAR

ZERO IN

MSB BITK-1 BITK-2 BIT K-3 BITK-4 BITK-5

TAKE DATA

COMMAND

SYNC

DATA SYNC

SERIAL

DATA OUT

UNDEFINED

(MAY BE HIGH FROM PREVIOUS RECEPTION)

MSB BITK-1 BITK-2 BITK-3

BIT 5 BIT 4 BIT 3 BIT 2 BIT 1

VALID WORD

1

2

3

4

FIGURE 2. DECODER

6

HD-15531

Frame Counter

PIN WORD

FRAME LENGTH

(BIT PERIODS)

DATA BITS

C

0

4

3

2

1

2

6

L

H

L

H

3

7

L

H

L

H

L

H

L

4

8

5

9

L

H

L

6

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

L

H

L

7

L

H

L

8

L

H

L

9

L

H

L

10

L

H

L

11

L

H

L

12

L

H

L

13

H

14

L

H

L

15

L

H

L

16

L

H

L

17

L

H

L

18

L

H

L

19

L

H

L

20

L

H

L

21

H

22

L

H

L

23

L

H

L

24

L

H

L

25

H

26

L

H

L

27

28

H

NOTE:

1. The above table demonstrates all possible combinations of frame lengths ranging from 6 to 32 bits. The pin word described here is com-

mon to both the Encoder and Decoder.

7

HD-15531

V

CC

VALID WORD

TAKE DATA

SYNC DATA

COUNT C

1

4

1

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

2

3

4

SYNC DATA

SELECT

DATA SYNC

5

6

7

SYNC

CLOCK

NC

COUNT C

3

8

9

DECODER

CLOCK

ENCODER

PARITY SEL.

10

11

12

13

14

15

16

17

18

19

20

SYNC CLOCK

SELECT

SYNC

SELECT

BIPOLAR

ZERO IN

NC

ENCODER

ENABLE

BIPOLAR

ONE IN

BIPOLAR

ONE OUT

UNIPOLAR

DATA IN

INHIBIT

OUTPUT

TRANSITION

SELECT

BIPOLAR

ZERO OUT

COMMAND

SYNC

A

B

CK

H

A

B

CK

O

SH/LD CK SI

O

SH/LD CK SI

74165

H

DECODER

PARITY SELECT

COUNT C

2

74164

74165

MASTER

RESET

COUNT C

0

PARALLEL OUT

PARALLEL IN

FIGURE 3. HOW TO MAKE OUR MTU LOOK LIKE A MANCHESTER ENCODED UART

Typical Timing Diagrams for a Manchester Encoded UART

ENCODER ENABLE

SYNC SELECT

VALID

PARALLEL IN

P

BIPOLAR ONE OUT

P

BIPOLAR ZERO OUT

SYNC

MSB

LSB PARITY

FIGURE 4. ENCODER TIMING

8

HD-15531

SYNC

MSB

LSB PARITY

P

BIPOLAR ONE IN

BIPOLAR ZERO IN

COMMAND SYNC

VALID

PARALLEL OUT

VALID WORD

FROM PREVIOUS

RECEPTION

FIGURE 5. DECODER TIMING

MIL-STD-1553

The 1553 Standard defines a time division multiplexed data Words, and Data. Terminals respond with Status Words, and

bus for application within aircraft. The bus is defined to be Data. Each word is preceded by a synchronizing pulse, and

bipolar, and encoded in a Manchester II format, so no DC

followed by parity bit, occupying a total of 20µs. The word

component appears on the bus. This allows transformer cou-

formats are shown in Figure 4. The special abbreviations are

pling and excellent isolation among systems and their envi-

as follows:

ronment.

P

Parity, which is defined to be odd, taken across all

17 bits.

The HD-15531 supports the full bipolar configuration,

assuming a bus driver configuration similar to that in

Figure 1. Bipolar inputs from the bus, like Figure 2, are also

accommodated.

R/T

ME

TF

Receive on logical zero, transmit on ONE.

Message Error if logical 1.

The signaling format in MIL-STD-1553 is specified on the

assumption that the network of 32 or fewer terminals are

controlled by a central control unit by means of Command-

Terminal Flag, if set, calls for controller to request

self-test data.

BUS

+

“1”

-

“1” REF

“0” REF

-

“0”

+

FIGURE 6. SIMPLIFIED MIL-STD-1553 DRIVER

FIGURE 7. SIMPLIFIED MIL-STD-1553 RECEIVER

9

HD-15531

COMMAND

SYNC

DATA

SYNC

BIT

PERIOD

LOGICAL ONE DATA

LOGICAL ZERO DATA

FIGURE 8. MIL-STD-1553 CHARACTER FORMATS

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19

COMMAND WORD (FROM CONTROLLER TO TERMINAL)

5

1

5

1

SYNC

TERMINAL

ADDRESS

SUB ADDRESS

/MODE

DATA WORD

COUNT

P

R/T

DATA WORD (SENT EITHER DIRECTION)

1

16

SYNC

DATA WORD

P

STATUS WORD (FROM TERMINAL TO CONTROLLER)

5

1

9

1

SYNC

TERMINAL

ADDRESS

CODE FOR FAILURE MODES

TF

P

FIGURE 9. MIL-STD-1553 WORD FORMATS

NOTE:

1. This page is a summary of MIL-STD-1553 and is not intended to describe the operation of the HD-15531.

10

HD-15531

Absolute Maximum Ratings

Thermal Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V

Input, Output or I/O Voltage . . . . . . . . . . . GND -0.5V to V +0.5V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

Thermal Resistance (Typical)

θ

JA

JC

o

CC

CERDIP Package . . . . . . . . . . . . . . . . . .

PDIP Package . . . . . . . . . . . . . . . . . . . . .

Storage Temperature Range . . . . . . . . . . . . . . . . .-65 C to +150 C

Maximum Junction Temperature

Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C

Plastic Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150 C

35 C/W

9 C/W

o

50 C/W

N/A

o

Operating Conditions

o

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V

Operating Temperature Range (T )

HD-15531-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to +85 C

HD-15531-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to +125 C

Encoder/Decoder Clock Rise Time (TECR, TDCR) . . . . . . .8ns Max

Encoder/Decoder Clock Fall Time (TECF, TDCF) . . . . . . . .8ns Max

A

o

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300 C

o

Die Characteristics

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Gates

Sync. Transition Span (TD2). . . . . . . . . . . 18 TDC Typical, (Note 1)

Short Data Transition Span (TD4). . . . . . . . 6 TDC Typical, (Note 1)

Long Data Transition Span (TD5) . . . . . . . 12 TDC Typical, (Note 1)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

o

DC Electrical Specifications

V

= 5.0V ±10%,

T

= -40 C to +85C (HD-15531-9)

CC

A

o

= -55 C to +125C (HD-15531-8)

A

PARAMETER

Input LOW Voltage

SYMBOL

TEST CONDITIONS

MIN

MAX

0.2 V

UNITS

V

= 4.5V and 5.5V

-

V

IL

CC

Input HIGH Voltage

V

0.7 V

-

IH

CC

Input LOW Clock Voltage

Input HIGH Clock Voltage

Output LOW Voltage

Output HIGH Voltage

Input Leakage Current

Standby Supply Current

V

GND +0.5

V

ILC

V

-0.5

CC

-

0.4

-

V

IHC

V

I

= +1.8mA, V

= 4.5V (Note 2)

-

V

OL

CC

V

= -3.0mA, V

2.4

-1.0

-

V

OH

CC

I

V = V

CC

or GND, V = 5.5V

CC

+1.0

2

µA

mA

I

V

= V

= 5.5V,

CCSB

IN CC

Outputs Open

Operating Power Supply Current

ICCOP

V

= V

CC

= 5.5V, f = 15MHz,

-

10

-

mA

-

IN

Outputs Open

Functional Test

F

(Note 3)

T

NOTES:

1. TDC = Decoder clock period = 1/FDC.

2. Interchanging of force and sense conditions is permitted.

3. Tested as follows: f = 15MHz, V = 70% V , V = 20% V , C = 50pF, V

≥ V /2 and V

CC OL

≤ V /2.

CC

IH

CC IL

CC

L

OH

o

Capacitance T = +25 C, Frequency = 1MHz

A

SYMBOL

PARAMETER

Input Capacitance

Output Capacitance

TYP

25

UNITS

pF

TEST CONDITIONS

All measurements are referenced to device GND

C

IN

OUT

25

pF

11

HD-15531

o

AC Electrical Specifications V = 5V ±10%, T = -40 C to +85 C (HD-15530-9)

CC

A

o

T

= -55 C to +125 C (HD-15530-8)

HD-15531B

HD-15531

SYMBOL

PARAMETER

MIN

MAX

MIN

MAX

UNITS

TEST CONDITIONS (NOTE 2)

ENCODER TIMING

FEC

FESC

FED

TMR

TE1

Encoder Clock Frequency

Send Clock Frequency

Encoder Data Rate

Master Reset Pulse Width

Shift Clock Delay

Serial Data Setup

Serial Data Hold

Enable Setup

-

15

-

30

MHz

ns

V

= 4.5V and 5.5V, C = 50pF

L

CC

2.5

5.0

= 4.5V and 5.5V, C = 50pF

L

-

1.25

-

2.5

= 4.5V and 5.5V, C = 50pF

L

150

-

150

-

= 4.5V and 5.5V, C = 50pF

L

125

80

ns

= 4.5V and 5.5V, C = 50pF

L

TE2

75

90

100

55

150

0

-

50

90

100

55

150

0

-

ns

= 4.5V and 5.5V, C = 50pF

L

TE3

-

ns

= 4.5V and 5.5V, C = 50pF

L

TE4

-

ns

= 4.5V and 5.5V, C = 50pF

L

TE5

Enable Pulse Width

Sync Setup

-

ns

= 4.5V and 5.5V, C = 50pF

L

TE6

-

ns

= 4.5V and 5.5V, C = 50pF

L

TE7

Sync Pulse Width

Send Data Delay

Bipolar Output Delay

Enable Hold

ns

= 4.5V and 5.5V, C = 50pF

L

TE8

50

130

-

50

130

-

ns

= 4.5V and 5.5V, C = 50pF

L

TE9

-

ns

= 4.5V and 5.5V, C = 50pF

L

TE10

TE11

10

95

10

95

ns

= 4.5V and 5.5V, C = 50pF

L

Sync Hold

-

ns

= 4.5V and 5.5V, C = 50pF

L

DECODER TIMING

FDC

FDS

Decoder Clock Frequency

-

15

-

30

MHz

ns

V

= 4.5V and 5.5V, C = 50pF

L

CC

Decoder Sync Clock

2.5

5.0

= 4.5V and 5.5V, C = 50pF

L

FDD

Decoder Data Rate

-

1.25

-

2.5

= 4.5V and 5.5V, C = 50pF

L

TDR

Decoder Reset Pulse Width

Decoder Reset Setup Time

Decoder Reset Hold Time

Master Reset Pulse

150

75

10

150

-

150

75

10

150

-

= 4.5V and 5.5V, C = 50pF

L

TDRS

TDRH

TMR

TD1

ns

= 4.5V and 5.5V, C = 50pF

L

ns

= 4.5V and 5.5V, C = 50pF

L

ns

= 4.5V and 5.5V, C = 50pF

L

Bipolar Data Pulse Width

TDC + 10

(Note 1)

TDC + 10

(Note 1)

ns

= 4.5V and 5.5V, C = 50pF

L

TD3

One Zero Overlap

-

TDC - 10

(Note 1)

-

TDC - 10

(Note 1)

ns

V

= 4.5V and 5.5V, C = 50pF

CC L

TD6

TD7

Sync Delay (ON)

-20

0

110

80

-20

0

110

80

ns

V

= 4.5V and 5.5V, C = 50pF

L

CC

Take Data Delay (ON)

Serial Data Out Delay

Sync Delay (OFF)

= 4.5V and 5.5V, C = 50pF

L

TD8

-

= 4.5V and 5.5V, C = 50pF

L

TD9

0

110

75

0

110

75

= 4.5V and 5.5V, C = 50pF

L

TD10

TD11

TD12

Take Data Delay (OFF)

Valid Word Delay

0

= 4.5V and 5.5V, C = 50pF

L

0

= 4.5V and 5.5V, C = 50pF

L

Sync Clock to Shift Clock

Delay

-

= 4.5V and 5.5V, C = 50pF

L

TD13

Sync Data Setup

75

-

75

-

ns

V

= 4.5V and 5.5V, C = 50pF

CC L

NOTES:

1. TDC = Decoder clock period = 1/FDC.

2. AC Testing as follows: Input levels: V = 70% V , V = 20% V ; Input rise/fall times driven at 1ns/V; Timing Reference

IH CC IL CC

levels: V /2; Output load: C = 50pF.

CC

L

12

HD-15531

Timing Waveforms

SEND CLOCK

T

E1

ENCODER SHIFT CLOCK

SERIAL DATA IN

T

E2

E3

VALID

SEND CLOCK

T

E10

E1

ENCODER SHIFT CLOCK

T

E11

E4

ENCODER ENABLE

SYNC SELECT

T

E5

E6

VALID

T

E7

ENCODER SHIFT CLOCK

SEND DATA

T

E8

SEND CLOCK

T

E9

BIPOLAR ONE OUT OR

BIPOLAR ZERO OUT

FIGURE 10. ENCODER TIMING

13

HD-15531

Timing Waveforms (Continued)

NOTE: UNIPOLAR IN = 0, FOR NEXT DIAGRAMS.

BIT PERIOD

BOI

T

D1

T

D3

D2

D3

T

BZI

D1

T

D2

COMMAND SYNC

T

D1

BOI

BZI

T

D3

D2

D3

T

D1

DATA SYNC

T

D2

T

D1

BOI

BZI

T

D3

T

D3

T

D2

T

D1

T

D4

D5

ONE

ZERO

ONE

NOTE: BIPOLAR ONE IN = 0, BIPOLAR ZERO IN = 1, FOR NEXT DIAGRAMS.

T

D2

UI

COMMAND SYNC

T

D2

DATA SYNC

T

UI

D4

D5

D4

ONE

ZERO

ONE

FIGURE 11. DECODER TIMING

14

HD-15531

Timing Waveforms (Continued)

DECODER SHIFT CLOCK

T

D6

D7

COMMAND/DATA SYNC

TAKE DATA

DECODER SHIFT CLOCK

SERIAL DATA OUT

T

D8

DATA BIT

T

D10

DECODER SHIFT CLOCK

COMMAND/DATA SYNC

T

D9

T

D10

TAKE DATA

T

VALID WORD

D11

DECODER SHIFT CLOCK

DECODER RESET

T

DRS

T

DR

T

DRH

SYNCHRONOUS INPUT (WITH EXTERNAL BIT SYNCHRONIZATION)

SYNCHRONOUS

CLOCK IN

T

D12

DECODER SHIFT

CLOCK

SYNCHRONOUS

CLOCK IN

T

D13

SYNCHRONOUS

DATA IN

MANCHESTER

PHASES

FIGURE 12. DECODER TIMINGS

15

HD-15531

AC Testing Input, Output Waveform

Test Load Circuit

DUT

INPUT

OUTPUT

C

(NOTE 1)

L

V

IH

OH

50%

V

IL

OL

FIGURE 14.

FIGURE 13.

NOTE:

1. Includes stray and jig capacitance.

1. AC Testing: All input signals must switch between V and V ,

IL IH

input rise and fall times are driven at 1ns per volt.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

Sales Office Headquarters

NORTH AMERICA

Intersil Corporation

7585 Irvine Center Drive

Suite 100

Irvine, CA 92618

TEL: (949) 341-7000

FAX: (949) 341-7123

EUROPE

ASIA

Intersil Corporation

2401 Palm Bay Rd.

Palm Bay, FL 32905

TEL: (321) 724-7000

FAX: (321) 724-7946

Intersil Europe Sarl

Ave. William Graisse, 3

1006 Lausanne

Switzerland

TEL: +41 21 6140560

FAX: +41 21 6140579

Unit 1804 18/F Guangdong Water Building

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TEL: +852 2723 6339

FAX: +852 2730 1433

16


型号：	HD-15531_02
厂家：	Intersil
描述：	CMOS Manchester Encoder-Decoder CMOS曼彻斯特编码器，解码器解码器编码器
文件：	总16页 (文件大小：267K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HD-15531_02 [INTERSIL]

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