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HD3-6408-9Z [INTERSIL]

CMOS Asynchronous Serial Manchester Adapter (ASMA); CMOS异步串行曼彻斯特适配器（ ASMA ）
HD3-6408-9Z
型号： HD3-6408-9Z
厂家： Intersil    Intersil
描述：

CMOS Asynchronous Serial Manchester Adapter (ASMA)
CMOS异步串行曼彻斯特适配器（ ASMA ）

电信集成电路 光电二极管 编码器
文件： 总11页 (文件大小：237K)
中文：  中文翻译
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HD-6408  
®
Data Sheet  
March 7, 2006  
FN2952.2  
CMOS Asynchronous Serial Manchester  
Adapter (ASMA)  
Features  
• Low Bit Error Rate  
The HD-6408 is a CMOS/LSI Manchester Encoder/Decoder  
for creating a very high speed asynchronous serial data bus.  
The Encoder converts serial NRZ data (typically from a shift  
register) to Manchester II encoded data, adding a sync pulse  
and parity bit. The Decoder recognizes this sync pulse and  
identifies it as a Command Sync or a Data Sync. The data is  
then decoded and shifted out in NRZ code (typically into a  
shift register). Finally, the parity bit is checked. If there were  
no Manchester or parity errors the Decoder responds with a  
valid word signal. The Decoder puts the Manchester code to  
full use to provide clock recovery and excellent noise  
immunity at these very high speeds.  
• Data Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1MBit/s  
• Sync Identification and Lock-In  
• Clock Recovery  
• Manchester II Encoder, Decoder  
• Separate Encode and Decode  
• Low Operating Power. . . . . . . . . . . . . . . . . . . 50mW at 5V  
• Single Power Supply  
• 24 Ld Package  
• Pb-Free Plus Anneal Available (RoHS Compliant)  
The HD-6408 can be used in many commercial applications  
such as security systems, environmental control systems,  
serial data links and many others. It utilizes a single 12 x  
clock and achieves data rates of up to one million bits per  
second with a very minimum overhead of only 4 bits out of  
20, leaving 16 bits for data.  
Ordering Information  
TEMP.  
PART  
PART  
RANGE  
(°C)  
PKG.  
NO.  
NUMBER  
MARKING  
PACKAGE  
HD3-6408-9 HD3-6408-9 -40 to +85 24 Ld PDIP  
E24.6  
E24.6  
Pinout  
HD3-6408-9Z HD3-6408-9Z -40 to +85 24 Ld PDIP*  
(Note)  
(Pb-Free)  
HD-6408 (DIP)  
TOP VIEW  
HD1-6408-9 HD1-6408-9 -40 to +85 24 Ld CERDIP F24.6  
NOTE: Intersil Pb-free plus anneal products employ special Pb-free  
material sets; molding compounds/die attach materials and 100%  
matte tin plate termination finish, which are RoHS compliant and  
compatible with both SnPb and Pb-free soldering operations. Intersil  
Pb-free products are MSL classified at Pb-free peak reflow  
temperatures that meet or exceed the Pb-free requirements of  
IPC/JEDEC J STD-020.  
*Pb-free PDIPs can be used for through hole wave solder processing  
only. They are not intended for use in Reflow solder processing  
applications.  
VW  
ESC  
TD  
1
2
3
4
5
6
7
8
9
24  
V
CC  
23 EC  
22 SCI  
21 SD  
20 SS  
SDO  
DC  
BZI  
19 EE  
BOI  
UDI  
DSC  
18 SDI  
17 BOO  
16 OI  
d
CDS 10  
DR 11  
15 BZO  
14 DBS  
13 MR  
GND 12  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
Copyright Intersil Americas Inc. 2006. All Rights Reserved  
1
All other trademarks mentioned are the property of their respective owners.  
HD-6408  
Block Diagrams  
ENCODER  
DECODER  
11  
1
DR  
BIT COUNTER  
23  
14  
13  
EC  
DBS  
MR  
÷ 6  
VALID  
WORD  
TEST  
VALID  
WORD  
LATCH  
PARITY  
CHECK  
VW  
TD  
22  
BIT COUNTER  
SCI  
ESC  
SD  
÷ 2  
CIRCUIT  
2
3
10  
SYNC  
LATCH  
CDS  
21  
COUNT  
RESET  
DECODER  
20  
18  
5
SS  
4
SYNC  
NRZ  
OUTPUT  
PORT  
CLOCK  
DC  
CHARACTER  
IDENTIFIER  
SDO  
SYNCHRO-  
NIZER  
9
15  
16  
17  
BZO  
OI  
DSC  
CHARACTER  
FORMER  
PARITY  
DATA  
BOO  
6
7
BZI  
19  
SDI  
TRANSITION  
FINDER  
BOI  
EE  
8
UDI  
FN2952.2  
March 7, 2006  
2
HD-6408  
Pin Description  
PIN  
TYPE  
SYMBOL  
VW  
SECTION  
Decoder  
Encoder  
DESCRIPTION  
1
O
Output high indicates receipt of a VALID WORD.  
2
O
ESC  
ENCODER SHIFT CLOCK is an output for shifting data into the Encoder. The  
Encoder samples SDI on the low-to-high transition of ESC.  
3
O
TD  
Decoder  
TAKE DATA output is high during receipt of data after identification of a sync pulse  
and two valid Manchester data bits.  
4
5
O
I
SDO  
DC  
Decoder  
Decoder  
SERIAL DATA OUT delivers received data in correct NRZ format.  
DECODER CLOCK input drives the transition finder, and the synchronizer which in  
turn supplies the clock to the balance of the Decoder. Input a frequency equal to  
12X the data rate.  
6
7
I
I
BZI  
BOI  
Decoder  
Decoder  
Decoder  
Decoder  
Decoder  
A high input should be applied to BIPOLAR ZERO IN when the bus is in its negative  
state. This pin must be held high when the Unipolar input is used.  
A high input should be applied to BIPOLAR ONE IN when the bus is in its positive  
state, this pin must be held low when the Unipolar input is used.  
8
I
UDI  
With pin 6 high and pin 7 low, this pin enters UNIPOLAR DATA IN to the transition  
finder circuit. If not used this input must be held low.  
9
O
O
DSC  
CDS  
DECODER SHIFT CLOCK output delivers a frequency (DECODER CLOCK ³÷ 12),  
synchronized by the recovered serial data stream.  
10  
COMMAND/DATA SYNC output high occurs during output of decoded data which  
was preceded by a Command synchronizing character. A low output indicates a  
Data synchronizing character.  
11  
I
DR  
Decoder  
A high input to DECODER RESET during a rising edge of DECODER SHIFT  
CLOCK resets the decoder bit counting logic to a condition ready for a new word.  
12  
13  
I
I
GND  
MR  
Both  
Both  
GROUND supply pin.  
A high on MASTER RESET clears the 2:1 counters in both the encoder and  
decoder and the ³ ÷ 6 counter.  
14  
15  
O
O
DBS  
BZO  
Encoder  
Encoder  
DIVIDE BY SIX is an output from 6:1 divider which is driven by the ENCODER  
CLOCK.  
BIPOLAR ZERO OUT is a active low output designed to drive the zero or negative  
sense of a bipolar line driver.  
16  
17  
I
OI  
Encoder  
Encoder  
A low on OUTPUT INHIBIT forces pin 15 and 17 high, their inactive states.  
O
BOO  
BIPOLAR ONE OUT is an active low output designed to drive the one or positive  
sense of a bipolar line driver.  
18  
19  
20  
21  
I
I
SDI  
EE  
SS  
SD  
Encoder  
Encoder  
Encoder  
Encoder  
SERIAL DATA IN accepts a serial data stream at a data rate equal to ENCODER  
SHIFT CLOCK.  
A high on ENCODER ENABLE initiates the encode cycle. (Subject to the preceding  
cycle being completed).  
I
SYNC SELECT actuates a Command sync for an input high and data sync for an  
input low.  
O
SEND DATA is an active high output which enables the external source of serial  
data.  
22  
23  
24  
I
I
I
SCI  
EC  
Encoder  
Encoder  
Both  
SEND CLOCK IN is 2X the Encoder data rate.  
ENCODER CLOCK is the input to the 6:1 divider.  
V
V
is the +5V power supply pin. A 0.1µF decoupling capacitor from V (pin 24)  
CC  
CC  
CC  
to GND (pin 12) is recommended.  
FN2952.2  
3
March 7, 2006  
HD-6408  
- (4). After the sync and Manchester II encoded data are  
Encoder Operation  
transmitted through the BOO and BZO outputs, the Encoder  
adds on an additional bit which is the (odd) parity for that  
word (5). If ENCODER ENABLE is held high continuously,  
consecutive words will be encoded without an interframe  
gap. ENCODER ENABLE must go low by time (5) as shown  
to prevent a consecutive word from being encoded. At any  
time a low on OI will force both bipolar outputs to a high state  
but will not affect the Encoder in any other way.  
The Encoder requires a single clock with a frequency of  
twice the desired data rate applied at the SClock input. An  
auxiliary divide by six counter is provided on chip which can  
be utilized to produce the SClock by dividing the DClock.  
The Encoder’s cycle begins when EE is high during a falling  
edge of ESC (1). This cycle lasts for one word length or  
twenty ESC periods. At the next low-to-high transition of the  
ESC, a high at SS input actuates a Command sync or a low  
will produce a Data sync for that word (2). When the Encoder  
is ready to accept data, the SD output will go high and  
remain high for sixteen ESC periods (3) - (4).  
To Abort the Encoder transmission a positive pulse must be  
applied at MR. Any time after or during this pulse, a low-to-  
high transition on SCI clears the internal counters and  
initializes the Encoder for a new word.  
During these sixteen periods the data should be clocked into  
the SD Input with every high-to-low transition of the ESC (3)  
0
1
2
3
4
5
6
7
15  
16  
17  
18  
19  
TIMING  
SCI  
ESC  
EE  
DON’T CARE  
SS  
VALID  
DON’T CARE  
SD  
SDI  
15  
1ST HALF 2ND HALF 15  
14  
13  
12  
11  
10  
3
2
1
0
BOO  
14  
14  
13  
13  
12  
12  
11  
11  
3
3
2
2
1
1
0
0
4
P
P
BZO  
SYNC  
SYNC  
3
15  
1
2
5
FN2952.2  
4
March 7, 2006  
HD-6408  
The decoded data available at SDO is in a NRZ format. The  
Decoder Operation  
DSC is provided so that the decoded bits can be shifted into  
an external register on every low-to-high transition of this  
clock (2) - (3). Note that DECODER SHIFT CLOCK may  
adjust its phase up until the time that TAKE DATA goes high.  
The Decoder requires a single clock with a frequency of 12  
times the desired data rate applied at the DClock input. The  
Manchester II coded data can be presented to the Decoder  
in one of two ways. The BOI and BZI inputs will accept data  
from a differential output comparator. The UDI input can only  
accept noninverted Manchester II coded data (e.g. from  
BOO of an Encoder through an inverter to UDI).  
After all sixteen decoded bits have been transmitted (3) the  
data is checked for odd parity. A high on VW output (4)  
indicates a successful reception of a word without any  
Manchester or parity errors. At this time the Decoder is  
looking for a new sync character to start another output  
sequence. VALID WORD will go low approximately 20  
DECODER SHIFT CLOCK periods after it goes high if not  
reset low sooner by a valid sync and two valid Manchester  
bits as shown (1).  
The Decoder is free running and continuously monitors its  
data input lines for a valid sync character and two valid  
Manchester data bits to start an output cycle. When a valid  
sync is recognized (1), the type of sync is indicated by the  
CDS output. If the sync character was a command, this  
output will go high (2) and remain high for sixteen DSC  
periods (3), otherwise it will remain low. The TD output will  
go high and remain high (2) - (3) while the Decoder is  
transmitting the decoded data through SDO.  
At any time in the above sequence a high input on DR during  
a low-to-high transition of DSC will abort transmission and  
initialize the Decoder to start looking for a new sync character.  
0
1
2
3
4
5
6
7
8
16  
17  
18  
19  
TIMING  
DSC  
1ST HALF2ND HALF  
15  
15  
14  
14  
13  
13  
12  
12  
11  
11  
10  
10  
2
2
1
1
0
0
P
P
BOI  
BZI  
SYNC  
SYNC  
TD  
CDS  
SDO  
VW  
UNDEFINED  
15  
14  
13  
12  
4
3
2
1
0
FROM PREVIOUS RECEPTION  
1
2
3
4
FN2952.2  
5
March 7, 2006  
HD-6408  
Absolute Maximum Ratings  
Thermal Information  
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V  
Thermal Resistance (Typical)  
CERDIP Package. . . . . . . . . . . . . . . . .  
PDIP Package* . . . . . . . . . . . . . . . . . .  
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C  
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C  
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300°C  
*Pb-free PDIPs can be used for through hole wave solder  
processing only. They are not intended for use in Reflow solder  
processing applications.  
θ
(°C/W)  
θ
(°C/W)  
JA  
JC  
Input, Output or I/O Voltage . . . . . . . . . . . .GND -0.3V to V  
+0.3V  
CC  
50  
60  
11  
N/A  
Gate Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 Gates  
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1  
Operating Conditions  
Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V  
Operating Temperature Range  
HD-6408-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C  
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the  
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.  
DC Electrical Specifications  
V
= 5.0V ±10%, T = -40°C to +85°C  
CC A  
SYMBOL  
PARAMETER  
Logical “1” Input Voltage  
Logical “0” Input Voltage  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
V
70% V  
-
-
-
V
V
IH  
CC  
V
20% V  
-
-
IL  
CC  
V
Logical “1” Input Voltage (Clock)  
Logical “0” Input Voltage (Clock)  
Input Leakage  
V
-0.5  
CC  
-
-
V
IHC  
V
-
GND +0.5  
-
V
ILC  
II  
V
= V  
or GND, DIP Pins  
CC  
-1.0  
+1.0  
µA  
IN  
5-8, 11, 13, 16, 18, 19, 20, 22, 23  
V
Logical “1” Output Voltage  
Logical “0” Output Voltage  
Supply Current Standby  
I
I
= -3mA  
2.4  
-
-
V
V
OH  
OH  
V
= 1.8mA  
-
-
-
-
0.4  
2
OL  
OL  
I
V
V
= V  
= 5.5V Outputs Open  
0.5  
8.0  
mA  
mA  
CCSB  
CCOP  
IN  
CC  
= 5.5V, f = 15MHz  
I
Supply Current Operating (Note 1)  
10.0  
CC  
NOTE:  
1. Guaranteed but not 100% tested.  
AC Electrical Specifications  
V
= 5.0V ±10%, T = -40°C to +85°C  
CC A  
SYMBOL  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
ENCODER TIMING  
(1)  
(2)  
F
F
T
T
F
T
T
T
T
T
T
T
T
T
T
Encoder Clock Frequency  
Send Clock Frequency  
Encoder Clock Rise Time  
Encoder Clock Fall Time  
Data Rate  
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
= 50pF  
0
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
12  
MHz  
MHz  
ns  
EC  
ESC  
ECR  
ECF  
ED  
MR  
E1  
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
= 50pF  
= 50pF  
= 50pF  
= 50pF  
= 50pF  
= 50pF  
= 50pF  
= 50pF  
= 50pF  
= 50pF  
= 50pF  
= 50pF  
= 50pF  
= 50pF  
2.0  
(3)  
-
8
(4)  
-
8
ns  
(5)  
0
1.0  
MHz  
ns  
(6)  
Master Reset Pulse Width  
Shift Clock Delay  
150  
-
-
(7)  
125  
ns  
(8)  
Serial Data Setup  
Serial Data Hold  
75  
75  
90  
100  
55  
150  
0
-
ns  
E2  
(9)  
-
ns  
E3  
(10)  
(11)  
(12)  
(13)  
(14)  
(15)  
Enable Setup  
-
-
ns  
E4  
Enable Pulse Width  
Sync Setup  
ns  
E5  
-
ns  
E6  
Sync Pulse Width  
Send Data Delay  
-
ns  
E7  
50  
130  
ns  
E8  
Bipolar Output Delay  
-
ns  
E9  
FN2952.2  
March 7, 2006  
6
HD-6408  
AC Electrical Specifications  
V
= 5.0V ±10%, T = -40°C to +85°C (Continued)  
CC  
A
SYMBOL  
PARAMETER  
TEST CONDITIONS  
MIN  
10  
TYP  
MAX  
UNITS  
ns  
(16)  
(17)  
T
Enable Hold  
Sync Hold  
C
C
= 50pF  
= 50pF  
-
-
-
-
E10  
E11  
L
L
T
95  
ns  
DECODER TIMING  
(18)  
(19)  
(20)  
(21)  
(22)  
(23)  
(24)  
(25)  
(26)  
(27)  
(28)  
(29)  
(30)  
(31)  
(32)  
(33)  
(34)  
(35)  
(36)  
NOTE:  
F
T
T
F
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
Decoder Clock Frequency  
Decoder Clock Rise Time  
Decoder Clock Fall Time  
Data Rate  
C
C
C
C
C
C
C
C
= 50pF  
= 50pF  
= 50pF  
= 50pF  
= 50pF  
= 50pF  
= 50pF  
= 50pF  
0
-
-
-
-
-
-
-
-
-
-
12  
MHz  
ns  
ns  
MHz  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
DC  
DCR  
DCF  
DD  
DR  
DRS  
DRH  
MR  
D1  
L
L
L
L
L
L
L
L
8
-
8
0
1.0  
Decoder Reset Pulse Width  
Decoder Reset Setup Time  
Decoder Reset Hold Time  
Master Reset Pulse Width  
Bipolar Data Pulse Width  
Sync Transition Span  
One Zero Overlap  
150  
75  
10  
150  
-
-
-
-
-
-
Note 2, C = 50pF  
T
+10  
DC  
L
Note 2, C = 50pF  
-
-
18T  
DC  
D2  
L
Note 2, C = 50pF  
-
T
-10  
D3  
L
DC  
-
Short Data Transition Span  
Long Data Transition Span  
Sync Delay (ON)  
Note 2, C = 50pF  
-
6T  
DC  
D4  
L
Note 2, C = 50pF  
-
12T  
DC  
-
D5  
L
C
C
C
C
C
C
= 50pF  
= 50pF  
= 50pF  
= 50pF  
= 50pF  
= 50pF  
-20  
0
-
-
-
-
-
-
-
110  
D6  
L
L
L
L
L
L
Take Data Delay (ON)  
Serial Data Out Delay  
Sync Delay (OFF)  
110  
80  
ns  
ns  
ns  
ns  
ns  
D7  
D8  
0
0
0
110  
110  
110  
D9  
Take Data Delay (OFF)  
Valid Word Delay  
D10  
D11  
1
2. T  
= Decoder Clock Period = /F . (These parameters are guaranteed but not 100% tested).  
DC  
DC  
Capacitance  
T = +25°C  
A
SYMBOL  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
pF  
C
Input Capacitance  
Output Capacitance  
FREQ = 1MHz, all measurements  
are referenced to device GND  
-
-
15  
15  
-
-
IN  
C
pF  
O
FN2952.2  
March 7, 2006  
7
HD-6408  
AC Tes ting Input, Output Waveform  
INPUT  
V
V
V
IH  
OH  
OL  
50%  
50%  
V
IL  
NOTE: AC Testing: All input signals must switch between V and V . Input rise and fall times are driven at 1ns per volt.  
IL IH  
Encoder Timing  
(7)  
TE1  
SCI  
ESC  
SDI  
(9)  
TE3  
VALID  
VALID  
TE2  
(8)  
SC  
ESC  
EE  
(7)  
TE1  
TE10 (16)  
(10)  
TE4  
(17)  
TE11  
(11)  
TE5  
(12)  
TE6  
SS  
VALID  
TE7  
(13)  
ESC  
SD  
(14)  
TE8  
SC  
(15)  
TE9  
BOO OR BZO  
FN2952.2  
8
March 7, 2006  
HD-6408  
Decoder Timing  
NOTE: UI = 0, FOR NEXT DIAGRAMS  
BIT PERIOD  
BIT PERIOD  
BIT PERIOD  
BOI  
BZI  
T
D1  
(26)  
T
T
T
(28)  
D3  
(28)  
D3  
D2  
(27)  
T
D1  
(26)  
T
D2  
(27)  
COMMAND SYNC  
T
D1  
(28)  
BOI  
BZI  
(26)  
T
T
T
D3  
(27)  
D2  
D3  
(28)  
T
D1  
(26)  
DATA SYNC  
T
D2  
(27)  
T
T
D1  
D1  
BOI  
BZI  
(26)  
T
(26)  
(28)  
D3  
T
T
(28)  
T
T
D3  
(28)  
(28)  
D3  
D3  
D3  
(28)  
T
D1  
(26)  
T
T
(30)  
T
(30)  
D5  
T
D4  
D5  
D4  
(29)  
(29)  
ONE  
ZERO  
ONE  
NOTE: BOI = 0, BZI = 1 FOR NEXT DIAGRAMS  
(27)  
(27)  
T
T
D2  
D2  
UI  
UI  
COMMAND SYNC  
(27)  
(27)  
T
T
D2  
D2  
DATA SYNC  
(29)  
(29)  
(30)  
T
(29)  
T
T
T
T
UI  
D4  
D5  
D5  
D4  
D4  
(30)  
ONE  
ZERO  
ONE  
ONE  
FN2952.2  
9
March 7, 2006  
HD-6408  
Decoder Timing (Continued)  
DSC  
(31)  
D6  
T
CDS  
TD  
T
D7  
(32)  
(33)  
DSC  
SDO  
T
D8  
DATA BIT  
DSC  
(34)  
T
D9  
CDS  
TD  
(35)  
T
D10  
(36) T  
D11  
VW  
DSC  
(23) T  
DRS  
(22) T  
DR  
DR  
(24) T  
DRH  
FN2952.2  
10  
March 7, 2006  
HD-6408  
Decoder Timing (Continued)  
DSC  
CDS  
TD  
(31)  
D6  
T
T
(32)  
D7  
(33)  
D8  
DSC  
SDO  
T
DATA BIT  
DSC  
CDS  
TD  
(34)  
T
D8  
(35)  
D10  
T
(36) T  
VW  
D11  
DSC  
DR  
(23) T  
CRS  
(22) T  
DR  
(24) T  
DRH  
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.  
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality  
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without  
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and  
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result  
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see www.intersil.com  
FN2952.2  
11  
March 7, 2006  

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