HFA1113EVAL [INTERSIL]
850MHz, Low Distortion, Output Limiting, Programmable Gain, Buffer Amplifier; 为850MHz ，低失真，输出限制，可编程增益缓冲放大器
| 型号： | HFA1113EVAL |
| 厂家： | 
Intersil |
| 描述： | 850MHz, Low Distortion, Output Limiting, Programmable Gain, Buffer Amplifier |
| 文件： | 总17页 (文件大小：254K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HFA1113
Data Sheet
February 1999
File Number 1342.5
850MHz, Low Distortion, Output Limiting,
Programmable Gain, Buffer Amplifier
Features
• User Programmable Output Voltage Limiting
The HFA1113 is a high speed Buffer featuring user
• User Programmable For Closed-Loop Gains of +1, -1 or
+2 Without Use of External Resistors
programmable gain and output limiting coupled with ultra
high speed performance. This buffer is the ideal choice for
high frequency applications requiring output limiting,
especially those needing ultra fast overload recovery times.
The output limiting function allows the designer to set the
maximum positive and negative output levels, thereby
protecting later stages from damage or input saturation. The
sub-nanosecond overdrive recovery time quickly returns the
amplifier to linear operation following an overdrive condition.
• Wide -3dB Bandwidth. . . . . . . . . . . . . . . . . . . . . .850MHz
• Excellent Gain Flatness (to 100MHz). . . . . . . . . . ±0.07dB
• Low Differential Gain and Phase . . . 0.02%/0.04 Degrees
• Low Distortion (HD3, 30MHz). . . . . . . . . . . . . . . . . -73dBc
• Very Fast Slew Rate . . . . . . . . . . . . . . . . . . . . . 2400V/µs
• Fast Settling Time (0.1%). . . . . . . . . . . . . . . . . . . . . 13ns
• High Output Current . . . . . . . . . . . . . . . . . . . . . . . . .60mA
• Excellent Gain Accuracy . . . . . . . . . . . . . . . . . . . 0.99V/V
• Overdrive Recovery . . . . . . . . . . . . . . . . . . . . . . . . . <1ns
• Standard Operational Amplifier Pinout
A unique feature of the pinout allows the user to select a
voltage gain of +1, -1, or +2, without the use of any external
components, as described in the “Application Information”
section. Compatibility with existing op amp pinouts provides
flexibility to upgrade low gain amplifiers, while decreasing
component count. Unlike most buffers, the standard pinout
provides an upgrade path should a higher closed loop gain
be needed at a future date.
Applications
Component and composite video systems will also benefit
from this buffer’s performance, as indicated by the excellent
gain flatness, and 0.02%/0.04 Degree Differential
• RF/IF Processors
• Driving Flash A/D Converters
• High-Speed Communications
• Impedance Transformation
• Line Driving
Gain/Phase specifications (R = 150Ω).
L
For Military product, refer to the HFA1113/883 data sheet.
Ordering Information
• Video Switching and Routing
• Radar Systems
PART NUMBER
(BRAND)
TEMP.
RANGE ( C)
PKG.
NO.
o
PACKAGE
8 Ld SOIC
• Medical Imaging Systems
HFA1113IB
(H1113I)
-40 to 85
M8.15
Pin Descriptions
HFA11XXEVAL
DIP Evaluation Board For High Speed Op Amps
PIN
NAME
NC
NUMBER
DESCRIPTION
No Connection
Pinout
HFA1113
(SOIC)
TOP VIEW
1
2
3
4
5
6
7
8
-IN
Inverting Input
Non-Inverting Input
Negative Supply
Lower Output Limit
Output
+IN
V-
300
NC
1
2
3
4
8
7
6
5
V
H
300
-IN
+IN
V-
V+
V
L
-
+
OUT
V+
OUT
Positive Supply
Upper Output Limit
V
L
V
H
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1
HFA1113
Absolute Maximum Ratings
Thermal Information
o
Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Thermal Resistance (Typical, Note 1)
θ
( C/W)
JA
SUPPLY
Voltage at V or V Terminal . . . . . . . . . . . . . . (V+) + 2V to (V-) - 2V
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
158
o
H
L
Maximum Junction Temperature (Plastic Package) . . . . . . . .150 C
o
o
Output Current (50% Duty Cycle) . . . . . . . . . . . . . . . . . . . . . . 60mA
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C
o
Operating Conditions
(SOIC - Lead Tips Only)
o
o
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
Electrical Specifications
V
= ±5V, A = +1, R = 100Ω, Unless Otherwise Specified
SUPPLY V L
TEMP.
o
PARAMETER
INPUT CHARACTERISTICS
Output Offset Voltage
TEST CONDITIONS
( C)
MIN
TYP
MAX
UNITS
25
Full
Full
25
-
8
-
25
mV
mV
-
35
o
Output Offset Voltage Drift
PSRR
-
39
35
-
10
45
-
-
µV/ C
-
dB
dB
Full
25
-
Input Noise Voltage (Note 3)
+Input Noise Current (Note 3)
Non-Inverting Input Bias Current
100kHz
100kHz
9
-
-
nV/√Hz
pA/√Hz
µA
25
-
37
25
-
25
-
40
65
-
Full
25
-
µA
Non-Inverting Input Resistance
25
240
-
50
300
2
kΩ
Inverting Input Resistance (Note 2)
Input Capacitance
25
360
-
Ω
25
pF
Input Common Mode Range
TRANSFER CHARACTERISTICS
Gain
Full
±2.5
±2.8
-
V
A
= +1, V = +2V
IN
25
Full
25
0.980
0.975
1.96
1.95
-
0.990
-
1.020
1.025
2.04
2.05
-
V/V
V/V
V/V
V/V
%
V
A
= +2, V = +1V
IN
1.98
-
V
Full
25
DC Non-Linearity (Note 3)
OUTPUT CHARACTERISTICS
Output Voltage (Note 3)
A
= +2, ±2V Full Scale
0.02
V
A
= -1
25
Full
±3.0
±2.5
50
±3.3
±3.0
60
-
-
-
-
-
V
V
V
Output Current (Note 3)
R
= 50Ω
25, 85
-40
mA
mA
Ω
L
35
50
Closed Loop Output Impedance
DC, A = +2
25
-
0.3
V
POWER SUPPLY CHARACTERISTICS
Supply Voltage Range
Full
25
±4.5
-
21
-
±5.5
26
V
Supply Current (Note 3)
-
-
mA
mA
Full
33
2
HFA1113
Electrical Specifications
V
= ±5V, A = +1, R = 100Ω, Unless Otherwise Specified (Continued)
SUPPLY
V
L
TEMP.
o
PARAMETER
AC CHARACTERISTICS
-3dB Bandwidth
TEST CONDITIONS
( C)
MIN
TYP
MAX
UNITS
A
= -1
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
450
800
850
-
MHz
MHz
MHz
V/µs
V/µs
V/µs
MHz
MHz
MHz
dB
V
(V
OUT
= 0.2V
, Notes 2, 3)
P-P
A
= +1
= +2
= -1
= +1
= +2
= -1
= +1
= +2
= -1
= +1
= +2
= -1
= +1
= +2
= -1
= +2
= -1
= +1
= +2
= -1
= +1
= +2
= -1
= +1
= +2
= -1
= +1
= +2
= -1
= +1
= +2
= -1
= +1
= +2
= -1
= +1
= +2
500
-
V
A
350
550
-
V
Slew Rate
(V = 5V
A
1500
2400
1500
1900
300
-
V
, Note 2)
P-P
OUT
A
800
-
V
A
1100
-
V
Full Power Bandwidth
(V = 5V , Note 3)
A
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
OUT P-P
A
150
-
V
A
220
-
V
Gain Flatness
(to 30MHz, Notes 2, 3)
A
±0.02
±0.1
±0.015
±0.05
±0.2
±0.036
±0.10
±0.07
±0.13
±0.83
±0.05
-52
-
V
A
-
dB
V
A
±0.04
dB
V
Gain Flatness
(to 50MHz, Notes 2, 3)
A
-
dB
V
A
-
dB
V
A
±0.08
dB
V
Gain Flatness
(to 100MHz, Notes 2, 3)
A
-
dB
V
A
±0.22
dB
V
Linear Phase Deviation
(to 100MHz, Note 3)
A
-
Degrees
Degrees
Degrees
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
V
A
-
V
A
-
V
2nd Harmonic Distortion
A
-
V
(30MHz, V
OUT
= 2V
, Notes 2, 3)
, Notes 2, 3)
, Notes 2, 3)
, Notes 2, 3)
P-P
A
-57
-
V
A
-52
-45
V
3rd Harmonic Distortion
(30MHz, V = 2V
A
-71
-
V
OUT
P-P
A
-73
-
V
A
-72
-65
V
2nd Harmonic Distortion
(50MHz, V = 2V
A
-47
-
V
OUT
P-P
A
-53
-
V
A
-47
-40
V
3rd Harmonic Distortion
(50MHz, V = 2V
A
-63
-
V
OUT
P-P
A
-68
-
-55
-
V
A
-65
V
2nd Harmonic Distortion
(100MHz, V = 2V , Notes 2, 3)
A
-41
V
OUT P-P
A
-50
-
V
A
-42
-35
-
V
3rd Harmonic Distortion
(100MHz, V = 2V
A
-55
V
, Notes 2, 3)
OUT P-P
A
-49
-
V
A
-62
-45
V
3
HFA1113
Electrical Specifications
V
= ±5V, A = +1, R = 100Ω, Unless Otherwise Specified (Continued)
SUPPLY
V
L
TEMP.
o
PARAMETER
TEST CONDITIONS
100MHz
( C)
MIN
TYP
28
MAX
UNITS
dBm
dBm
dBm
dBm
dB
3rd Order Intercept
(A = +2, Note 3)
V
25
25
25
25
25
25
25
-
-
-
-
-
-
-
-
-
-
-
-
-
-
300MHz
100MHz
300MHz
40MHz
13
1dB Compression
(A = +2, Note 3)
V
19
12
Reverse Isolation
-70
-60
-32
(S , Note 3)
12
100MHz
600MHz
dB
dB
TRANSIENT CHARACTERISTICS
Rise Time
A
= -1
= +1
= +2
= -1
= +1
= +2
= -1
= +1
= +2
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
500
480
700
0.82
1.06
1.00
12
800
ps
V
(V
OUT
= 0.5V Step, Note 2)
A
750
ps
V
A
1000
ps
V
Rise Time
(V = 2V Step)
A
-
-
ns
V
OUT
A
ns
V
A
-
ns
V
Overshoot
(V = 0.5V Step,
A
30
65
20
20
33
-
%
V
OUT
A
45
%
V
Input t /t = 200ps, Notes 2, 3, 4)
R F
A
6
%
ns
V
0.1% Settling Time (Note 3)
0.05% Settling Time
Differential Gain
V
= 2V to 0V
13
OUT
V
= 2V to 0V
20
ns
OUT
A
= +1, 3.58MHz, R = 150Ω
0.03
0.02
0.05
0.04
%
V
L
A
= +2, 3.58MHz, R = 150Ω
-
%
V
L
Differential Phase
A
= +1, 3.58MHz, R = 150Ω
-
Degrees
Degrees
V
L
A
= +2, 3.58MHz, R = 150Ω
-
V
L
OUTPUT LIMITING CHARACTERISTICS
A = +2, V = +1V, V = -1V, Unless Otherwise Specified
V H L
Clamp Accuracy (Note 3)
V
= ±1.6V, A = -1
25
Full
25
-
-
-
-
-
±100
±150
mV
mV
%
IN
V
-
7
±200
Clamp Overshoot
V
V
= ±1V, Input t /t = 500ps
-
1.5
-
IN
IN
R F
Overdrive Recovery Time (Note 3)
Negative Clamp Range
= ±1V
25
0.75
ns
V
25
-5.0 to
+2.0
Positive Clamp Range
25
-
-2.0 to
+5.0
-
V
Clamp Input Bias Current (Note 3)
25
Full
25
-
-
-
50
-
200
300
-
µA
µA
Clamp Input Bandwidth (Note 3)
NOTES:
V
or V = 100mV
P-P
500
MHz
H
L
2. This parameter is not tested. The limits are guaranteed based on lab characterization, and reflect lot-to-lot variation.
3. See Typical Performance Curves for more information.
4. Overshoot decreases as input transition times increase, especially for A = +1. Please refer to Typical Performance Curves.
V
4
HFA1113
avoided by placing a resistor (R ) in series with the output
prior to the capacitance.
Application Information
S
Closed Loop Gain Selection
Figure 1 details starting points for the selection of this
The HFA1113 features a novel design which allows the user
to select from three closed loop gains, without any external
components. The result is a more flexible product, fewer part
types in inventory, and more efficient use of board space.
resistor. The points on the curve indicate the R and C
S
L
combinations for the optimum bandwidth, stability, and
settling time, but experimental fine tuning is recommended.
Picking a point above or to the right of the curve yields an
overdamped response, while points below or left of the curve
indicate areas of underdamped performance.
This “buffer” operates in closed loop gains of -1, +1, or +2,
and gain selection is accomplished via connections to the
±Inputs. Applying the input signal to +IN and floating -IN
selects a gain of +1, while grounding -IN selects a gain of
+2. A gain of -1 is obtained by applying the input signal to
-IN with +IN grounded.
R
and C form a low pass network at the output, thus
L
S
limiting system bandwidth well below the amplifier bandwidth
of 850MHz. By decreasing R as C increases (as illustrated
S
L
in the curves), the maximum bandwidth is obtained without
sacrificing stability. Even so, bandwidth does decrease as
you move to the right along the curve. For example, at
The table below summarizes these connections:
CONNECTIONS
A = +1, R = 50Ω, C = 30pF, the overall bandwidth is
V
S
L
limited to 300MHz, and bandwidth drops to 100MHz at
+INPUT
(PIN 3)
-INPUT
(PIN 2)
GAIN (A
)
A = +1, R = 5Ω, C = 340pF.
CL
V
S
L
-1
+1
+2
GND
Input
Input
Input
NC (Floating)
GND
50
45
40
35
30
25
20
15
10
5
A
= +1
V
PC Board Layout
The frequency response of this amplifier depends greatly on
the amount of care taken in designing the PC board. The
use of low inductance components such as chip
resistors and chip capacitors is strongly recommended,
while a solid ground plane is a must!
A
= +2
40
Attention should be given to decoupling the power supplies.
A large value (10µF) tantalum in parallel with a small value
chip (0.1µF) capacitor works well in most cases.
V
0
0
80 120 160 200 240 280 320 360 400
LOAD CAPACITANCE (pF)
Terminated microstrip signal lines are recommended at the
input and output of the device. Capacitance directly on the
output must be minimized, or isolated as discussed in the
next section.
FIGURE 1. RECOMMENDED SERIES RESISTOR vs LOAD
CAPACITANCE
For unity gain applications, care must also be taken to
minimize the capacitance to ground seen by the amplifier’s
inverting input. At higher frequencies this capacitance will
tend to short the -INPUT to GND, resulting in a closed loop
gain which increases with frequency. This will cause
excessive high frequency peaking and potentially other
problems as well.
Evaluation Board
The performance of the HFA1113 may be evaluated using
the HFA11XX Evaluation Board, slightly modified as follows:
1. Remove the 500Ω feedback resistor (R ), and leave the
2
connection open.
2. a. For A = +1 evaluation, remove the 500Ω gain setting
V
resistor (R ), and leave pin 2 floating.
1
An example of a good high frequency layout is the
Evaluation Board shown in Figure 3.
b. For A = +2, replace the 500Ω gain setting resistor with
V
a 0Ω resistor to GND.
The modified schematic and layout of the board are shown
in Figures 2 and 3.
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly
terminated transmission line will degrade the amplifier’s
phase margin resulting in frequency response peaking and
possible oscillations. In most cases, the oscillation can be
To order evaluation boards (part number HFA11XXEVAL),
please contact your local sales office.
NOTE: The SOIC version may be evaluated in the DIP board by
using a SOIC-to-DIP adapter such as Aries Electronics Part Number
08-350000-10.
5
HFA1113
.
between the positive and negative inputs. This buffer forces
-IN to track +IN, and sets up a slewing current of:
∞ (A = +1)
V
OR 0Ω (A = +2)
V
V
H
(V - V
)/R + V /R
F G
R
1
-IN OUT -IN
1
2
3
4
8
7
6
5
This current is mirrored onto the high impedance node (Z) by
-Q , where it is converted to a voltage and fed to the
output via another unity gain buffer. If no clamping is utilized,
the high impedance node may swing within the limits defined
0.1µF
50Ω
10µF
+5V
50Ω
Q
X3 X4
IN
OUT
V
L
by Q and Q . Note that when the output reaches its
P4 N4
0µF
0.1µF
GND
quiescent value, the current flowing through -IN is reduced to
GND
-5V
only that small current (-I
the final voltage.
) required to keep the output at
BIAS
FIGURE 2. MODIFIED EVALUATION BOARD SCHEMATIC
TOP LAYOUT
Tracing the path from V to Z illustrates the effect of the
H
clamp voltage on the high impedance node. V decreases
H
by 2V (Q and Q ) to set up the base voltage on Q
BE N6 P6
.
P5
V+
V
H
50K
(30K
FOR V )
Q
Q
P3
P4
Z
1
L
+IN
Q
N2
R
1
OUT
V-
V+
V
L
Q
P1
V-
V+
I
CLAMP
GND
+IN
+1
200Ω
V
H
Q
N1
Q
N6
Q
N5
BOTTOM LAYOUT
Q
P2
Q
P6
Q
P5
Q
Q
N4
N3
V
-IN
V-
300Ω
R
= 300Ω
R
F
G
(INTERNAL)
(INTERNAL)
V
OUT
-IN
FIGURE 4. HFA1113 SIMPLIFIED V CLAMP CIRCUITRY
H
Q
begins to conduct whenever the high impedance node
FIGURE 3. EVALUATION BOARD LAYOUT
P5
reaches a voltage equal to Q ’s base voltage + 2V (Q
P5 BE
P5
Limiting Operation
and Q ). Thus, Q clamps node Z whenever Z reaches
N5 P5
V . R provides a pull-up network to ensure functionality
H
1
General
with the clamp inputs floating. A similar description applies to
The HFA1113 features user programmable output clamps to
limit output voltage excursions. Clamping action is obtained
the symmetrical low clamp circuitry controlled by V .
L
When the output is clamped, the negative input continues to
by applying voltages to the V and V terminals (pins 8 and
H
L
source a slewing current (I
) in an attempt to force the
CLAMP
5) of the amplifier. V sets the upper output limit, while V
H
L
output to the quiescent voltage defined by the input. Q
must sink this current while clamping, because the -IN
current is always mirrored onto the high impedance node.
The clamping current is calculated as:
P5
sets the lower clamp level. If the amplifier tries to drive the
output above V , or below V , the clamp circuitry limits the
H
L
output voltage at V or V (± the clamp accuracy),
H
L
respectively. The low input bias currents of the clamp pins
allow them to be driven by simple resistive divider circuits, or
active elements such as amplifiers or DACs.
I
= (V - V
)/300Ω + V /R .
-IN
CLAMP
-IN OUT CLAMPED
G
As an example, a unity gain circuit with V = 2V, and V = 1V,
IN
H
Clamp Circuitry
would have I
= (2V - 1V)/300Ω + 2V/∞ = 3.33mA
CLAMP
(R = ∞ because -IN is floated for unity gain applications).
Figure 4 shows a simplified schematic of the HFA1113 input
G
stage, and the high clamp (V ) circuitry. As with all current
Note that I
will increase by I
when the output is
CLAMP
H
CC
clamp limited.
feedback amplifiers, there is a unity gain buffer (Q - Q
X1
)
X2
6
HFA1113
restrictions indicated in the specifications. For example, the
HFA1113 could be limited to ECL output levels by setting
= -0.8V and V = -1.8V. V and V may be connected to
the same voltage (GND for instance) but the result won’t be
in a DC output voltage from an AC input signal. A
Clamp Accuracy
The clamped output voltage will not be exactly equal to the
V
H
L
H
L
voltage applied to V or V . Offset errors, mostly due to V
H
L
BE
mismatches, necessitate a clamp accuracy parameter which
is found in the device specifications. Clamp accuracy is a
function of the clamping conditions. Referring again to
Figure 4, it can be seen that one component of clamp
accuracy is the VBE mismatch between the Q transistors,
and the Q transistors. If the transistors always ran at the
X5
150mV - 200mV AC signal will still be present at the output.
Recovery from Overdrive
X6
The output voltage remains at the clamp level as long as the
overdrive condition remains. When the input voltage drops
same current level there would be no V mismatch, and no
contribution to the inaccuracy. The Q transistors are
X6
BE
below the overdrive level (V ) the amplifier will
/A
CLAMP VCL
return to linear operation. A time delay, known as the
Overdrive Recovery Time, is required for this resumption of
linear operation. The plots of “Unclamped Performance” and
“Clamped Performance” (Figures 41 and 42) highlight the
HFA1113’s subnanosecond recovery time. The difference
between the unclamped and clamped propagation delays is
the overdrive recovery time. The appropriate propagation
delays are 8.0ns for the unclamped pulse, and 8.8ns for the
clamped (2X overdrive) pulse yielding an overdrive recovery
time of 800ps. The measurement uses the 90% point of the
output transition to ensure that linear operation has
biased at a constant current, but as described earlier, the
current through Q is equivalent to I
. V increases
increases, causing the clamped output voltage to
X5 CLAMP BE
as I
CLAMP
increase as well. I
is a function of the overdrive level
CLAMP
(A
x V - V
), so clamp accuracy
VCL
IN
OUT CLAMPED
degrades as the overdrive increases. As an example, the
specified accuracy of ±100mV (A = -1, V = 1V) for a 1.6X
V
H
overdrive degrades to ±240mV for a 3X (200%) overdrive, as
shown in Figure 43.
Consideration must also be given to the fact that the clamp
voltages have an affect on amplifier linearity. The
resumed. Note: The propagation delay illustrated is
“Nonlinearity Near Clamp Voltage” curve, Figure 48,
illustrates the impact of several clamp levels on linearity.
dominated by the fixturing. The delta shown is accurate, but
the true HFA1113 propagation delay is 500ps.
Overdrive recovery time is also a function of the overdrive
level. Figure 47 details the overdrive recovery time for
various clamp and overdrive levels.
Clamp Range
Unlike some competitor devices, both V and V have
usable ranges that cross 0V. While V must be more positive
H
L
H
than V , both may be positive or negative, within the range
L
o
Typical Performance Curves
V
= ±5V, T = 25 C, R = 100Ω, Unless Otherwise Specified
SUPPLY A L
200
2.0
1.5
1.0
0.5
0
A
= +2
A = +2
V
V
150
100
50
0
-50
-0.5
-1.0
-1.5
-2.0
-100
-150
-200
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 5. SMALL SIGNAL PULSE RESPONSE
FIGURE 6. LARGE SIGNAL PULSE RESPONSE
7
HFA1113
o
Typical Performance Curves
V
= ±5V, T = 25 C, R = 100Ω, Unless Otherwise Specified (Continued)
SUPPLY
A
L
200
2.0
1.5
1.0
0.5
0
A
= +1
A
= +1
V
V
150
100
50
0
-50
-0.5
-1.0
-1.5
-2.0
-100
-150
-200
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 7. SMALL SIGNAL PULSE RESPONSE
FIGURE 8. LARGE SIGNAL PULSE RESPONSE
200
2.0
1.5
1.0
0.5
0
A
= -1
A
= -1
V
V
150
100
50
0
-0.5
-1.0
-1.5
-2.0
-50
-100
-150
-200
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 9. SMALL SIGNAL PULSE RESPONSE
FIGURE 10. LARGE SIGNAL PULSE RESPONSE
6
3
V
= 200mV
A
= +2, V = 200mV
OUT P-P
OUT
P-P
V
A
= +1
V
9
GAIN
GAIN
0
6
3
0
A
A
= -1
V
-3
-6
-9
= +2
R
R
R
= 50Ω
= 100Ω
= 1kΩ
V
L
L
L
PHASE
0
-90
A
= +2
= -1
V
PHASE
A
V
-180
-270
-360
0
A
= +1
V
-90
R
R
R
= 100Ω
= 50Ω
= 1kΩ
L
L
L
-180
-270
-360
0.3
1
10
FREQUENCY (MHz)
100
1000
0.3
1
10
FREQUENCY (MHz)
100
1000
FIGURE 11. FREQUENCY RESPONSE
FIGURE 12. FREQUENCY RESPONSE FOR VARIOUS LOAD
RESISTORS
8
HFA1113
o
Typical Performance Curves
V
= ±5V, T = 25 C, R = 100Ω, Unless Otherwise Specified (Continued)
SUPPLY
A
L
6
6
3
A
= +1, V = 200mV
OUT P-P
A
= -1, V = 200mV
OUT P-P
V
R
= 1kΩ
V
L
3
0
GAIN
GAIN
0
R
R
= 100Ω
= 50Ω
R
= 1kΩ
L
L
L
-3
-6
-9
-3
-6
-9
R
= 100Ω
L
R
= 50Ω
L
PHASE
PHASE
R
= 100Ω
L
180
90
0
-90
R
= 100Ω
= 50Ω
= 1kΩ
100
L
L
L
0
-180
-270
-360
R
R
= 50Ω
= 1kΩ
R
R
L
-90
-180
L
0.3
1
10
FREQUENCY (MHz)
100
1000
0.3
1
10
1000
FREQUENCY (MHz)
FIGURE 13. FREQUENCY RESPONSE FOR VARIOUS LOAD
RESISTORS
FIGURE 14. FREQUENCY RESPONSE FOR VARIOUS LOAD
RESISTORS
12
6
A
= +2
A
= +1
V
V
1V
3
0
9
6
3
0
P-P
GAIN
GAIN
V
= 4V
P-P
OUT
4.0V
P-P
2.5V
-3
-6
V
= 2.5V
P-P
OUT
P-P
V
= 1V
P-P
OUT
PHASE
PHASE
0
0
-90
-90
V
= 4V
OUT
P-P
-180
-270
-360
4.0V
-180
-270
-360
P-P
P-P
P-P
V
= 2.5V
OUT
P-P
2.5V
1V
V
= 1V
P-P
OUT
0.3
1
10
FREQUENCY (MHz)
100
1000
0.3
1
10
FREQUENCY (MHz)
100
1000
FIGURE15. FREQUENCYRESPONSEFORVARIOUSOUTPUT
VOLTAGES
FIGURE16. FREQUENCYRESPONSEFORVARIOUSOUTPUT
VOLTAGES
15
6
V = 5V
OUT P-P
A
= -1
V
= 2.5V
= 4V
V
OUT
P-P
12
9
3
0
V
GAIN
OUT
P-P
V
= 1V
P-P
OUT
-3
-6
6
3
PHASE
180
90
0
A
= -1
= +2
= +1
V
-3
-6
A
V
V
= 4V
P-P
OUT
0
A
V
= 2.5V
P-P
V
OUT
-9
-12
-15
-90
-180
V
= 1V
P-P
OUT
0.3
1
10
FREQUENCY (MHz)
100
1000
0.3
1
10
FREQUENCY (MHz)
100
1000
FIGURE17. FREQUENCYRESPONSEFORVARIOUSOUTPUT
VOLTAGES
FIGURE 18. FULL POWER BANDWIDTH
9
HFA1113
o
Typical Performance Curves
V
= ±5V, T = 25 C, R = 100Ω, Unless Otherwise Specified (Continued)
SUPPLY
A
L
900
0.35
0.30
0.25
0.20
0.15
0.10
0.05
A
= +1
V
850
800
750
700
650
600
550
500
A
= -1
V
A
= -1
A
= +1
V
V
0
-0.05
-0.10
-0.15
A
= +2
V
A
= +2
V
-50
-25
0
25
50
75
100
125
1
10
100
o
TEMPERATURE ( C)
FREQUENCY (MHz)
FIGURE 19. -3dB BANDWIDTH vs TEMPERATURE
FIGURE 20. GAIN FLATNESS
4
3
A
= +2, V = 2V
OUT
V
0.6
0.4
2
1
A
= -1
V
0.2
0.1
0
0
-1
-2
-3
-4
-5
-6
-0.1
A
= +2
V
-0.2
A
= +1
V
-0.4
-0.6
-2
3
8
13
18
23
28 33
38
43
48
0
15
30
45
60
75
90
105 120 135 150
FREQUENCY (MHz)
TIME (ns)
FIGURE 21. DEVIATION FROM LINEAR PHASE
FIGURE 22. SETTLING RESPONSE
235
-24
-30
-36
-42
-48
-54
-60
-66
-72
-78
-84
180
90
45
0
A
= +1
PHASE
GAIN
V
A
= +1
V
A
= -1
V
-24
-30
-36
-42
-48
-54
-60
A
= +2
V
A
= +2
V
A
= +2
= -1
A
= -1
A
V
V
V
A
= -1
V
A
= +2
20
A
= -1
V
V
40 60
80 100 120 140 160 180 200
FREQUENCY (MHz)
0
100 190 280 370 460 550 640 730 820 910 1000
FREQUENCY (MHz)
FIGURE 23. LOW FREQUENCY REVERSE ISOLATION (S
)
FIGURE 24. HIGH FREQUENCY REVERSE ISOLATION (S )
12
12
10
HFA1113
o
Typical Performance Curves
V
= ±5V, T = 25 C, R = 100Ω, Unless Otherwise Specified (Continued)
SUPPLY
A
L
30
20
10
0
20
18
2 - TONE
A
= -1
V
16
14
12
10
8
A
= -1
V
A = +2
V
A
= +2
V
A
= +1
V
A
= +1
6
V
4
2
0
100
200
300
400
100
200
300
FREQUENCY (MHz)
400
500
FREQUENCY (MHz)
FIGURE 25. 1dB GAIN COMPRESSION vs FREQUENCY
FIGURE 26. THIRD ORDER INTERMODULATION INTERCEPT
vs FREQUENCY
-20
-20
A
= +2
A
= +2
V
V
-30
-40
-50
-60
-70
-80
-90
-100
-30
-40
-50
-60
-70
-80
-90
-100
30MHz
50MHz
100MHz
30MHz
50MHz
6
100MHz
3
-6
-3
0
3
6
9
12
15
-6
-3
0
9
12
15
18
OUTPUT POWER (dBm)
OUTPUT POWER (dBm)
FIGURE 27. SECOND HARMONIC DISTORTION vs P
FIGURE 28. THIRD HARMONIC DISTORTION vs P
OUT
OUT
-20
-30
-40
-20
A
= +1
A
= +1
V
V
-30
-40
-50
-60
-70
-80
-50
-60
-70
-80
30MHz
50MHz
100MHz
100MHz
30MHz
6
50MHz
3
-90
-90
-100
-100
-6
-3
0
3
6
9
12
15
-6
-3
0
9
12
15
OUTPUT POWER (dBm)
OUTPUT POWER (dBm)
FIGURE 29. SECOND HARMONIC DISTORTION vs P
FIGURE 30. THIRD HARMONIC DISTORTION vs P
OUT
OUT
11
HFA1113
o
Typical Performance Curves
V
= ±5V, T = 25 C, R = 100Ω, Unless Otherwise Specified (Continued)
SUPPLY
A
L
-20
-20
-30
-40
A
= -1
A
= -1
V
V
-30
-40
-50
-60
-50
-60
30MHz
-70
-70
50MHz
100MHz
-80
-80
30MHz
50MHz
100MHz
0
-90
-90
-100
-100
-6
-3
3
6
9
12
15
-6
-3
0
3
6
9
12
15
OUTPUT POWER (dBm)
OUTPUT POWER (dBm)
FIGURE 31. SECOND HARMONIC DISTORTION vs P
FIGURE 32. THIRD HARMONIC DISTORTION vs P
OUT
OUT
0.04
0.02
0
60
V
= 0.5V
OUT
50
40
30
20
A
= +1
V
-0.02
-0.04
A
= -1
V
10
0
A
= +2
V
100
300
500
700
900
1100
1300
-3.0
-2.0
-1.0
0
1.0
2.0
3.0
INPUT VOLTAGE (V)
INPUT RISE TIME (ps)
FIGURE 33. INTEGRAL LINEARITY ERROR
FIGURE 34. OVERSHOOT vs INPUT RISE TIME
60
50
40
30
20
60
50
40
30
20
10
0
V
= 1V
OUT
V
= 2V
OUT
A
= +1
V
A
= +1
= -1
V
A
V
A
= +2
V
A
= -1
V
10
0
A
= +2
V
100
300
500
700
900
1100
1300
100
300
500
700
900
1100
1300
INPUT RISE TIME (ps)
INPUT RISE TIME (ps)
FIGURE 35. OVERSHOOT vs INPUT RISE TIME
FIGURE 36. OVERSHOOT vs INPUT RISE TIME
12
HFA1113
o
Typical Performance Curves
V
= ±5V, T = 25 C, R = 100Ω, Unless Otherwise Specified (Continued)
SUPPLY
A
L
22
21
20
19
18
17
16
15
14
13
12
11
10
9
25
24
23
22
21
20
19
18
17
16
15
8
7
6
5
5
6
7
8
9
10
-50
-25
0
25
50
75
100 125
TOTAL SUPPLY VOLTAGE (V+ - V-, V)
o
TEMPERATURE ( C)
FIGURE 37. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 38. SUPPLY CURRENT vs TEMPERATURE
3.6
50
40
30
20
10
0
130
A
= -1
V
3.5
3.4
3.3
3.2
3.1
+V
OUT
(R = 50Ω)
L
110
90
70
50
30
+V
OUT
(R = 100Ω)
L
|-V
OUT
| (R = 100Ω)
L
3.0
2.9
E
NI
2.8
2.7
2.6
|-V
OUT
| (R = 50Ω)
L
I
NI
-50
-25
0
25
50
o
75
100
125
0.1
1
10
100
TEMPERATURE ( C)
FREQUENCY (kHz)
FIGURE 39. OUTPUT VOLTAGE vs TEMPERATURE
FIGURE 40. INPUT NOISE CHARACTERISTICS
A
= +2
V
IN
0V TO
0.5V
IN
0V TO
1V
A
= +2
V
OUT
0V TO
1V
OUT
0V TO
1V
TIME (20ns/DIV.)
TIME (20ns/DIV.)
FIGURE 41. UNCLAMPED PERFORMANCE
FIGURE 42. CLAMPED PERFORMANCE
13
HFA1113
o
Typical Performance Curves
V
= ±5V, T = 25 C, R = 100Ω, Unless Otherwise Specified (Continued)
SUPPLY
A
L
350
250
200
150
100
50
A
= ±1
A = ±1
V
V
V
= -500mV
L
300
250
200
150
100
50
V
= 500mV
H
V
= -1V
L
V
V
= 1V
= 2V
H
V
= -2V
H
L
V
= 100mV
H
V
= -100mV
L
0
0
100
200
300
400
500
0
0
100
200
300
400
500
OVERDRIVE (% OF V )
OVERDRIVE (% OF V )
H
L
FIGURE 43. V CLAMP ACCURACY vs OVERDRIVE
FIGURE 44. V CLAMP ACCURACY vs OVERDRIVE
L
H
400
300
200
100
0
250
200
150
100
50
A
= ±2
V
A
= +2
V
= -1V
V
L
V
= 1V
H
V
= -500mV
L
V
= 2V
H
V
= -2V
L
V
= 500mV
H
V
= 100mV
H
V
= -100mV
L
0
0
100
200
300
400
500
0
100
200
300
400
500
OVERDRIVE (% OF V )
OVERDRIVE (% OF V )
H
L
FIGURE 45. V CLAMP ACCURACY vs OVERDRIVE
FIGURE 46. V CLAMP ACCURACY vs OVERDRIVE
L
H
3500
20
A
= -1
V
15
10
5
3000
2500
2000
1500
1000
500
V
= -3V
V
= -2V
V = -1V
L
L
L
V
= 2V
H
0
-5
V
= 1V
H
V
= 2V
V = 3V
H
V
H
= 1V
H
-10
-15
-20
V
= 0.5V
H
V
= 0.1V
H
0
100
-3
-2
-1
0
1
2
3
200
300
400
500
A
x V (V)
IN
OVERDRIVE LEVEL (% OF CLAMP LEVEL)
V
FIGURE 47. OVERDRIVE RECOVERY vs OVERDRIVE
FIGURE 48. NON-LINEARITY NEAR CLAMP VOLTAGE
14
HFA1113
o
Typical Performance Curves
V
= ±5V, T = 25 C, R = 100Ω, Unless Otherwise Specified (Continued)
SUPPLY
A
L
140
130
120
110
100
90
V
= 1V, V = -1V
L
H
A
= -1, V = ±1.6V
= 1V, V = -1V
L
V
IN
V
130
120
110
100
90
H
V
H
V
L
80
70
60
V
H
V
L
50
80
40
70
60
30
20
-75
-25
75
125
-50
0
25
50
100
150
-75
-25
75
125
-50
0
25
50
100
150
o
o
TEMPERATURE ( C)
TEMPERATURE ( C)
FIGURE 49. CLAMP ACCURACY vs TEMPERATURE
FIGURE 50. CLAMP BIAS CURRENT vs TEMPERATURE
6
6
V
= 300mV
P-P
L
V
= 300mV
P-P
H
3
0
3
0
-3
-3
-6
-6
V
V
= 600mV
L
L
P-P
V
= 600mV
H
P-P
P-P
-9
-9
= 1.2V
P-P
V
= 1.2V
H
-12
-12
1
10
100
FREQUENCY (MHz)
1000
1
10
100
FREQUENCY (MHz)
1000
FIGURE 52. V CLAMP INPUT BANDWIDTH
FIGURE 51. V CLAMP INPUT BANDWIDTH
H
L
15
HFA1113
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
63 mils x 44 mils x 19 mils
Type: Nitride
1600µm x 1130µm x 483µm
Thickness: 4kÅ ±0.5kÅ
METALLIZATION:
TRANSISTOR COUNT:
Type: Metal 1: AICu(2%)/TiW
Thickness: Metal 1: 8kÅ ±0.4kÅ
Type: Metal 2: AICu(2%)
52
SUBSTRATE POTENTIAL (POWERED UP):
Floating (Recommend Connection to V-)
Thickness: Metal 2: 16kÅ ±0.8kÅ
Metallization Mask Layout
HFA1113
NC
+IN
V-
V
L
-IN
V
H
NC
V+
OUT
16
HFA1113
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
N
INDEX
AREA
0.25(0.010)
M
B M
H
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
NOTES
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
1
2
3
L
-
9
SEATING PLANE
A
0.0075
0.1890
0.1497
0.0098
0.1968
0.1574
-
-A-
o
h x 45
D
3
4
-C-
α
0.050 BSC
1.27 BSC
-
e
A1
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
C
B
0.10(0.004)
5
0.25(0.010) M
C
A M B S
L
6
N
α
8
8
7
NOTES:
o
o
o
o
0
8
0
8
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA
EUROPE
ASIA
Intersil Corporation
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
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