HFA1113MJ/883_技术文档

TM

HFA1113/883

Output Limiting, Ultra High Speed

Programmable Gain, Buffer Amplifier

July 1994

Features

Description

• This Circuit is Processed in Accordance to MIL-STD- The HFA1113/883 is a closed loop buffer featuring a high

883 and is Fully Conformant Under the Provisions of degree of gain accuracy, wide bandwidth, low distortion, and

Paragraph 1.2.1.

programmable output limiting. This buffer is the ideal choice

for high frequency applications requiring output limiting,

especially those needing ultra fast overdrive recovery times.

The output limiting function allows the designer to set the

maximum positive and negative output levels, thereby pro-

tecting later stages from damage or input saturation. The

sub-nanosecond overdrive recovery time quickly returns the

amplifier to linear operation following an overdrive condition.

• User Programmable Output Voltage Limiting

• User Programmable For Closed-Loop Gains of +1, -1

or +2 Without Use of External Resistors

• Low Differential Gain and Phase . . . . .0.02%/0.04 Deg.

• Low Distortion (HD3, 30MHz) . . . . . . . . . . -73dBc (Typ)

• Wide -3dB Bandwidth . . . . . . . . . . . . . . . 850MHz (Typ)

• Very High Slew Rate . . . . . . . . . . . . . . . 2400V/µs (Typ)

• Fast Settling (0.1%) . . . . . . . . . . . . . . . . . . . . 13ns (Typ)

• Excellent Gain Flatness (to 100MHz) . . . . 0.07dB (Typ)

• Excellent Gain Accuracy. . . . . . . . . . . . . . 0.99V/V (Typ)

• High Output Current . . . . . . . . . . . . . . . . . . 60mA (Typ)

• Fast Overdrive Recovery . . . . . . . . . . . . . . . <1ns (Typ)

Component and composite video systems will also benefit

from this buffer’s performance, as indicated by the excellent

gain flatness, and 0.02%/0.04 Deg. Differential Gain/Phase

specifications (R = 150Ω).

L

A unique feature of the pinout allows the user to select a

voltage gain of +1, -1, or +2, without the use of any external

components, as described in the “Design Information” sec-

tion. Compatibility with existing op amp pinouts provides

flexibility to upgrade low gain amplifiers, while decreasing

component count. Unlike most buffers, the standard pinout

provides an upgrade path should a higher closed loop gain

be needed at a future date.

Applications

This amplifier is available without output limiting as the

HFA1112/883. For applications requiring a standard buffer

pinout, please refer to the HFA1110/883 datasheet.

• Video Switching and Routing

• Pulse and Video Amplifiers

• Wideband Amplifiers

• RF/IF Signal Processing

• Flash A/D Driver

Ordering Information

TEMPERATURE

PART NUMBER

HFA1113MJ/883

HFA1113ML/883

RANGE

PACKAGE

• Medical Imaging Systems

-55^oC to +125^oC 8 Lead CerDIP

-55^oC to +125^oC 20 Lead Ceramic LCC

Pinouts

HFA1113/883

(CERDIP)

HFA1113/883

(CLCC)

TOP VIEW

300

NC

-IN

+IN

V-

1

2

3

4

8

7

6

5

V_H

3

2

1

20 19

300

V+

V_H

V+

300

18

17

16

15

14

NC

-IN

4

5

6

7

8

-

+

300

OUT

V_L

-

NC

+IN

NC

+

OUT

NC

13

10 11 12

9

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.

Spec Number 511106-883

189

FN3618.1

Specifications HFA1113/883

Absolute Maximum Ratings

Thermal Information

Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V

Voltage at Either Input Terminal. . . . . . . . . . . . . . . . . . . . . . V+ to V-

Voltage at V_Hor V_LTerminal . . . . . . . . . . . . . (V+) + 2V to (V-) - 2V

Output Current (50% Duty Cycle) . . . . . . . . . . . . . . . . . . . . . . . .±55mA

Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175^oC

ESD Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .< 2000V

Storage Temperature Range . . . . . . . . . . . . . .-65^oC ≤ T_A≤ +150^oC

Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300^oC

Thermal Resistance

θ_JA

θ_JC

CerDIP Package . . . . . . . . . . . . . . . . . 115^oC/W

Ceramic LCC Package . . . . . . . . . . . . 75^oC/W

Maximum Package Power Dissipation at +75^oC

30^oC/W

23^oC/W

CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.87W

Ceramic LCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.33W

Package Power Dissipation Derating Factor above +75^oC

CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.7mW/^oC

Ceramic LCC Package . . . . . . . . . . . . . . . . . . . . . . . . 13.3mW/^oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions

Operating Supply Voltage (±V_S) . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5V

Operating Temperature Range. . . . . . . . . . . . .-55^oC ≤ T_A≤ +125^oC

R_LŠ≥ 50Ω

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

Device Tested at: V_SUPPLY= ±5V, R_SOURCE= 0Ω, R_L= 100Ω, V_OUT= 0V, Unless Otherwise Specified.

LIMITS

GROUP A

PARAMETERS

SYMBOL

CONDITIONS

V_CM= 0V

SUBGROUPS

TEMPERATURE

+25^oC

+125^oC, -55^oC

+25^oC

MIN

MAX

UNITS

mV

Output Offset Voltage

V_OS

1

-25

-40

39

25

40

-

2, 3

1

mV

Power Supply

Rejection Ratio

PSRRP

PSRRN

∆V_SUPPLY= ±1.25V,

V+ = 6.25V, V- = -5V,

V+ = 3.75V, V- = -5V

dB

2, 3

+125^oC, -55^oC

35

-

dB

∆V_SUPPLY= ±1.25V,

V+ = 5V, V- = -6.25V,

V+ = 5V, V- = -3.75V

1

+25^oC

+125^oC, -55^oC

39

35

-

dB

2, 3

Non-Inverting Input (+IN)

Current

I_BSP

V_CM= 0V

1

+25^oC

+125^oC, -55^oC

+25^oC

-40

-65

-

40

65

40

50

µA

2, 3

1

+IN Common

Mode Rejection

CMS_IBP

∆V_CM= ±2V,

V+ = 3V, V- = -7V,

V+ = 7V, V- = -3V

µA/V

2, 3

+125^oC, -55^oC

-

+IN Resistance

+R_IN

A_VP1

Note 1

1

2, 3

1

+25^oC

+125^oC, -55^oC

+25^oC

+125^oC, -55^oC

+25^oC

+125^oC, -55^oC

+25^oC

+125^oC, -55^oC

+25^oC

25

-

kΩ

V/V

V

20

-

Gain (V_OUT= 2V_P-P

Gain (V_OUT= 4V_P-P

)

A_V= +1,

0.980

0.975

0.980

0.975

1.960

1.950

3

1.020

1.025

1.020

1.025

2.040

2.050

-

V_IN= -1V to +1V

2, 3

1

A_VM1

A_V= -1,

_IN= -1V to +1V

V

2, 3

1

A_VP2

A_V= +2,

_IN= -1V to +1V

V

2, 3

1

Output Voltage

Swing

V_OP100

A_V= -1

R_L= 100Ω

V_IN= -3.2V

V_IN= -

2.7V

2, 3

+125^oC, -55^oC

2.5

-

V

V_ON100

A_V= -1

R_L= 100Ω

V_IN= +3.2V

V_IN= +2.7V

V_IN= -2.7V

1

+25^oC

+125^oC, -55^oC

+25^oC, +125^oC

-55^oC

-

-3

V

2, 3

1, 2

3

-

-2.5

Output Voltage

Swing

V_OP50

A_V= -1

R_L= 50Ω

2.5

1.5

-

V_IN= -

2.25V

V_ON50

A_V= -1

R_L= 50Ω

V_IN= +2.7V

V_IN=+2.25V

1, 2

3

+25^oC, +125^oC

-55^oC

-

-2.5

-1.5

V

Spec Number 511106-883

190

Specifications HFA1113/883

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

Device Tested at: V_SUPPLY= ±5V, R_SOURCE= 0Ω, R_L= 100Ω, V_OUT= 0V, Unless Otherwise Specified.

LIMITS

GROUP A

PARAMETERS

Output Current

SYMBOL

CONDITIONS

Note 2

SUBGROUPS

TEMPERATURE

+25^oC, +125^oC

-55^oC

+25^oC, +125^oC

-55^oC

+25^oC

+125^oC, -55^oC

+25^oC

+125^oC, -55^oC

+25^oC

+125^oC, -55^oC

+25^oC

+125^oC, -55^oC

+25^oC

+125^oC, -55^oC

+25^oC

MIN

MAX

-

UNITS

mA

mV

µA

+I_OUT

1, 2

3

50

30

-

-I_OUT

Note 2

1, 2

3

-

-50

-30

26

33

-14

-

Quiescent Power

Supply Current

I_CC

R_L= 100Ω

1

14

2, 3

1

-

I_EE

R_L= 100Ω

-26

-33

-150

-200

-150

-200

-

2, 3

1

Limiting Accuracy

V_Hor V_LInput Current

NOTES:

V_HCLMP

V_LCLMP

V_HBIAS

V_LBIAS

A_V= -1, V_IN= -1.6V,

150

200

150

200

300

-

V_H= 1V

2, 3

1

A_V= -1, V_IN= +1.6V,

V_L= -1V

2, 3

1

V_H= 1V

2, 3

1

-

µA

V_L= -1V

-200

-300

µA

2, 3

+125^oC, -55^oC

-

µA

1. Guaranteed from +IN Common Mode Rejection Test, by: +R_IN= 1/CMS_IBP

.

2. Guaranteed from V_OUTTest with R_L= 50Ω, by: I_OUT= V_OUT/50Ω.

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

Table 2 Intentionally Left Blank.

Device Characterized at: V_SUPPLY= ±5V, R_L= 100Ω, Unless Otherwise Specified.

LIMITS

PARAMETERS

-3dB Bandwidth

SYMBOL

BW(-1)

BW(+1)

BW(+2)

GF30

CONDITIONS

A_V= -1, V_OUT= 200mV_P-P

A_V= +1, V_OUT= 200mV_P-P

A_V= +2, V_OUT= 200mV_P-P

A_V= +2, f ≤ 30MHz,

NOTES

TEMPERATURE

+25^oC

MIN

450

500

350

-

MAX

UNITS

MHz

dB

1

-

+25^oC

-

+25^oC

Gain Flatness

+25^oC

±0.04

V_OUT= 200mV_P-P

GF50

A

V

_V= +2, f ≤ 50MHz,

_OUT= 200mV_P-P

1

+25^oC

-

±0.08

±0.22

dB

GF100

A

V

_V= +2, f ≤ 100MHz,

_OUT= 200mV_P-P

Slew Rate

+SR(-1)

-SR(-1)

+SR(+1)

-SR(+1)

+SR(+2)

-SR(+2)

A

_V= -1, V_OUT= 5V_P-P

1, 2

+25^oC

1500

1800

900

-

V/µs

A_V= -1, V_OUT= 5V_P-P

A_V= +1, V_OUT= 5V_P-P

A_V= +2, V_OUT= 5V_P-P

800

1200

1100

Spec Number 511106-883

191

Specifications HFA1113/883

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

Device Characterized at: V_SUPPLY= ±5V, R_L= 100Ω, Unless Otherwise Specified.

LIMITS

MIN

PARAMETERS

SYMBOL

T_R(-1)

CONDITIONS

A_V= -1, V_OUT= 0.5V_P-P

A_V= +1, V_OUT= 0.5V_P-P

A_V= +2, V_OUT= 0.5V_P-P

NOTES

1, 2

1, 3

1

TEMPERATURE

+25^oC

MAX

750

800

750

1000

30

UNITS

ps

%

Rise and Fall Time

-

T_F(-1)

+25^oC

T_R(+1)

+25^oC

T_F(+1)

+25^oC

T_R(+2)

+25^oC

T_F(+2)

+25^oC

Overshoot

+OS(-1)

-OS(-1)

+OS(+1)

-OS(+1)

+OS(+2)

-OS(+2)

TS(0.1)

A

_V= -1, V_OUT= 0.5V_P-P

A_V= -1, V_OUT= 0.5V_P-P

_V= +1, V_OUT= 0.5V_P-P

+25^oC

25

%

A

+25^oC

65

%

A_V= +1, V_OUT= 0.5V_P-P

A_V= +2, V_OUT= 0.5V_P-P

+25^oC

60

%

+25^oC

20

%

+25^oC

20

%

Settling Time

A_V= +2, to 0.1%, V_OUT= 2V to

+25^oC

20

ns

0V

TS(0.05)

HD2(30)

HD2(50)

HD2(100)

HD3(30)

HD3(50)

HD3(100)

A

_V= +2, to 0.05%,

1

+25^oC

-

33

-45

-40

-35

-65

-55

-45

ns

V_OUT= 2V to 0V

2nd Harmonic Distortion

A

_V= +2, f = 30MHz,

dBc

V_OUT= 2V_P-P

A

_V= +2, f = 50MHz,

V_OUT= 2V_P-P

A

_V= +2, f = 100MHz,

V_OUT= 2V_P-P

3rd Harmonic Distortion

A_V= +2, f = 30MHz,

V_OUT= 2V_P-P

A

_V= +2, f = 50MHz,

V_OUT= 2V_P-P

A

_V= +2, f = 100MHz,

V_OUT= 2V_P-P

NOTES:

1. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These param-

eters are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization

based upon data from multiple production runs which reflect lot-to-lot and within lot variation.

2. Measured between 10% and 90% points.

3. For 200ps input transition times. Overshoot decreases as input transition times increase, especially for A_V= +1. Please refer to

Performance Curves.

TABLE 4. ELECTRICAL TEST REQUIREMENTS

MIL-STD-883 TEST REQUIREMENTS

Interim Electrical Parameters (Pre Burn-In)

Final Electrical Test Parameters

Group A Test Requirements

SUBGROUPS (SEE TABLE 1)

1

1 (Note 1), 2, 3

1, 2, 3

Groups C and D Endpoints

1

NOTE:

1. PDA applies to Subgroup 1 only.

Spec Number 511106-883

192

HFA1113/883

Die Characteristics

DIE DIMENSIONS:

63 x 44 x 19 mils ± 1 mils

1600 x 1130 x 483µm ± 25.4µm

METALLIZATION:

Type: Metal 1: AICu(2%)/TiW

Thickness: Metal 1: 8kÅ ± 0.4kÅ

Type: Metal 2: AICu(2%)

Thickness: Metal 2: 16kÅ ± 0.8kÅ

GLASSIVATION:

Type: Nitride

Thickness: 4kÅ ± 0.5kÅ

WORST CASE CURRENT DENSITY:

5

2

2.0 x 10 A/cm at 47.5mA

TRANSISTOR COUNT: 52

SUBSTRATE POTENTIAL (Powered Up): Floating (Recommend Connection to V-)

Metallization Mask Layout

HFA1113/883

NC

+IN

V-

V_L

-IN

V_H

NC

V+

OUT

Spec Number 511106-883

193

HFA1113/883

Test Circuit (Applies to Table 1)

NC

K3

V_L

50

0.1

V_Y

V+

+

V_os

V_Y

=

100

10

0.1

I_CC

0.1

+

-

470pF

NC

510

x100

510

7

1

K2

2

5

-

-V_IN

1K

6

2

0.1

V_OUT

DUT

1

3

+

+V_IN

8

100

0.1

K1

2

4

50

100K (0.01%)

K3

V_Z

+I_BIAS

=

0.1

100K

-

+

10

0.1

NC

V_Z

+

0.1

HA-5177

K4

NOTE:

Terminal Numbers Refer to CerDIP Package

All Resistors = ±1% (Ω)

I_EE

0.1

All Capacitors = ±10% (µF)

Unless Otherwise Noted

Chip Components Recommended

V-

V_H

For A_V= +1, K1 = Position 1, K2 = Position 1

For A_V= +2, K1 = Position 1, K2 = Position 2, -V_IN= 0V

For A_V= -1, K1 = Position 1, K2 = Position 2, +V_IN= 0V

Test Waveforms

SIMPLIFIED TEST CIRCUIT FOR LARGE AND SMALL SIGNAL PULSE RESPONSE (Applies to Table 3)

A_V= +1 or +2 TEST CIRCUIT

A_V= -1 TEST CIRCUIT

V+

7

2

3

6

+

-

V_OUT

2

V_OUT

2

6

-

V_IN

2

3

+

R_S

50Ω

R_S

50Ω

4

50Ω

R_G

V-

NOTE:

V_S= ±5V, A_V= -1

NOTE:

V_S= ±5V, R_G= 0Ω for A_V= +2, R_G= ∞ for A_V= +1

_F= Internal, R_S= 50Ω

R_L= 100Ω For Small and Large Signals

Terminal Numbers Refer to CerDIP Package

R

_F= Internal

_S= 50Ω, R_L= 100Ω For Small and Large Signals

R

Terminal Numbers Refer to CerDIP Package

LARGE SIGNAL WAVEFORM

SMALL SIGNAL WAVEFORM

V_OUT

+2.5V

+250mV

90%

+SR

-SR

T_R, +OS

-250mV

T

_F, -OS

10%

-2.5V

-250mV

Spec Number 511106-883

194

HFA1113/883

Burn-In Circuits

HFA1113MJ/883 CERAMIC DIP

300

1

2

3

4

8

7

6

5

D3

C1

300

NC

V+

-

+

D1

D4

R1

V-

D2

C2

NOTES:

R1 = 100Ω, ±5% (Per Socket)

C1 = C2 = 0.01µF (Per Socket) or 0.1µF (Per Row) Minimum

D1 = D2 = 1N4002 or Equivalent (Per Board)

D3 = D4 = 1N4002 or Equivalent (Per Socket)

V+ = +5.5V ±0.5V

V- = -5.5V ±0.5V

HFA1113ML/883 CERAMIC LCC

3

2

1 20 19

18

17

16

15

14

4

5

6

7

8

300

D3

300

V+

NC

-

C1

D1

+

R1

R2

13

10 11 12

9

D4

V-

D2

C2

NOTES:

R1 = 1kΩ, ±5% (Per Socket)

R2 = 100Ω, ±5% (Per Socket)

C1 = C2 = 0.01µF (Per Socket) or 0.1µF (Per Row) Minimum

D1 = D2 = 1N4002 or Equivalent (Per Board)

D3 = D4 = 1N4002 or Equivalent (Per Socket)

V+ = +5.5V ±0.5V

V- = -5.5V ±0.5V

Spec Number 511106-883

195

HFA1113/883

Ceramic Dual-In-Line Frit Seal Packages (CerDIP)

c1 LEAD FINISH

F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A)

8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE

-D-

E

-A-

INCHES MILLIMETERS

MIN

BASE

(c)

METAL

SYMBOL

MAX

0.200

0.026

0.023

0.065

0.045

0.018

0.015

0.405

0.310

MIN

-

MAX

5.08

0.66

0.58

1.65

1.14

0.46

0.38

10.29

7.87

NOTES

b1

A

b

-

M

0.014

0.045

0.023

0.008

-

0.36

1.14

0.58

0.20

-

2

-B-

(b)

b1

b2

b3

c

3

SECTION A-A

S

D

bbb

C A - B

D

-

4

BASE

PLANE

Q

2

A

-C-

SEATING

PLANE

c1

D

3

L

α

5

S1

b2

eA

A A

E

0.220

5.59

5

e

b

C A - B

eA/2

c

e

0.100 BSC

2.54 BSC

-

eA

eA/2

L

0.300 BSC

0.150 BSC

7.62 BSC

3.81 BSC

-

M

S

M

S

D

ccc

D

aaa

C A - B

-

NOTES:

0.125

0.200

0.060

-

3.18

5.08

1.52

-

1. Index area: A notch or a pin one identification mark shall be locat-

ed adjacent to pin one and shall be located within the shaded

area shown. The manufacturer’s identification shall not be used

as a pin one identification mark.

Q

0.015

0.38

6

S1

α

0.005

0.13

7

90^o

105^o

0.015

0.030

0.010

0.0015

90^o

105^o

0.38

0.76

0.25

0.038

-

2. The maximum limits of lead dimensions b and c or M shall be

measured at the centroid of the finished lead surfaces, when

solder dip or tin plate lead finish is applied.

aaa

bbb

ccc

M

-

3. Dimensions b1 and c1 apply to lead base metal only. Dimension

M applies to lead plating and finish thickness.

2, 3

8

4. Corner leads (1, N, N/2, and N/2+1) may be configured with a

partial lead paddle. For this configuration dimension b3 replaces

dimension b2.

N

8

Rev. 0 4/94

5. This dimension allows for off-center lid, meniscus, and glass

overrun.

6. Dimension Q shall be measured from the seating plane to the

base plane.

7. Measure dimension S1 at all four corners.

8. N is the maximum number of terminal positions.

9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.

10. Controlling dimension: INCH.

11. Materials: Compliant to MIL-I-38535.

Spec Number 511106-883

196

HFA1113/883

Ceramic Leadless Chip Carrier Packages (CLCC)

J20.A MIL-STD-1835 CQCC1-N20 (C-2)

20 PAD LEADLESS CERAMIC CHIP CARRIER

0.010

E H

S

D

INCHES

MIN

MILLIMETERS

D3

SYMBOL

A

MAX

0.100

0.088

-

MIN

1.52

1.27

-

MAX

2.54

2.23

-

NOTES

j x 45^o

0.060

0.050

-

6, 7

A1

B

-

B1

B2

B3

D

0.022

0.028

0.56

0.71

2, 4

E3

E

0.072 REF

1.83 REF

-

B

0.006

0.342

0.022

0.358

0.15

8.69

0.56

9.09

-

D1

D2

D3

E

0.200 BSC

0.100 BSC

5.08 BSC

2.54 BSC

-

h x 45^o

-

0.358

-

9.09

2

0.010

E F

S

0.342

8.69

-

A

A1

E1

E2

E3

e

0.200 BSC

0.100 BSC

0.358

0.050 BSC

0.015

5.08 BSC

2.54 BSC

9.09

1.27 BSC

0.38

1.02 REF

0.51 REF

-

PLANE 2

PLANE 1

-

2

-

-E-

e1

h

-

2

0.040 REF

0.020 REF

5

j

5

0.007

E F

H

S S

M

L

0.045

0.055

0.095

0.015

1.14

1.91

0.08

1.40

2.41

0.38

-

B1

L1

L2

L3

ND

NE

N

0.045

0.075

0.003

-

e

L3

L

-

-H-

-

5

3

20

-F-

Rev. 0 4/94

B3

E1

NOTES:

1. Metallized castellations shall be connected to plane 1 terminals

and extend toward plane 2 across at least two layers of ceramic

or completely across all of the ceramic layers to make electrical

connection with the optional plane 2 terminals.

L2

E2

B2

2. Unless otherwise specified, a minimum clearance of 0.015 inch

(0.38mm) shall be maintained between all metallized features

(e.g., lid, castellations, terminals, thermal pads, etc.)

L1

D2

3. Symbol “N” is the maximum number of terminals. Symbols “ND”

and “NE” are the number of terminals along the sides of length

“D” and “E”, respectively.

e1

D1

4. The required plane 1 terminals and optional plane 2 terminals (if

used) shall be electrically connected.

5. The corner shape (square, notch, radius, etc.) may vary at the

manufacturer’s option, from that shown on the drawing.

6. Chip carriers shall be constructed of a minimum of two ceramic

layers.

7. Dimension “A” controls the overall package thickness. The maxi-

mum “A” dimension is package height before being solder dipped.

8. Dimensioning and tolerancing per ANSI Y14.5M-1982.

9. Controlling dimension: INCH.

10. Materials: Compliant to MIL-I-38535.

Spec Number 511106-883

197

TM

HFA1113

DESIGN INFORMATION

February 2002

Output Limiting, Ultra High Speed

Programmable Gain Buffer Amplifier

The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as

application and design information only. No guarantee is implied.

Typical Performance Curves V_SUPPLY= ±5V, R_L= 100Ω, T_A= +25^oC, Unless Otherwise Specified

SMALL SIGNAL PULSE RESPONSE

LARGE SIGNAL PULSE RESPONSE

200

150

100

50

2.0

1.5

1.0

0.5

0

A_V= +2

0

-50

-0.5

-1.0

-1.5

-2.0

-100

-150

-200

5ns/DIV

SMALL SIGNAL PULSE RESPONSE

LARGE SIGNAL PULSE RESPONSE

2.0

1.5

1.0

0.5

0

200

150

100

50

A_V= +1

0

-0.5

-1.0

-1.5

-2.0

-50

-100

-150

-200

5ns/DIV

SMALL SIGNAL PULSE RESPONSE

LARGE SIGNAL PULSE RESPONSE

2.0

1.5

1.0

0.5

0

200

150

100

50

A_V= -1

0

-0.5

-1.0

-1.5

-2.0

-50

-100

-150

-200

5ns/DIV

Spec Number 511106-883

198

HFA1113

DESIGN INFORMATION(Continued)

The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as

application and design information only. No guarantee is implied.

Typical Performance Curves V_SUPPLY= ±5V, R_L= 100Ω, T_A= +25^oC, Unless Otherwise Specified (Continued)

UNCLAMPED PERFORMANCE

CLAMPED PERFORMANCE

(A_V= +2, V_H= 2V, V_L= -2V)

(A_V= +2, V_H= 1V, V_L= -1V, 2X Overdrive)

A_V= +2

IN

0V TO

1V

IN

0V TO

0.5V

A_V= +2

OUT

0V TO

1V

OUT

0V TO

1V

20ns/DIV

FREQUENCY RESPONSE

FREQUENCY RESPONSE FOR VARIOUS LOAD RESISTORS

6

A_V= +2, V_OUT= 200mV_P-P

9

A_V= +1

V_OUT= 200mV_P-P

3

0

6

GAIN

A_V= -1

A_V= +2

3

-3

R_L= 50Ω

R_L= 100Ω

R_L= 1kΩ

0

-6

-9

0

PHASE

-90

A_V= +2

A_V= -1

A_V= +1

0

-180

-270

-360

PHASE

-90

R_L= 100Ω

R_L= 50Ω

R_L= 1kΩ

-180

-270

-360

0.3

1

10

100

1000

0.3

1

10

FREQUENCY (MHz)

100

1000

FREQUENCY (MHz)

FREQUENCY RESPONSE FOR VARIOUS LOAD RESISTORS

6

FREQUENCY RESPONSE FOR VARIOUS LOAD RESISTORS

6

A_V= -1, V_OUT= 200mV_P-P

A_V= +1, V_OUT= 200mV_P-P

R_L= 1kΩ

3

R_L= 1kΩ

0

GAIN

PHASE

1

R_L= 100Ω

R_L= 50Ω

R_L= 100Ω

-3

-6

-9

R_L= 50Ω

-6

-9

R_L= 100Ω

180

0

PHASE

90

-90

R_L= 100Ω

R_L= 50Ω

-180

-270

-360

0

R_L= 50Ω

R_L= 1kΩ

-90

R_L= 1kΩ

-180

1000

0.3

10

FREQUENCY (MHz)

100

1000

0.3

1

10

100

FREQUENCY (MHz)

Spec Number 511106-883

199

HFA1113

DESIGN INFORMATION(Continued)

The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as

application and design information only. No guarantee is implied.

Typical Performance Curves V_SUPPLY= ±5V, R_L= 100Ω, T_A= +25^oC, Unless Otherwise Specified (Continued)

FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES

12

FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES

6

A_V= +1

1V_P-P

A_V= +2

9

3

0

6

GAIN

V_OUT= 4V_P-P

-3

GAIN

3

V_OUT= 2.5V_P-P

4.0V_P-P

-6

0

V_OUT= 1V_P-P

2.5V_P-P

0

PHASE

-90

-180

4.0V_P-P

V_OUT= 4V_P-P

2.5V_P-P

1V_P-P

-270

-360

-270

-360

V_OUT= 2.5V_P-P

V_OUT= 1V_P-P

0.3

1

10

100

1000

0.3

1

10

FREQUENCY (MHz)

100

1000

FREQUENCY (MHz)

FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES

6

FULL POWER BANDWIDTH

15

12

9

A_V= -1

V_OUT= 2.5V_P-P

V_OUT= 4V_P-P

V_OUT= 5V_P-P

3

0

GAIN

V_OUT= 1V_P-P

-3

-6

6

3

PHASE

180

90

0

A_V= -1

A_V= +2

-3

-6

V_OUT= 4V_P-P

0

A_V= +1

V_OUT= 2.5V_P-P

V_OUT= 1V_P-P

-90

-180

-9

-12

-15

0.3

1

10

100

1000

0.3

1

10

FREQUENCY (MHz)

100

1000

FREQUENCY (MHz)

-3dB BANDWIDTH vs TEMPERATURE

GAIN FLATNESS

900

0.35

0.30

0.25

0.20

0.15

0.10

0.05

A_V= +1

A_V= -1

850

800

750

700

650

600

550

500

A_V= -1

A_V= +1

0

-0.05

-0.10

-0.15

A_V= +2

100

1

10

FREQUENCY (MHz)

-50

-25

0

+25

+50

+75 +100 +125

TEMPERATURE (^oC)

Spec Number 511106-883

200

HFA1113

DESIGN INFORMATION(Continued)

The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as

application and design information only. No guarantee is implied.

Typical Performance Curves V_SUPPLY= ±5V, R_L= 100Ω, T_A= +25^oC, Unless Otherwise Specified (Continued)

DEVIATION FROM LINEAR PHASE

SETTLING RESPONSE

4

3

A_V= +2, V_OUT= 2V

0.6

0.4

2

1

A_V= -1

A_V= +2

0.2

0.1

0

-0.1

-0.2

0

-1

-2

-3

-4

-5

-6

A_V= +1

-0.4

-0.6

-2

3

8

13

18

23

28 33

38

43

48

0

15

30

45 60 75

90 105 120 135 150

TIME (ns)

FREQUENCY (MHz)

LOW FREQUENCY REVERSE ISOLATION (S₁₂

)

HIGH FREQUENCY REVERSE ISOLATION (S₁₂)

180

-24

-30

-36

-42

-48

-54

-60

-66

-72

-78

-84

135

90

45

0

PHASE

A_V= +1

A_V= -1

A_V= +2

GAIN

-24

-30

-36

-42

-48

-54

-60

A_V= +2

A_V= -1

A_V= +2

A_V= +1

A_V= -1

A_V= +2

A_V= -1

100 190 280 370 460 550 640 730 820 910 1000

20

40 60

80 100 120 140 160 180 200

FREQUENCY (MHz)

0

FREQUENCY (MHz)

1dB GAIN COMPRESSION vs FREQUENCY

3rd ORDER INTERMODULATION INTERCEPT vs FREQUENCY

20

18

16

14

12

10

8

30

2 - TONE

A_V= -1

20

A_V= +2

A_V= +1

10

6

4

2

0

100

0

100

200

300

400

200

300

400

500

FREQUENCY (MHz)

Spec Number 511106-883

201

HFA1113

DESIGN INFORMATION(Continued)

The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as

application and design information only. No guarantee is implied.

Typical Performance Curves V_SUPPLY= ±5V, R_L= 100Ω, T_A= +25^oC, Unless Otherwise Specified (Continued)

2nd HARMONIC DISTORTION vs P_OUT

3rd HARMONIC DISTORTION vs P_OUT

-20

-30

-40

-50

-60

-70

-80

-90

-100

-20

-30

-40

-50

-60

-70

-80

-90

-100

A_V= +2

30MHz

50MHz

100MHz

30MHz

50MHz

100MHz

-6

-3

0

3

6

9

12

15

18

-6

-3

0

3

6

9

12

15

OUTPUT POWER (dBm)

2nd HARMONIC DISTORTION vs P_OUT

A_V= +1

3rd HARMONIC DISTORTION vs P_OUT

A_V= +1

-20

-30

-40

-20

-30

-40

-50

-60

-70

-80

-50

-60

-70

-80

30MHz

50MHz

100MHz

30MHz

6

50MHz

-90

-100

-6

-3

0

3

6

9

12

15

-6

-3

0

3

9

12

15

OUTPUT POWER (dBm)

2nd HARMONIC DISTORTION vs P_OUT

A_V= -1

3rd HARMONIC DISTORTION vs P_OUT

A_V= -1

-20

-30

-40

-20

-30

-40

-50

-60

-70

-80

-50

-60

50MHz

30MHz

100MHz

-70

-80

30MHz

50MHz

100MHz

-90

-100

-6

-3

0

3

6

9

12

15

-6

-3

0

3

6

9

12

15

OUTPUT POWER (dBm)

Spec Number 511106-883

202

HFA1113

DESIGN INFORMATION(Continued)

The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as

application and design information only. No guarantee is implied.

Typical Performance Curves V_SUPPLY= ±5V, R_L= 100Ω, T_A= +25^oC, Unless Otherwise Specified (Continued)

INTEGRAL LINEARITY ERROR

OVERSHOOT vs INPUT RISE TIME

60

50

40

30

20

+0.04

+0.02

0

V_OUT= 0.5V

A_V= +1

-0.02

A_V= -1

10

0

A_V= +2

300

-0.04

100

500

700

900

1100

1300

-3.0

-2.0

-1.0

0

+1.0

+2.0

+3.0

INPUT VOLTAGE (V)

INPUT RISE TIME (ps)

OVERSHOOT vs INPUT RISE TIME

V_OUT= 1V

OVERSHOOT vs INPUT RISE TIME

V_OUT= 2V

60

50

40

30

20

10

0

60

50

40

30

20

A_V= +1

A_V= +2

A_V= -1

10

0

A_V= -1

A_V= +2

100

300

500

700

900

1100

1300

100

300

500

700

900

1100

1300

INPUT RISE TIME (ps)

SUPPLY CURRENT vs SUPPLY VOLTAGE

SUPPLY CURRENT vs TEMPERATURE

25

22

21

20

19

18

17

16

15

14

13

12

11

10

9

24

23

22

21

20

19

18

17

16

15

8

7

6

5

-50

-25

0

+25

+50

+75

+100 +125

5

6

7

8

9

10

TEMPERATURE (^oC)

TOTAL SUPPLY VOLTAGE (V+ - V-, V)

Spec Number 511106-883

203

HFA1113

DESIGN INFORMATION(Continued)

The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as

application and design information only. No guarantee is implied.

Typical Performance Curves V_SUPPLY= ±5V, R_L= 100Ω, T_A= +25^oC, Unless Otherwise Specified (Continued)

OUTPUT VOLTAGE vs TEMPERATURE

INPUT NOISE CHARACTERISTICS

3.6

3.5

3.4

3.3

3.2

3.1

50

40

30

20

10

0

130

110

A_V= -1

+V_OUT(R_L= 50Ω)

+V_OUT(R_L= 100Ω)

|-V_OUT| (R_L= 100Ω)

90

70

50

30

3.0

2.9

eni

ini

2.8

2.7

2.6

|-V_OUT| (R_L= 50Ω)

-50

-25

0

+25

+50

+75

+100 +125

0.1

1

10

100

TEMPERATURE (^oC)

FREQUENCY (kHz)

NON-LINEARITY NEAR CLAMP VOLTAGE

V_HCLAMP ACCURACY vs OVERDRIVE

(A_V= -1)

20

350

300

250

200

150

100

50

A_V= ±1

15

10

5

V_L= -2V

V_L= -3V

V_L= -1V

V_H= 500mV

V_H= 1V

0

-5

V

_H= 2V

V_H= 2V

V_H= 1V

V_H= 3V

-10

-15

-20

V_H= 100mV

-3

-2

-1

0

1

2

3

0

100

200

300

400

500

A

_V* V_IN(V)

OVERDRIVE (% OF V_H)

V_LCLAMP ACCURACY vs OVERDRIVE

V_HCLAMP ACCURACY vs OVERDRIVE

250

200

150

100

50

400

300

200

100

0

A_V= ±1

A_V= +2

V_L= 500mV

V_H= 1V

V_L= 1V

V

_H= 2V

V_H= 500mV

V_L= 2V

V_H= 100mV

V_L= 100mV

400 500

0

100

200

300

0

100

200

300

400

500

OVERDRIVE (% OF V_L)

OVERDRIVE (% OF V_H)

Spec Number 511106-883

204

HFA1113

DESIGN INFORMATION(Continued)

The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as

application and design information only. No guarantee is implied.

Typical Performance Curves V_SUPPLY= ±5V, R_L= 100Ω, T_A= +25^oC, Unless Otherwise Specified (Continued)

V_LCLAMP ACCURACY vs OVERDRIVE

OVERDRIVE RECOVERY vs OVERDRIVE

250

200

150

100

50

3500

3000

2500

2000

1500

A_V= +2

V_L= 1V

V_L= 500mV

V_H= 2V

V

_L= 2V

V_H= 1V

1000

500

0

V

_H= 0.5V

V_L= 100mV

400

V_H= 0.1V

0

100

200

300

500

100

200

300

400

500

OVERDRIVE (% OF V_L)

OVERDRIVE LEVEL (% OF CLAMP LEVEL)

CLAMP ACCURACY vs TEMPERATURE

CLAMP BIAS CURRENT vs TEMPERATURE

V_H= 1V, V_L= -1V

140

130

120

110

100

130

120

110

100

90

A_V= -1, V_IN= ±1.6V

V_H= 1V, V_L= -1V

V_L

V_H

80

70

90

80

60

V_H

V_L

50

40

70

60

30

20

-75

-25

+75

TEMPERATURE (°C)

+125

+100 +150

-50

0

+25 +50

-25

+25

+75

+125

+100 +150

-50

0

+50

TEMPERATURE (°C)

V_HCLAMP INPUT BANDWIDTH

V_LCLAMP INPUT BANDWIDTH

6

3

0

6

V_L= 300mV_P-P

V_H= 300mV_P-P

3

0

-3

-6

V_L= 600mV_P-P

V_L= 1.2V_P-P

V_H= 600mV_P-P

V_H= 1.2V_P-P

-9

-12

1

10

100

FREQUENCY (MHz)

1000

1

10

100

1000

FREQUENCY (MHz)

Spec Number 511106-883

205

HFA1113

DESIGN INFORMATION(Continued)

The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as

application and design information only. No guarantee is implied.

Application Information

Closed Loop Gain Selection

The HFA1113 features a novel design which allows the user Figure 1 details starting points for the selection of this resis-

to select from three closed loop gains, without any external tor. The points on the curve indicate the R and C combina-

S

L

components. The result is a more flexible product, fewer part tions for the optimum bandwidth, stability, and settling time,

types in inventory, and more efficient use of board space.

but experimental fine tuning is recommended. Picking a

point above or to the right of the curve yields an overdamped

response, while points below or left of the curve indicate

areas of underdamped performance.

This “buffer” operates in closed loop gains of -1, +1, or +2, and

gain selection is accomplished via connections to the ±Inputs.

Applying the input signal to +IN and floating -IN selects a gain

of +1, while grounding -IN selects a gain of +2. A gain of -1 is

obtained by applying the input signal to -IN with +IN grounded.

R and C form a low pass network at the output, thus lim-

S

L

iting system bandwidth well below the amplifier bandwidth

of 850MHz. By decreasing R as C increases (as illus-

S

L

The table below summarizes these connections:

trated in the curves), the maximum bandwidth is obtained

without sacrificing stability. Even so, bandwidth does

decrease as you move to the right along the curve. For

CONNECTIONS

GAIN

(A_CL

)

+INPUT (PIN 3)

-INPUT (PIN 2)

example, at A = +1, R = 50Ω, C = 30pF, the overall

bandwidth is limited to 300MHz, and bandwidth drops to

V

S

L

-1

GND

Input

+1

Input

NC (Floating)

GND

100MHz at A = +1, R = 5Ω, C = 340pF.

V

S

L

+2

Input

PC Board Layout

50

45

40

35

30

25

20

15

10

5

The frequency response of this amplifier depends greatly on

the amount of care taken in designing the PC board. The

use of low inductance components such as chip resis-

tors and chip capacitors is strongly recommended,

while a solid ground plane is a must!

A_V= +1

Attention should be given to decoupling the power supplies.

A large value (10µF) tantalum in parallel with a small value

(0.1µF) chip capacitor works well in most cases.

A_V= +2

40

0

80 120 160 200 240 280 320 360 400

LOAD CAPACITANCE (pF)

Terminated microstrip signal lines are recommended at the

input and output of the device. Capacitance directly on the

output must be minimized, or isolated as discussed in the

next section.

FIGURE 1. RECOMMENDED SERIES OUTPUT RESISTOR vs.

LOAD CAPACITANCE

Evaluation Board

For unity gain applications, care must also be taken to

minimize the capacitance to ground seen by the amplifier’s

inverting input. At higher frequencies this capacitance will

tend to short the -INPUT to GND, resulting in a closed loop

gain which increases with frequency. This will cause

excessive high frequency peaking and potentially other

problems as well.

The performance of the HFA1113 may be evaluated using

the HFA11XX Evaluation Board, slightly modified as follows:

1. Remove the 500Ω feedback resistor (R2), and leave the

connection open.

2. A. For A = +1 evaluation, remove the 500Ω gain setting

V

resistor (R1), and leave pin 2 floating.

An example of a good high frequency layout is the Evalua-

tion Board shown in Figure 2.

B. For A = +2, replace the 500Ω gain setting resistor

V

with a 0Ω resistor to GND.

The layout and modified schematic of the board are shown

in Figure 2.

Driving Capacitive Loads

Capacitive loads, such as an A/D input, or an improperly

terminated transmission line will degrade the amplifier’s

phase margin resulting in frequency response peaking and

possible oscillations. In most cases, the oscillation can be

To order evaluation boards, please contact your local sales

office.

avoided by placing a resistor (R ) in series with the output

S

prior to the capacitance.

Spec Number 511106-883

206

HFA1113

DESIGN INFORMATION(Continued)

The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as

application and design information only. No guarantee is implied.

V+

BOTTOM LAYOUT

TOP LAYOUT

V_H

QP3

QP4

1

50K

(30K

QN2

+IN

R1

FOR

V_L)

OUT

V+

QP1

V

^LV-

Z

I_CLAMP

GND

+IN

+1

V-

V+

V_H

QN1

QN6

QP6

QN5

200Ω

∞ (A_V= +1)

or 0Ω (A_V= +2)

QP2

V_H

R1

1

2

3

4

8

7

6

5

QP5

0.1µF

50Ω

10µF

+5V

QN3

QN4

50Ω

IN

OUT

V_L

V_-IN

R_G

V-

300Ω

R_F= 300Ω

GND

0.1µF

10µF

(INTERNAL)

GND

-5V

V_OUT

-IN

FIGURE 2. EVALUATION BOARD SCHEMATIC AND LAYOUT

FIGURE 3. HFA1113 SIMPLIFIED V_HCLAMP CIRCUITRY

QP5 begins to conduct whenever the high impedance node

Clamp Operation

reaches a voltage equal to QP5’s base voltage + 2V (QP5

BE

General

and QN5). Thus, QP5 clamps node Z whenever Z reaches

V . R1 provides a pull-up network to ensure functionality

with the clamp inputs floating. A similar description applies to

The HFA1113 features user programmable output clamps to

limit output voltage excursions. Clamping action is obtained

by applying voltages to the V and V terminals (DIP pins 8

H

the symmetrical low clamp circuitry controlled by V .

L

H

L

& 5) of the amplifier. V sets the upper output limit, while V

H

L

When the output is clamped, the negative input continues to

sets the lower clamp level. If the amplifier tries to drive the

output above V , or below V , the clamp circuitry limits the

source a slewing current (I

) in an attempt to force the

CLAMP

H

L

output to the quiescent voltage defined by the input. QP5

must sink this current while clamping, because the -IN cur-

rent is always mirrored onto the high impedance node. The

clamping current is calculated as:

output voltage at V or V (± the clamp accuracy), respec-

H

L

tively. The low input bias currents of the clamp pins allow

them to be driven by simple resistive divider circuits, or

active elements such as amplifiers or DACs.

I

= (V - V

) / 300Ω + V / R .

CLAMP

-IN

OUT CLAMPED -IN G

As an example, a unity gain circuit with V = 2V, and V

=

H

Clamp Circuitry

IN

1V, would have I

= (2V-1V) / 300Ω + 2V / ∞ = 3.33mA

CLAMP

Figure 3 shows a simplified schematic of the HFA1113 input

(R = ∞ because -IN is floated for unity gain applications).

G

stage, and the high clamp (V ) circuitry. As with all current

H

Note that I

will increase by I

when the output is

CC

CLAMP

feedback amplifiers, there is a unity gain buffer (QX1 - QX2)

between the positive and negative inputs. This buffer forces

-IN to track +IN, and sets up a slewing current of:

clamp limited.

Clamp Accuracy

The clamped output voltage will not be exactly equal to the

(V - V

)/R + V / R .

-IN

OUT

F -IN G

This current is mirrored onto the high impedance node (Z) by

QX3-QX4, where it is converted to a voltage and fed to the

output via another unity gain buffer. If no clamping is utilized,

the high impedance node may swing within the limits defined

by QP4 and QN4. Note that when the output reaches it’s qui-

escent value, the current flowing through -IN is reduced to

voltage applied to V or V . Offset errors, mostly due to V

H

L

BE

mismatches, necessitate a clamp accuracy parameter which

is found in the device specifications. Clamp accuracy is a

function of the clamping conditions. Referring again to Figure

3, it can be seen that one component of clamp accuracy is the

V

mismatch between the QX6 transistors, and the QX5

BE

only that small current (-I

the final voltage.

) required to keep the output at

BIAS

transistors. If the transistors always ran at the same current

level there would be no V mismatch, and no contribution to

BE

Tracing the path from V to Z illustrates the effect of the the inaccuracy. The QX6 transistors are biased at a constant

H

clamp voltage on the high impedance node. V decreases current, but as described earlier, the current through QX5 is

H

by 2V (QN6 and QP6) to set up the base voltage on QP5.

equivalent to I

. V

increases as I

increases,

BE

CLAMP

BE

CLAMP

Spec Number 511106-883

207

HFA1113

DESIGN INFORMATION(Continued)

The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as

application and design information only. No guarantee is implied.

Recovery from Overdrive

causing the clamped output voltage to increase as well.

is a function of the overdrive level (A x V - V

OUT

I

CLAMP

VCL

IN

The output voltage remains at the clamp level as long as the

overdrive condition remains. When the input voltage drops

below the overdrive level (V

return to linear operation. A time delay, known as the Over-

drive Recovery Time, is required for this resumption of linear

operation. The plots of “Unclamped Performance” and

“Clamped Performance” highlight the HFA1113’s subnano-

second recovery time. The difference between the

unclamped and clamped propagation delays is the overdrive

recovery time. The appropriate propagation delays are 8.0ns

), so clamp accuracy degrades as the overdrive

CLAMPED

increases. As an example, the specified accuracy of ±100mV

for a 1.6X overdrive degrades to ±240mV for a 3X overdrive.

/ A

) the amplifier will

CLAMP

VCL

Consideration must also be given to the fact that the clamp

voltages have an affect on amplifier linearity. The “Nonlin-

earity Near Clamp Voltage” curve in the data sheet illus-

trates the impact of several clamp levels on linearity.

Clamp Range

Unlike some competitor devices, both V and V have usable for the unclamped pulse, and 8.8ns for the clamped (2X

H

L

ranges that cross 0V. While V must be more positive than overdrive) pulse yielding an overdrive recovery time of

H

V , both may be positive or negative, within the range restric- 800ps. The measurement uses the 90% point of the output

L

tions indicated in the specifications. For example, the transition to ensure that linear operation has resumed. Note:

HFA1113 could be limited to ECL output levels by setting The propagation delay illustrated is dominated by the fixtur-

V = -0.8V and V = -1.8V. V and V may be connected to ing. The delta shown is accurate, but the true HFA1113

H

L

H

L

the same voltage (GND for instance) but the result won’t be a propagation delay is 500ps.

DC output voltage from an AC input signal. A 150 - 200mV AC

signal will still be present at the output.

TYPICAL PERFORMANCE CHARACTERISTICS

Device Characterized at: V_SUPPLY= ±5V, A_V= +2V/V, R_L= 100Ω, Unless Otherwise Specified.

PARAMETERS

Output Offset Voltage

CONDITIONS

TEMPERATURE

+25^oC

TYPICAL

8

UNITS

mV

µV/^oC

µA

A

_V= +1, V

= 0V

CM

Average Offset Voltage Drift

+Input Current

Versus Temperature

A_V= +1, V = 0V

Full

10

+25^oC

25

CM

+Input Resistance

-Input Resistance

+Input Noise Voltage *

+Input Noise Current *

Input Common Mode Range

Input Capacitance

Gain

A_V= +1, ∆V

= 2V

+25^oC

50

kΩ

CM

+25^oC

300

9

Ω

f = 100kHz

+25^oC

nV/√Hz

pA/√Hz

V

+25^oC

37

Full

±2.8

2.2

+25^oC

pF

A_V= +1, V_IN= 2V

+25^oC

0.99

1.98

0.02

±3.3

±3.0

±60

±50

0.3

V/V

%

Gain

A

V

_V= +2, V_IN= 1V

+25^oC

DC Non-Linearity *

Output Voltage *

_OUT= ±2V Full Scale

+25^oC

A_V= -1, R_L= 100Ω

+25^oC

V

A

_V= -1, R_L= 100Ω

_V= -1, R_L= 50Ω

Full

V

Output Current *

A

+25^oC to +125^oC

-55^oC to 0^oC

+25^oC

mA

Ω

A_V= -1, R_L= 50Ω

DC Closed Loop Output Resistance

Quiescent Supply Current *

-3dB Bandwidth *

R_L= Open

Full

24

mA

MHz

A_V= -1, V_OUT= 200mV_P-P

+25^oC

800

850

550

A_V= +1, V_OUT= 200mV_P-P

+25^oC

A_V= +2, V_OUT= 200mV_P-P

+25^oC

^{Spec Number}511106-883

208

HFA1113

DESIGN INFORMATION(Continued)

The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as

application and design information only. No guarantee is implied.

TYPICAL PERFORMANCE CHARACTERISTICS (Continued)

Device Characterized at: V_SUPPLY= ±5V, A_V= +2V/V, R_L= 100Ω, Unless Otherwise Specified.

PARAMETERS

CONDITIONS

A_V= -1, V_OUT= 5V_P-P

_V= +1, V_OUT= 5V_P-P

TEMPERATURE

+25^oC

TYPICAL

2400

1500

1900

300

UNITS

V/µs

MHz

dB

Slew Rate

A

A_V= +2, V_OUT= 5V_P-P

A_V= -1, V_OUT= 5V_P-P

Full Power Bandwidth (Note 1)

Gain Flatness (Note 1)

A_V= +1, V_OUT= 5V_P-P

150

A_V= +2, V_OUT= 5V_P-P

220

To 30MHz, A_V= -1

±±0.02

±±0.10

±0.015

±0.05

±0.20

±0.036

±0.10

±0.07

±0.13

±0.83

±0.05

-52

To 30MHz, A_V= +1

dB

To 30MHz, A_V= +2

dB

Gain Flatness (Note 1)

To 50MHz, A_V= -1

dB

To 50MHz, A_V= +1

dB

To 50MHz, A_V= +2

dB

Gain Flatness (Note 1)

To 100MHz, A_V= -1

dB

To 100MHz, A_V= +2

dB

Linear Phase Deviation (Note 1)

To 100MHz, A_V= -1

Degrees

dBc

To 100MHz, A_V= +1

To 100MHz, A_V= +2

2nd Harmonic Distortion (Note 1)

3rd Harmonic Distortion (Note 1)

2nd Harmonic Distortion (Note 1)

3rd Harmonic Distortion (Note 1)

2nd Harmonic Distortion (Note 1)

3rd Harmonic Distortion (Note 1)

30MHz, A_V= -1, V_OUT= 2V_P-P

30MHz, A_V= +1, V_OUT= 2V_P-P

30MHz, A_V= +2, V_OUT= 2V_P-P

30MHz, A_V= -1, V_OUT= 2V_P-P

30MHz, A_V= +1, V_OUT= 2V_P-P

30MHz, A_V= +2, V_OUT= 2V_P-P

50MHz, A_V= -1, V_OUT= 2V_P-P

50MHz, A_V= +1, V_OUT= 2V_P-P

50MHz, A_V= +2, V_OUT= 2V_P-P

50MHz, A_V= -1, V_OUT= 2V_P-P

50MHz, A_V= +1, V_OUT= 2V_P-P

50MHz, A_V= +2, V_OUT= 2V_P-P

100MHz, A_V= -1, V_OUT= 2V_P-P

100MHz, A_V= +1, V_OUT= 2V_P-P

100MHz, A_V= +2, V_OUT= 2V_P-P

100MHz, A_V= -1, V_OUT= 2V_P-P

100MHz, A_V= +1, V_OUT= 2V_P-P

100MHz, A_V= +2, V_OUT= 2V_P-P

-57

-52

-71

-73

-72

-47

-53

-47

-63

-68

-65

-41

-50

-42

-55

-49

-62

Spec Number 511106-883

209

HFA1113

DESIGN INFORMATION(Continued)

The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as

application and design information only. No guarantee is implied.

TYPICAL PERFORMANCE CHARACTERISTICS (Continued)

Device Characterized at: V_SUPPLY= ±5V, A_V= +2V/V, R_L= 100Ω, Unless Otherwise Specified.

PARAMETERS

CONDITIONS

TEMPERATURE

+25^oC

TYPICAL

28

UNITS

dBm

dB

3rd Order Intercept (Note 1)

100MHz

300MHz

100MHz

300MHz

40MHz

13

1dB Compression (Note 1)

19

12

Reverse Isolation (S₁₂) (Note 1)

-70

-60

-32

500

480

700

12

100MHz

600MHz

dB

Rise and Fall Time

Overshoot (Note 1)

Settling Time (Note 1)

A

_V= -1, V_OUT= 0.5V_P-P

ps

A

_V= +1, V_OUT= 0.5V_P-P

ps

A_V= +2, V_OUT= 0.5V_P-P

A_V= -1, V_OUT= 0.5V_P-P

ps

%

A

_V= +1, V_OUT= 0.5V_P-P

45

%

A_V= +2, V_OUT= 0.5V_P-P

6

%

A_V= +2, to 0.1%, V_OUT= 2V to 0V

13

ns

A

_V= +2, to 0.05%, V_OUT= 2V to 0V

20

ns

A_V= +2, to 0.02%, V_OUT= 2V to 0V

36

ns

Differential Gain

A_V= +2, R_L= 150Ω, NTSC

0.02

0.04

0.75

±100

%

Differential Phase

A

_V= +2, R_L= 150Ω, NTSC

Degrees

ns

Overdrive Recovery Time, (2X Overdrive) V_IN= ±1V, V_H= +1V, V_L= -1V

Clamp Accuracy

A_V= -1, V_IN= ±1.6V, V_H= +1V,

mV

V_L= -1V

Clamped Overshoot

V_IN= ±1V, V_H= +1V, V_L= -1V,

+25^oC

7

%

Input t_R/ t_F= 2ns

Negative Clamp Range (V_L)

Positive Clamp Range (V_H)

Clamp Input Bias Current

Clamp Input Bandwidth

NOTE:

+25^oC

-5.0 to +2.0

-2.0 to +5.0

50

V

V_H= +1V, V_L= -1V

µA

MHz

V_IN= ±100mV, V_Hor V_L= 100mV_P-P

500

1. See Typical Performance Curves for more information.

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.

Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reli-

able. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may

result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

Spec Number 511106-883

210


型号：	HFA1113MJ/883
厂家：	Intersil
描述：	Output Limiting, Ultra High Speed Programmable Gain, Buffer Amplifier 输出限制，超高速可编程增益缓冲放大器缓冲放大器
文件：	总22页 (文件大小：551K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HFA1113MJ/883 [INTERSIL]

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