HFA1115IP [INTERSIL]
225MHz, Low Power, Output Limiting, Closed Loop Buffer Amplifier; 225MHz ，低功耗，输出限制，闭环缓冲放大器
| 型号： | HFA1115IP |
| 厂家： | 
Intersil |
| 描述： | 225MHz, Low Power, Output Limiting, Closed Loop Buffer Amplifier |
| 文件： | 总14页 (文件大小：162K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HFA1115
September 1998
File Number 3606.4
225MHz, Low Power, Output
Features
Limiting, Closed Loop Buffer Amplifier
• User Programmable Output Voltage Limiting
The HFA1115 is a high speed closed loop Buffer featuring both
user programmable gain and output limiting. Manufactured on
Intersil’s proprietary complementary bipolar UHF-1 process, the
HFA1115 also offers a wide -3dB bandwidth of 225MHz, very
fast slew rate, excellent gain flatness and high output current.
• High Input Impedance . . . . . . . . . . . . . . . . . . . . . . . 1MΩ
• Differential Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.02%
• Differential Phase . . . . . . . . . . . . . . . . . . . . 0.03 Degrees
• Wide -3dB Bandwidth (A = +2). . . . . . . . . . . . . .225MHz
V
This buffer is the ideal choice for high frequency applications
requiring output limiting, especially those needing ultra fast
overload recovery times. The limiting function allows the
designer to set the maximum positive and negative output
levels, thereby protecting later stages from damage or input
saturation. The HFA1115 also allows for voltage gains of +2,
+1, and -1, without the use of external resistors. Gain
selection is accomplished via connections to the inputs, as
described in the “Application Information” text. The result is a
more flexible product, fewer part types in inventory, and more
efficient use of board space.
• Very Fast Slew Rate (A = -1) . . . . . . . . . . . . . . 1135V/µs
V
• Low Supply Current . . . . . . . . . . . . . . . . . . . . . . . . 7.1mA
• High Output Current . . . . . . . . . . . . . . . . . . . . . . . . .60mA
• Excellent Gain Accuracy . . . . . . . . . . . . . . . . . . . 0.99V/V
• User Programmable For Closed-Loop Gains of +1, -1 or
+2 Without Use of External Resistors
• Fast Overdrive Recovery . . . . . . . . . . . . . . . . . . . . . <1ns
• Standard Operational Amplifier Pinout
Compatibility with existing op amp pinouts provides flexibility
to upgrade low gain amplifiers, while decreasing component
count. Unlike most buffers, the standard pinout provides an
upgrade path, should a higher closed loop gain be needed at
a future date. For Military product, refer to the HFA1115/883
data sheet.
Applications
• Flash A/D Drivers
• Video Cable Drivers
• High Resolution Monitors
• Professional Video Processing
• Medical Imaging
Pinout
HFA1115
(PDIP, SOIC)
TOP VIEW
• Video Digitizing Boards/Systems
• Battery Powered Communications
350
NC
-IN
+IN
V-
1
2
3
4
8
7
6
5
V
H
Ordering Information
350
_
+
V+
PART NUMBER
(BRAND)
TEMP.
RANGE ( C)
PKG.
NO.
o
PACKAGE
8 Ld PDIP
8 Ld SOIC
OUT
HFA1115IP
-40 to 85
E8.3
M8.15
V
L
HFA1115IB
(H1115I)
-40 to 85
Pin Descriptions
HFA11XXEVAL
High Speed Op Amp DIP Evaluation Board
NAME
PIN NUMBER
DESCRIPTION
NC
1
2
3
4
5
6
7
8
No Connection
Inverting Input
Non-Inverting Input
Negative Supply
Lower Output Limit
Output
-IN
+IN
V-
V
L
OUT
V+
Positive Supply
Upper Output Limit
V
H
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
HFA1115
Absolute Maximum Ratings
Thermal Information
o
Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Output Current (Note 2) . . . . . . . . . . . . . . . . Short Circuit Protected
Thermal Resistance (Typical, Note 1)
θJA ( C/W)
SUPPLY
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
130
170
o
ESD Rating
Maximum Junction Temperature (Die) . . . . . . . . . . . . . . . . . . . .175 C
Maximum Junction Temperature (Plastic Packages) . . . . . . .150 C
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C
o
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . .600V
o
o
o
Operating Conditions
(SOIC - Lead Tips Only)
o
o
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C
Supply Voltage Range (Typical). . . . . . . . . . . . . . . . . . . . 5V to 10V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
2. Output is protected for short circuits to ground. Brief short circuits to ground will not degrade reliability, however, continuous (100% duty cycle)
output current should not exceed 30mA for maximum reliability.
Electrical Specifications
V
= ±5V, A = +1, R = 100Ω, Unless Otherwise Specified
SUPPLY V L
(NOTE 3)
TEST
LEVEL
TEST
CONDITIONS
TEMP.
( C)
o
PARAMETER
INPUT CHARACTERISTICS
Output Offset Voltage
MIN
TYP
MAX
UNITS
A
A
B
A
A
A
A
A
A
A
A
B
A
A
A
A
A
C
C
A
A
B
B
25
Full
Full
25
-
-
2
3
10
mV
mV
15
o
Average Output Offset Voltage Drift
Common-Mode Rejection Ratio
-
22
45
44
45
49
48
48
1
70
µV/ C
∆V
∆V
∆V
= ±1.8V
= ±1.8V
= ±1.2V
42
40
40
45
43
43
-
-
dB
dB
dB
dB
dB
dB
µA
µA
CM
CM
CM
85
-
-40
25
-
Power Supply Rejection Ratio
Non-Inverting Input Bias Current
∆V = ±1.8V
PS
-
∆V = ±1.8V
PS
85
-
∆V = ±1.2V
PS
-40
25
-
15
25
80
1
Full
Full
25
-
3
o
Non-Inverting Input Bias Current Drift
-
30
0.5
-
nA/ C
Non-Inverting Input Bias Current Power
Supply Sensitivity
∆V = ±1.25V
PS
-
µA/V
µA/V
MΩ
Full
25
-
3
Non-Inverting Input Resistance
∆V
∆V
∆V
= ±1.8V
= ±1.8V
= ±1.2V
0.8
0.5
0.5
280
-
1.1
1.4
1.3
350
1.6
±2.4
±1.7
7
-
CM
CM
CM
85
-
MΩ
-40
25
-
MΩ
Inverting Input Resistance
Input Capacitance
420
-
Ω
25
pF
Input Voltage Common Mode Range
(Implied by V CMRR and +R Tests)
IO IN
25, 85
-40
25
±1.8
±1.2
-
-
V
-
V
Input Noise Voltage Density (Note 4)
f = 100kHz
f = 100kHz
-
nV/√Hz
pA/√Hz
Non-Inverting Input Noise Current Density
(Note 4)
25
-
3.6
-
2
HFA1115
Electrical Specifications
V
= ±5V, A = +1, R = 100Ω, Unless Otherwise Specified (Continued)
SUPPLY
V
L
(NOTE 3)
TEST
LEVEL
TEST
CONDITIONS
TEMP.
( C)
o
PARAMETER
TRANSFER CHARACTERISTICS
Gain
MIN
TYP
MAX
UNITS
A
= -1
A
A
A
A
A
A
25
Full
25
-0.98
-0.975
0.98
-0.996
-1.000
0.992
0.993
1.988
1.990
-1.02
-1.025
1.02
V/V
V/V
V/V
V/V
V/V
V/V
V
A
= +1
= +2
V
Full
25
0.975
1.96
1.025
2.04
A
V
Full
1.95
2.05
AC CHARACTERISTICS
-3dB Bandwidth
A
= -1
B
B
B
B
B
B
B
B
B
B
25
25
25
25
25
25
25
25
25
25
-
-
-
-
-
-
-
-
-
-
225
200
-
-
-
-
-
-
-
-
-
-
MHz
MHz
MHz
MHz
MHz
MHz
dB
V
(V
OUT
= 0.2V
, Note 4)
P-P
A
= +1, +R = 620Ω
V
S
A
= +2
= -1
225
V
Full Power Bandwidth
(V = 5V at A = +2/-1,
A
157
V
OUT
4V
P-P
V
A
= +1, +R = 620Ω
140
V
S
at A = +1, Note 4)
P-P
V
A
= +2
125
V
Gain Flatness
(to 25MHz, V
A
= +1, +R = 620Ω
±0.1
±0.04
±0.25
±0.1
V
S
= 0.2V
= 0.2V
, Note 4)
, Note 4)
OUT
P-P
A
= +2
dB
V
Gain Flatness
(to 50MHz, V
A
= +1, +R = 620Ω
dB
V
S
OUT
P-P
A
= +2
dB
V
OUTPUT CHARACTERISTICS
Output Voltage Swing (Note 4)
A
= -1, R = 100Ω
A
A
A
A
B
B
B
B
B
B
25
Full
25, 85
-40
25
±3.0
±3.2
±3.0
55
-
-
-
-
-
-
-
-
-
-
V
V
L
±2.8
V
Output Current (Note 4)
A
= -1, R = 50Ω
50
28
-
mA
mA
mA
Ω
V
L
42
Output Short Circuit Current
Output Resistance (Note 4)
Second Harmonic Distortion
90
DC, A = +2
V
25
-
0.07
-50
-45
-50
-45
10MHz
20MHz
10MHz
20MHz
25
-
dBc
dBc
dBc
dBc
(A = +2, V
= 2V )
P-P
V
OUT
25
-
Third Harmonic Distortion
(A = +2, V = 2V
25
-
)
P-P
V
OUT
25
-
TRANSIENT RESPONSE A = +2, Unless Otherwise Specified
V
Rise and Fall Times
(V = 0.5V , Note 4)
Rise Time
Fall Time
+OS
B
B
B
B
B
B
B
B
25
25
25
25
25
25
25
25
-
-
-
-
-
-
-
-
1.7
1.9
-
-
-
-
-
-
-
-
ns
ns
OUT P-P
Overshoot
(V = 0.5V
0
%
, V = 2.5ns)
t
OUT
P-P IN RISE
-OS
0
%
Slew Rate
(V = 5V
+SR
1660
1135
1125
800
V/µs
V/µs
V/µs
V/µs
, A = -1)
OUT
P-P
P-P
V
-SR (Note 5)
+SR
Slew Rate
(V = 4V
, A = +1, +R = 620Ω)
OUT
V
S
-SR (Note 5)
3
HFA1115
Electrical Specifications
V
= ±5V, A = +1, R = 100Ω, Unless Otherwise Specified (Continued)
SUPPLY
V
L
(NOTE 3)
TEST
LEVEL
TEST
CONDITIONS
TEMP.
( C)
o
PARAMETER
MIN
TYP
1265
870
23
MAX
UNITS
V/µs
V/µs
ns
Slew Rate
+SR
B
B
B
B
B
25
25
25
25
25
-
-
-
-
-
-
-
-
-
-
(V
= 5V , A = +2)
P-P V
OUT
-SR (Note 5)
To 0.1%
Settling Time
(V = +2V to 0V step, Note 4)
OUT
To 0.05%
To 0.02%
33
ns
45
ns
VIDEO CHARACTERISTICS
Differential Gain
f = 3.58MHz, A = +2,
B
B
25
25
-
-
0.02
0.03
-
-
%
V
R
= 150Ω
L
Differential Phase
f = 3.58MHz, A = +2,
Degrees
V
R
= 150Ω
L
OUTPUT LIMITING CHARACTERISTICS A = +2, V = +1V, V = -1V, Unless Otherwise Specified
V
H
L
Limit Accuracy (Note 4)
V
V
= ±1.6V, A = -1
A
B
B
B
A
C
Full
25
-125
-
-70
0.8
125
-
mV
ns
IN
IN
V
Overdrive Recovery Time (Note 4)
Negative Limit Range
= ±1V
25
-5.0 to +2.5
-2.5 to +5.0
85
V
Positive Limit Range
25
V
Limit Input Bias Current
Full
25
-
-
200
-
µA
MHz
Limit Input Bandwidth
100
POWER SUPPLY CHARACTERISTICS
Power Supply Range
C
A
A
25
25
4.5
6.6
-
-
5.5
7.1
7.3
±V
mA
mA
Power Supply Current (Note 4)
6.9
7.1
Full
NOTE:
3. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only.
4. See Typical Performance Curves for more information.
5. Slew rates are asymmetrical if the output swings below GND (e.g., a bipolar signal). Positive unipolar output signals have symmetric positive and
negative slew rates comparable to the +SR specification. See the “Application Information” section, and the pulse response graphs for details.
Application Information
the two gain setting resistors, which frees up board space for
termination resistors.
Relevant Application Notes
The following Application Notes pertain to the HFA1115:
Like most newer high performance amplifiers, the HFA1115
is a current feedback amplifier (CFA). CFAs offer high
bandwidth and slew rate at low supply currents, but can be
difficult to use because of their sensitivity to feedback
capacitance and parasitics on the inverting input (summing
node). The HFA1115 eliminates these concerns by bringing
the gain setting resistors on-chip. This yields the optimum
placement and value of the feedback resistor, while
minimizing feedback and summing node parasitics. Because
there is no access to the summing node, the PCB parasitics
do not impact performance at gains of +2 or -1 (see “Unity
Gain Considerations” for discussion of parasitic impact on
unity gain performance).
• AN9653-Use and Application of Output Limiting
Amplifiers
• AN9752-Sync Stripper and Sync Inserter for
Composite Video
These publications may be obtained from Intersil’s web site
(http://www.intersil.com) or via our AnswerFax system.
HFA1115 Advantages
The HFA1115 features a novel design which allows the user
to select from three closed loop gains, without any external
components. The result is a more flexible product, fewer part
types in inventory, and more efficient use of board space.
Implementing a gain of 2, cable driver with this IC eliminates
4
HFA1115
The HFA1115’s closed loop gain implementation provides
better gain accuracy, lower offset and output impedance,
and better distortion compared with open loop buffers.
frequencies, which prevents the increased output offset
voltage but delivers less gain flatness.
Another straightforward approach is to add a 620Ω resistor
in series with the positive input. This resistor and the
HFA1115 input capacitance form a low pass filter which rolls
off the signal bandwidth before gain peaking occurs. This
configuration was employed to obtain the datasheet AC and
transient parameters for a gain of +1.
Closed Loop Gain Selection
This “buffer” operates in closed loop gains of -1, +1, or +2, and
gain selection is accomplished via connections to the ±inputs.
Applying the input signal to +IN and floating -IN selects a gain
of +1 (see next section for layout caveats), while grounding -IN
selects a gain of +2. A gain of -1 is obtained by applying the
input signal to -IN with +IN grounded through a 50Ω resistor.
Non-inverting Input Source Impedance
For best operation, the DC source impedance seen by the
non-inverting input should be ≥50Ω. This is especially
important in inverting gain configurations where the non-
inverting input would normally be connected directly to GND.
The table below summarizes these connections:
CONNECTIONS
GAIN
(A )
V
+INPUT (PIN 3)
50Ω to GND
Input
-INPUT (PIN 2)
Pulse Undershoot and Asymmetrical Slew Rates
-1
+1
+2
Input
The HFA1115 utilizes a quasi-complementary output stage to
achieve high output current while minimizing quiescent supply
current. In this approach, a composite device replaces the
traditional PNP pulldown transistor. The composite device
switches modes after crossing 0V, resulting in added
distortion for signals swinging below ground, and an
increased undershoot on the negative portion of the output
waveform (see Figures 9, 13, and 17). This undershoot isn’t
present for small bipolar signals, or large positive signals.
Another artifact of the composite device is asymmetrical slew
rates for output signals with a negative voltage component.
The slew rate degrades as the output signal crosses through
0V (see Figures 9, 13, and 17), resulting in a slower overall
negative slew rate. Positive only signals have symmetrical
slew rates as illustrated in the large signal positive pulse
response graphs (see Figures 7, 11, and 15).
NC (Floating)
GND
Input
Unity Gain Considerations
Unity gain selection is accomplished by floating the -Input of
the HFA1115. Anything that tends to short the -Input to GND,
such as stray capacitance at high frequencies, will cause the
amplifier gain to increase toward a gain of +2. The result is
excessive high frequency peaking, and possible instability.
Even the minimal amount of capacitance associated with
attaching the -Input lead to the PCB results in approximately
3dB of gain peaking. At a minimum this requires due care to
ensure the minimum capacitance at the -Input connection.
.
TABLE 1. UNITY GAIN PERFORMANCE FOR VARIOUS
IMPLEMENTATIONS
±0.1dB
PEAK-
ING
(dB)
GAIN
FLATNESS
(MHz)
PC Board Layout
BW
(MHz)
+SR/-SR
(V/µs)
APPROACH
This amplifier’s frequency response depends greatly on the
care taken in designing the PC board. The use of low
inductance components such as chip resistors and chip
capacitors is strongly recommended, while a solid
ground plane is a must!
Remove Pin 2
2.5
0.6
0
400
170
165
1200/850
1125/800
1050/775
20
25
65
+R = 620Ω
S
+R = 620Ω and
S
Remove Pin 2
Attention should be given to decoupling the power supplies.
A large value (10µF) tantalum in parallel with a small value
(0.1µF) chip capacitor works well in most cases.
Short Pins 2, 3
0
200
190
875/550
900/550
45
19
100pF cap. be-
tween pins 2, 3
0.2
Terminated microstrip signal lines are recommended at the input
and output of the device. Capacitance directly on the output
must be minimized, or isolated as discussed in the next section.
Table 1 lists five alternate methods for configuring the
HFA1115 as a unity gain buffer, and the corresponding
performance. The implementations vary in complexity and
involve performance trade-offs. The easiest approach to
implement is simply shorting the two input pins together, and
applying the input signal to this common node. The amplifier
bandwidth drops from 400MHz to 200MHz, but excellent
gain flatness is the benefit. Another drawback to this
approach is that the amplifier input noise voltage and input
offset voltage terms see a gain of +2, resulting in higher
noise and output offset voltages. Alternately, a 100pF
capacitor between the inputs shorts them only at high
For unity gain applications, care must also be taken to
minimize the capacitance to ground at the amplifier’s
inverting input. At higher frequencies this capacitance tends
to short the -INPUT to GND, resulting in a closed loop gain
which increases with frequency. This causes excessive high
frequency peaking and potentially other problems as well.
An example of a good high frequency layout is the
Evaluation Board shown in Figure 2.
5
HFA1115
Driving Capacitive Loads
BOARD SCHEMATIC (MODIFIED)
= ∞ (A = +1) or 0Ω (A = +2)
Capacitive loads, such as an A/D input, or an improperly
terminated transmission line degrade the amplifier’s phase
margin resulting in frequency response peaking and
possible oscillations. In most cases, the oscillation can be
R
1
V
V
V
H
R
1
1
2
3
4
8
7
6
5
0.1µF
50Ω
10µF
+5V
50Ω
avoided by placing a resistor (R ) in series with the output
S
IN
OUT
prior to the capacitance.
V
L
Figure 1 details starting points for the selection of this
resistor. The points on the curve indicate the R and C
combinations for the optimum bandwidth, stability, and
10µF
0.1µF
GND
S
L
GND
-5V
settling time, but experimental fine tuning is recommended.
Picking a point above or to the right of the curve yields an
overdamped response, while points below or left of the curve
indicate areas of underdamped performance.
TOP LAYOUT
V
H
1
R
and C form a low pass network at the output, thus
L
S
limiting system bandwidth well below the amplifier bandwidth
+IN
of 200MHz (A = +1). By decreasing R as C increases (as
V
S
L
OUT
V-
V+
V
illustrated by the curves), the maximum bandwidth is
obtained without sacrificing stability. In spite of this,
bandwidth still decreases as the load capacitance increases.
L
GND
For example, at A = +1, R = 50Ω, C = 22pF, the overall
V
S
L
BOTTOM LAYOUT
bandwidth is 185MHz, but the bandwidth drops to 50MHz at
A = +1, R = 15Ω, C = 330pF.
V
S
L
50
45
40
35
30
25
20
15
10
5
A
= +1
V
FIGURE 2. EVALUATION BOARD SCHEMATIC (AFTER
MODIFICATION FOR BUFFER USE) AND LAYOUT
A
= +2
V
0
Limiting Operation
General
0
40
80 120 160 200 240 280 320 360 400
LOAD CAPACITANCE (pF)
The HFA1115 features user programmable output clamps to
limit output voltage excursions. Limiting action is obtained by
FIGURE 1. RECOMMENDED SERIES RESISTOR vs LOAD
CAPACITANCE
applying voltages to the V and V terminals (pins 8 and 5)
H
L
of the amplifier. V sets the upper output limit, while V sets
H
L
Evaluation Board
The performance of the HFA1115 may be evaluated using
the HFA11XX Evaluation Board, slightly modified as follows:
the lower limit level. If the amplifier tries to drive the output
above V , or below V , the clamp circuitry limits the output
H
L
voltage at V or V (± the limit accuracy), respectively. The
H
L
low input bias currents of the limit pins allow them to be
driven by simple resistive divider circuits, or active elements
such as amplifiers or DACs.
1. 1. Remove the 510Ω feedback resistor (R ), and leave the
2
connection open.
2. 2. a. For A = +1 evaluation, remove the 510Ω gain setting
V
resistor (R ), and leave pin 2 floating.
Limit Circuitry
1
b. For A = +2, replace the 510Ω gain setting resistor with
V
Figure 3 shows a simplified schematic of the HFA1115 input
stage, and the high limit (V ) circuitry. As with all current
feedback amplifiers, there is a unity gain buffer (Q - Q
between the positive and negative inputs. This buffer forces
-IN to track +IN, and sets up a slewing current of:
a 0Ω resistor to GND.
H
The layout and modified schematic of the board are shown
in Figure 2.
)
X1 X2
To order evaluation boards (Part Number HFA11XXEVAL),
please contact your local sales office.
I
= (V - V
)/R + V /R
-IN G
SLEW
-IN OUT
F
6
HFA1115
found in the device specifications. Limit accuracy is a
V+
function of the limiting conditions. Referring again to Figure
3, it can be seen that one component of limit accuracy is the
Q
Q
P4
P3
V
mismatch between the Q transistors, and the Q
X6 X5
BE
transistors. If the transistors always ran at the same current
Q
N2
R
50kΩ
1
level there would be no V mismatch, and no contribution
BE
Q
to the inaccuracy. The Q transistors are biased at a
X6
constant current, but as described earlier, the current
P1
V-
V+
Z
I
LIMIT
+IN
+1
through Q is equivalent to I
. V increases as I
X5
Limit BE LIMIT
200Ω
V
H
Q
increases, causing the limited output voltage to increase as
well. I is a function of the overdrive level
N1
Q
N6
Q
N5
LIMIT
((A x V - V
Q
P2
) / V
), so limit accuracy degrades as
Q
P6
V
IN
LIMIT LIMIT
the overdrive increases (see Figures 28 and 29). For
example, accuracy degrades from -20mV to +30mV when
Q
P5
Q
Q
N4
N3
the overdrive increases from 100% to 200% (A = +2,
V
V
= 500mV).
V
H
-IN
V-
R
= 350Ω
Consideration must also be given to the fact that the limit
voltages have an effect on amplifier linearity. The “Linearity
Near Limit Voltage” curves, Figures 30 and 31, illustrate the
impact of several limit levels on linearity.
R
= 350Ω
F
G
(INTERNAL)
(INTERNAL)
V
OUT
-IN
FIGURE 3. HFA1115 SIMPLIFIED V LIMIT CIRCUITRY
H
Limit Range
This current is mirrored onto the high impedance node (Z) by
-Q , where it is converted to a voltage and fed to the
Unlike some competitor devices, both V and V have
Q
H
L
X3 X4
usable ranges that cross 0V. While V must be more
positive than V , both may be positive or negative, within
L
output via another unity gain buffer. If no limiting is utilized,
the high impedance node may swing within the limits defined
H
the range restrictions indicated in the specifications. For
example, the HFA1115 could be limited to ECL output
levels by setting V = -0.8V and V = -1.8V. V and V may
be connected to the same voltage (GND for instance) but
the result won’t be a DC output voltage from an AC input
signal. A 150mV - 200mV AC signal will still be present at
the output.
by Q and Q . Note that when the output reaches its
quiescent value, the current flowing through -IN is reduced to
P4 N4
only that small current (-I
the final voltage.
) required to keep the output at
H
L
H
L
BIAS
Tracing the path from V to Z illustrates the effect of the limit
H
voltage on the high impedance node. V decreases by 2V
H
BE
(Q and Q ) to set up the base voltage on Q . Q
N6 P6 P5 P5
Recovery from Overdrive
begins to conduct whenever the high impedance node
reaches a voltage equal to Q ’s base voltage + 2V (Q
The output voltage remains at the limit level as long as the
overdrive condition remains. When the input voltage drops
P5
BE
P5
and Q ). Thus, Q limits node Z whenever Z reaches V .
N5 P5
H
R provides a pull-up network to ensure functionality with the
limit inputs floating. A similar description applies to the
symmetrical low limit circuitry controlled by V .
L
below the overdrive level (V
/A ) the amplifier returns to
1
LIMIT
V
linear operation. A time delay, known as the Overdrive
Recovery Time, is required for this resumption of linear
operation. Overdrive recovery time is defined as the
When the output is limited, the negative input continues to
difference between the amplifier’s propagation delay exiting
limiting and the amplifier’s normal propagation delay, and it is
a strong function of the overdrive level. Figure 32 details the
overdrive recovery time for various limit and overdrive levels
source a slewing current (I
output to the quiescent voltage defined by the input. Q
must sink this current while limiting, because the -IN current
is always mirrored onto the high impedance node. The
limiting current is calculated as:
) in an attempt to force the
Limit
P5
Benefits of Output Limiting
The plots of “Pulse Response Without Limiting” and “Pulse
Response With Limiting” (Figures 4 and 5) highlight the
advantages of output limiting. Besides the obvious benefit of
constraining the output swing to a defined range, limiting the
output excursions also keeps the output transistors from
saturating, which prevents unwanted saturation artifacts
from distorting the output signal. Output limiting also takes
advantage of the HFA1115’s ultra-fast overdrive recovery
time, reducing the recovery time from 2.5ns to 0.5ns, based
on the amplifier’s normal propagation delay of 1.2ns.
I
= (V - V
)/R + V /R .
-IN
LIMIT
-IN OUT LIMITED
F
G
As an example, a unity gain circuit with V = 2V, and V = 1V,
IN
would have I
because -IN is floated for unity gain applications). Note that I
increases by I
LIMIT
H
= (2V - 1V)/350Ω + 2V/∞ = 2.8mA (R = ∞
LIMIT
G
CC
when the output is limited.
Limit Accuracy
The limited output voltage will not be exactly equal to the
voltage applied to V or V . Offset errors, mostly due to V
mismatches, necessitate a limit accuracy parameter which is
H
L
BE
7
HFA1115
o
Typical Performance Curves V
= ±5V, T = 25 C, R = 100Ω, Unless Otherwise Specified
SUPPLY
A
L
A
= +2
IN
A
= +2
V
V
4.0
3.0
2.0
1.5
2.0
1.5
1.0
0.5
0
IN
OUT
2.0
1.0
0
2.0
1.0
1.0
0.5
OUT
0
0
-0.5
-1.0
-1.0
-0.5
-1.0
-2.0
-1.0
V
= +2.0V, V = 0V
L
H
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 4. PULSE RESPONSE WITHOUT LIMITING
FIGURE 5. PULSE RESPONSE WITH LIMITING
300
3.0
2.5
A
= +2
A
= +2
V
V
250
200
150
2.0
1.5
100
1.0
50
0
0.5
0
-50
-0.5
-1.0
-100
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 6. SMALL SIGNAL POSITIVE PULSE RESPONSE
FIGURE 7. LARGE SIGNAL POSITIVE PULSE RESPONSE
2.0
200
A
= +2
A
= +2
V
V
1.5
150
100
50
1.0
0.5
0
0
-0.5
-1.0
-1.5
-2.0
-50
-100
-150
-200
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 8. SMALL SIGNAL BIPOLAR PULSE RESPONSE
FIGURE 9. LARGE SIGNAL BIPOLAR PULSE RESPONSE
8
HFA1115
o
Typical Performance Curves V
= ±5V, T = 25 C, R = 100Ω, Unless Otherwise Specified (Continued)
SUPPLY
A
L
300
3.0
2.5
A
= +1
A
= +1
V
V
250
200
150
2.0
1.5
1.0
0.5
100
50
0
0
-0.5
-1.0
-50
-100
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 10. SMALL SIGNAL POSITIVE PULSE RESPONSE
FIGURE 11. LARGE SIGNAL POSITIVE PULSE RESPONSE
200
2.0
A
= +1
V
A
= +1
V
150
1.5
1.0
0.5
0
100
50
0
-50
-0.5
-1.0
-1.5
-2.0
-100
-150
-200
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 12. SMALL SIGNAL BIPOLAR PULSE RESPONSE
FIGURE 13. LARGE SIGNAL BIPOLAR PULSE RESPONSE
3.0
300
A
= -1
A
= -1
V
V
2.5
2.0
1.5
1.0
0.5
0
250
200
150
100
50
0
-50
-0.5
-1.0
-100
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 14. SMALL SIGNAL POSITIVE PULSE RESPONSE
FIGURE 15. LARGE SIGNAL POSITIVE PULSE RESPONSE
9
HFA1115
o
Typical Performance Curves V
= ±5V, T = 25 C, R = 100Ω, Unless Otherwise Specified (Continued)
SUPPLY
A
L
200
2.0
1.5
A
= -1
A = -1
V
V
150
100
50
1.0
0.5
0
0
-50
-100
-0.5
-1.0
-1.5
-2.0
-150
-200
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 16. SMALL SIGNAL BIPOLAR PULSE RESPONSE
FIGURE 17. LARGE SIGNAL BIPOLAR PULSE RESPONSE
A
= +1
V
= 200mV
A = +2
V
V
OUT
P-P
V
= 1V
P-P
OUT
3
0
3
0
GAIN
GAIN
-3
-6
-3
-6
V
= 2.5V
P-P
A
= +2
OUT
V
PHASE
PHASE
V
= 4V
P-P
A
= -1
OUT
V
0
0
90
90
V
= 4V
P-P
OUT
A
= -1
V
= 2.5V
V
OUT
P-P
180
270
360
180
270
360
V
= 1V
P-P
OUT
A
= +1
V
A
= +2
V
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 18. FREQUENCY RESPONSE
FIGURE 19. FREQUENCY RESPONSE FOR VARIOUS OUTPUT
VOLTAGES
A
= +1
V
= 1V
A = -1
V
V
OUT
P-P
V
= 1V
P-P
OUT
3
0
3
GAIN
GAIN
0
-3
-6
V
= 2.5V
= 4V
OUT
P-P
-3
-6
V
V
= 2.5V
P-P
OUT
P-P
OUT
PHASE
PHASE
V
= 4V
OUT
P-P
0
0
90
90
V
= 4V
= 2.5V
V
= 4V
P-P
OUT
P-P
P-P
OUT
V
V
= 2.5V
OUT
OUT
P-P
= 1V
180
270
360
180
270
360
V
= 1V
V
OUT
P-P
OUT
P-P
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 20. FREQUENCY RESPONSE FOR VARIOUS OUTPUT
VOLTAGES
FIGURE 21. FREQUENCY RESPONSE FOR VARIOUS OUTPUT
VOLTAGES
10
HFA1115
o
Typical Performance Curves V
= ±5V, T = 25 C, R = 100Ω, Unless Otherwise Specified (Continued)
SUPPLY
A
L
260
250
240
230
220
210
200
190
180
170
A
= +1, V
OUT
= 4V
P-P
V
A
= -1
V
3
0
A
= +2
V
-3
-6
-9
A
= +2, V
OUT
= 5V
P-P
A
= +1
V
V
A
= -1, V
OUT
= 5V
P-P
V
-75
-50
-25
0
25
50
o
75
100
125
1
10
100
1000
TEMPERATURE ( C)
FREQUENCY (MHz)
FIGURE 22. FULL POWER BANDWIDTH
FIGURE 23. -3dB BANDWIDTH vs TEMPERATURE
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
V
= 200mV
P-P
OUT
0.4
0.3
0.2
0.1
0
A
= -1
V
A
= +1
V
A
= -1
V
A
= +2
-0.1
-0.2
-0.3
-0.4
V
A
= +1
V
A
= +2
V
1
10
FREQUENCY (MHz)
100
1
10
100
1000
FREQUENCY (MHz)
FIGURE 24. GAIN FLATNESS
FIGURE 25. REVERSE ISOLATION (S
)
12
A
= +2
V
0.1
1K
100
10
0.05
0.025
0
1
-0.025
-0.05
0.1
0.01
-0.1
0.3
1
10
100
1000
3
13 23
33 43
53
63
73
83
93 103
FREQUENCY (MHz)
TIME (ns)
FIGURE 26. OUTPUT RESISTANCE
FIGURE 27. SETTLING TIME RESPONSE
11
HFA1115
o
Typical Performance Curves V
= ±5V, T = 25 C, R = 100Ω, Unless Otherwise Specified (Continued)
SUPPLY
A
L
150
100
50
150
A
= +2
A
= +2
V
V
V
= -500mV
L
100
50
V
= +500mV
H
V
= -1.0V
L
V
= +1V
H
0
-50
0
V
= -2.0V
L
-50
-100
-150
V
= +2.0V
H
-100
-150
0
100
200
300
400
500
0
100
200
300
400
500
OVERDRIVE (% OF V )
H
OVERDRIVE (% OF V )
L
FIGURE 28. V LIMIT ACCURACY vs OVERDRIVE
FIGURE 29. V LIMIT ACCURACY vs OVERDRIVE
L
H
2.0
1.8
1.6
1.4
1.2
2.0
A
= +1
A
= +2
V
V
1.8
1.6
1.4
V
= -2V
V
= +2V
V = +2V
H
L
V
= -2V
H
L
1.2
V
L
= -1V
V
L
= -1V
V = +1V
H
V
= +1V
H
1.0
0.8
0.6
0.4
0.2
1.0
0.8
0.6
0.4
0.2
0
V
= -500mV
V = +500mV
H
L
V
= -500mV
V
= +500mV
L
H
0
-2.0
-1.5
-1.0
-0.5
0
0.5
1.0
1.5
2.0
-2.0
-1.0
-0.5
0
0.5
1.0
1.5
2.0
-1.5
A
x V (V)
A
x V (V)
V
IN
V IN
FIGURE 30. LINEARITY NEAR LIMIT VOLTAGE
FIGURE 31. LINEARITY NEAR LIMIT VOLTAGE
4.0
3.6
A
= -1
A
= +2
|-V
OUT
| (R = 100Ω)
L
V
V
V
= -2V
L
3.5
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
+V
OUT
(R = 100Ω)
L
V
= +2V
H
3.4
3.3
3.2
3.1
|-V
OUT
| (R = 50Ω)
L
V
= -1V
L
+V
OUT
(R = 50Ω)
L
V
= -3V
L
3.0
2.9
V
= +1V
H
2.8
2.7
2.6
V
= +3V
H
0
100
200
300
400
-50
-25
0
25
50
75
100
125
OVERDRIVE (% OF V OR V )
o
H
L
TEMPERATURE ( C)
FIGURE 32. OVERDRIVE RECOVERY TIME vs OVERDRIVE
FIGURE 33. OUTPUT VOLTAGE vs TEMPERATURE
12
HFA1115
o
Typical Performance Curves V
= ±5V, T = 25 C, R = 100Ω, Unless Otherwise Specified (Continued)
SUPPLY
A
L
7.1
7.0
6.9
6.8
6.7
2.2
2.1
2.0
1.9
1.8
1.7
1.6
V
= 500mV
P-P
OUT
A
= +2
V
FALL TIMES
RISE TIMES
A
= -1
V
A
= +1
V
A
= +2
V
A
= -1
V
A
= +1
V
A
= +2
V
4.0
4.5
5.0
5.5
6.0
6.5
7.0
-75
-50
-25
0
25
50
o
75
100
125
SUPPLY VOLTAGE (±V)
TEMPERATURE ( C)
FIGURE 34. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 35. RISE AND FALL TIMES vs TEMPERATURE
100
100
E
NI
10
10
I
NI
1
100
1
0.1
1
10
FREQUENCY (kHz)
FIGURE 36. INPUT NOISE CHARACTERISTICS
13
HFA1115
Die Characteristics
DIE DIMENSIONS:
SUBSTRATE POTENTIAL (Powered Up):
59 mils x 58.2 mils x 19 mils
Floating (Recommend Connection to V-)
1500µm x 1480µm x 483µm
PASSIVATION:
METALLIZATION:
Type: Nitride
Type: Metal 1: AICu(2%)/TiW
Thickness: 4kÅ ±0.5kÅ
Thickness: Metal 1: 8kÅ ±0.4kÅ
TRANSISTOR COUNT:
Type: Metal 2: AICu(2%)
Thickness: Metal 2: 16kÅ ±0.8kÅ
89
Metallization Mask Layout
HFA1115
-IN
V
H
V+
OUT
+IN
V-
V
L
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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14
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