HI1-7151T-2 [INTERSIL]
10-Bit, High Speed, A/D Converter with Track and Hold; 10位，高速，A / D转换器和跟踪保持
| 型号： | HI1-7151T-2 |
| 厂家： | 
Intersil |
| 描述： | 10-Bit, High Speed, A/D Converter with Track and Hold |
| 文件： | 总17页 (文件大小：829K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
HI-7151
10-Bit, High Speed, A/D Converter
with Track and Hold
December 1997
Features
Description
• Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 10µs The Intersil HI-7151 is a high speed 10-bit A/D converter
which uses a 2-Step Flash algorithm to achieve throughput
rates of 100kHz. A unique switched capacitor technique
• Continuous Throughput Rate. . . . . . . . . . . . . . . 100kHz
allows a new input voltage to be sampled while a conversion
is taking place.
• No Offset or Gain Adjustments Necessary
• Internal Track and Hold Amplifier
A Track and Hold amplifier is included on the chip, consisting
of two high speed amplifiers and an internal hold capacitor.
• Analog and Reference Inputs Fully Buffered
• µP Compatible Byte Organized Outputs
Microprocessor bus interfacing is simplified by the use of
standard Chip Select, Read, and Write control signals. The
digital three-state outputs are byte organized for interfacing
the either 8- or 16-bit systems. An Over-Range pin, together
with the MSB, can be used to indicate an out-of-range
condition.
• Low Power Consumption . . . . . . . . . . . . . . . . . .150mW
• Uses a Single 2.5V Reference for ±2.5 V Input Range
Applications
The HI-7151 operates with ±5V supplies. A single +2.5V
reference is required to provide a bipolar input range from
-2.5V to +2.5V.
• µP Controlled Data Acquisition Systems
• DSP
Internal high speed CMOS buffers at both the analog and
reference inputs simplify external drive requirements.
- Avionics
- Sonar
Ordering Information
• Process Control
PART
NUMBER
LINEARITY
(MAX. DLE) RANGE ( C)
TEMP.
- Automotive Transducer Sensing
- Industrial
o
PACKAGE
28 Ld PDIP
HI3-7151J-5
HI3-7151K-5
HI3-7151A-9
HI3-7151B-9
HI1-7151S-2
HI1-7151T-2
±1 LSB
0 to 75
0 to 75
0 to 85
0 to 85
• Robotics
1
± / LSB
28 Ld PDIP
28 Ld PDIP
28 Ld PDIP
2
• Digital Communications
• Image Processing
±1 LSB
1
± / LSB
2
±1 LSB
-55 to 125 28 Ld CERDIP
-55 to 125 28 Ld CERDIP
1
± / LSB
2
HI-7151
(PDIP, CERDIP)
TOP VIEW
Pinout
28 V+
27 OVR
26 D9
25 D8
24 D7
23 D6
22 D5
21 D4
GND
V-
1
2
3
4
5
6
7
8
9
V
REF
AG
V
IN
SET
BUSY
CLK
HOLD
20
D3
19 D2
WR 10
CS 11
18 D1
RD 12
17 D0
SMODE 13
DG 14
16 HBE
15 BUS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 3099.1
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1
HI-7151
Functional Diagram
(+)
(-)
REF
AMP
(33)
17
D0
DATA
V
REF
REF
3
4
5
INVERT
OUTPUTS
LATCHES
AND
OUTPUT
BUFFERS
TWO
STEP
FLASH
AG
RESISTOR
LADDER
(ANALOG GROUND)
D9
26
27
7
OVR
INPUT
BUFFER
AMP
V
BUSY
IN
(ANALOG INPUT)
BUS
HBE
BUS
CTRL
15
16
(1)
TRACK
HOLD
AMP
HOLD
RD
9
12
10
11
13
V+
V-
WR
CS
28
2
POWER
SUPPLY
DISTRIBUTION
CONTROL
LOGIC
GND
1
SMODE
DG
14
(DIGITAL GROUND)
CLK
SET
8
6
2
HI-7151
Pin Descriptions
PIN
1
NAME
GND
V-
DESCRIPTION
Ground return for comparators (0V).
Negative supply voltage input (-5V).
Reference voltage input (+2.5V).
Analog ground reference (0V).
Analog Input Voltage.
2
3
V
REF
4
AG
5
V
IN
6
SET
Connect to V+ for proper operation.
7
BUSY Output High-Conversion complete. Output Low - Conversion in progress. Output floats when chip is not selected (RD
and CS both high).
8
CLK
Clock input.
9
HOLD Indicates start of conversion. Active low.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
WR
CS
RD
Write input. With CS low, starts conversion when pulsed low; continuous conversions when kept low.
Chip select input. Active low.
Read input. With CS low, enables output buffers when pulsed low; outputs updated at end of conversion when kept low.
SMODE Slow memory mode input. Active high.
DG
BUS
HBE
D0
Digital ground (0V).
Bus select input. High = all outputs enabled together D0 - D9, OVR. Low = outputs enabled by HBE.
Byte select (HBE/LBE) input for 8-bit bus. Input high-High byte select, D8-D9, OVR Input low-low byte select, D0-D7.
Bit 0 (Least significant, LSB).
D1
Bit 1.
Bit 2.
D2
D3‘
D4
Bit 3.
Low
Byte
Bit 4.
Output Data Bits
(High = True)
D5
Bit 5.
D6
Bit 6.
D7
Bit 7.
D8
Bit 8 (Most Significant).
High
Byte
D9
Bit 9 (Sign).
OVR
V+
Out of Range flag. Valid at end of conversion when output exceeds full scale.
Positive supply voltage input (+5V).
3
HI-7151
Absolute Maximum Ratings (Note 1)
Thermal Information
o
o
Supply Voltage
Thermal Resistance (Typical)
θ
( C/W)
θ
( C/W)
JA
JC
V+ to Gnd (DG/AG/GND) . . . . . . . . . . . . . . . . -0.3V < V+ < +5.7V
V- to Gnd (DG/AG/GND). . . . . . . . . . . . . . . . . .-5.7V < V- < +0.3V
PDIP Package . . . . . . . . . . . . . . . . . . .
CERDIP Package . . . . . . . . . . . . . . . .
__
__
N/A
__
Analog Input Pins . . . . . . . . . . . . . . . . . V- -0.3V < V
Digital I/O Pins . . . . . . . . . . . . . . . . . . .DG - 0.3V < V < V+ +0.3V
< V+ +0.3V
Maximum Power Dissipation (Note 2). . . . . . . . . . . . . . . . . <500mW
INA
I/O
o
o
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
o
Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300 C
Operating Conditions
Temperature Range
HI3-7151X-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 C to 75 C
HI3-7151X-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C
o
o
o
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Input voltages may exceed the supply voltage provided the inputs current is limited to ±1mA.
o
o
2. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board (derate above 75 C at -10mW/ C).
Electrical Specifications V+ = +5V, V- = -5V, V
= 2.5V, f = 300kHz, 50% Duty Cycle, Unless Otherwise Specified (Note 4)
CLK
REF
J, A GRADE
K, B GRADE
TYP
(NOTE 3)
TEMPERATURE
PARAMETER
ACCURACY
SYMBOL
RES
MIN
TYP
MAX
MIN
MAX
UNITS
o
Resolution (Note 5) (With
no missing codes)
T
T
T
T
T
T
T
T
T
T
= -25 C
10
10
-
-
-
-
10
10
-
-
-
Bits
Bits
A
to T
o
-
-
-
MIN
MAX
Integral Linearity Error
Differential Linearity Error
Bipolar Offset Error
Unadjusted Gain Error
NOTE:
ILE
= 25 C
±0.5
±0.75
-
±1.0
±1.0
±1.0
±1.0
±2.5
±3.0
±2.5
±3.0
±0.3
±0.5
-
±-0.5
±0.75
±0.5
±0.75
±1.5
±2.0
±1.5
±2.0
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
A
to T
o
-
-
MIN
MAX
DLE
= 25 C
-
-
A
to T
o
-
-
-
-
MIN
MAX
V
= 25 C
-
±1.0
±1.5
±1.0
±1.5
-
±0.6
±1.0
±0.6
±1.0
OS
A
to T
o
-
-
MIN
MAX
eG+ and
eG-
= 25 C
-
-
A
to T
-
-
MIN
MAX
3. T
to T : See Ordering Information Table.
MAX
MIN
o
DC Electrical Specifications V+ = 5V, V- = -5V, V
= 2.5V, T = 25 C, f
= 300kHz, 50% Duty Cycle,
REF
A
CLK
Unless Otherwise Specified
o
o
o
o
o
25 C
0 C to 75 C
-40 C to 85 C
(NOTE 4)
PARAMETER
ANALOG INPUT
SYMBOL
CONDITIONS
MIN
TYP
MAX
MIN MAX
MIN MAX
UNITS
Analog Input Range
V
V
= 0V
-V
REF
-
0.01
8
V
-V
REF
V
-V
REF
V
REF
V
IR
IN
REF
REF
Analog INput Bias Current
I
-
-
100
20
-
-
100
-
-
-
100
-
nA
pF
BI
Analog Input Capacitance
(Note 5)
CV
IN
REFERENCE INPUT
Reference Input Range
(Note 6)
V
V
= 2.5V
2.2
2.5
2.6
2.2
2.6
2.2
2.6
V
RR
REF
Reference Input Bias Current
I
-
-
0.01
7
100
20
-
-
100
-
-
-
100
-
nA
pF
BR
Reference Input Capacitance
(Note 5)
CV
R
4
HI-7151
o
DC Electrical Specifications V+ = 5V, V- = -5V, V
= 2.5V, T = 25 C, f = 300kHz, 50% Duty Cycle,
CLK
REF
A
Unless Otherwise Specified (Continued)
o
o
o
o
o
25 C
0 C to 75 C
-40 C to 85 C
(NOTE 4)
PARAMETER
TRACK AND HOLD (See Text)
Slew Rate
SYMBOL
CONDITIONS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
SR
-
-
-
-
-
-
9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V/µs
MHz
ns
Bandwidth
BW
1.5
30
2
Aperture Time
Aperture Uncertainty
Feedthrough in HOLD
Acquisition Time
ns
f
= 100kHz
-80
1.5
dB
IN
µs
LOGIC INPUTS
Input High Voltage
Input Low Voltage
Logic Input Current
Input Capacitance (Note 5)
LOGIC OUTPUTS
Output High Voltage
Output Low Voltage
Output Leakage Current
V
2.0
-
-
-
2.0
-
0.8
1
2.0
-
0.8
1
V
V
IH
V
-
-
-
0.8
1
-
-
-
-
-
-
IL
IL
I
V
= 0V, V+
0.05
5
µA
pF
IN
C
17
-
-
IN
V
I
I
= -200µA
2.4
-
-
-
0.4
1
2.4
-
0.4
10
-
2.4
-
0.4
10
-
V
OH
OH
V
= 1.6mA
-
-
-
-
-
-
V
OL
OL
OL
I
RD = V+, V
RD = V+, V
= V+
= 0V
0.04
-0.01
7
µA
µA
pF
OUT
OUT
-1
-
-
-10
-
-10
-
Output Capacitance (Note 5)
C
High-Z State
15
-
-
OUT
POWER SUPPLY VOLTAGE RANGE
(Note 7)
V+
V-
Function Operation
Only
4.5
5.0
5.5
4.5
5.5
4.5
5.5
V
V
(Note 7)
-4.5
-5.0
-5.5
-4.5
-5.5
-4.5
-5.5
POWER SUPPLY REJECTION
V+, V- Gain Coefficient
eGVS
V+ = 5V, V- = -4.75V,
-5.25V
-
-
-
-
±0.1
±0.1
±0.1
±0.1
±0.05
±0.5
±0.5
±0.5
-
-
-
-
±0.6
±0.6
±0.6
±0.6
-
-
-
-
±0.6
±0.6
±0.6
±0.6
LSB
LSB
LSB
LSB
V- = -5V, V+ = 4.75V,
5.25V
V+, V- Offset Coefficient
VOSVS V+ = 5V, V- = -4.75V,
-5.25V
V- = -5V, V+ = 4.75V,
5.25V
SUPPLY CURRENTS
V+ Supply Current
V- Supply Current
GND Current
I+
I-
V+ = 5V ±10%
V- = -5V ±10%
-
-
-
-
-
20
-10
-8
30
-15
-15
-3
-
-
-
-
-
30
-15
-15
-3
-
-
-
-
-
30
-15
-15
-3
mA
mA
mA
mA
µA
V
= 0V, Digital
IN
Outputs are
Unloaded
I
GND
DG Current
I
-2
DG
AG
AG Current
I
0.02
10
10
10
NOTES:
4. FSR (Full Scale Range) = 2 X V
(5V at V
REF
= 2.5V). LSB (Least Significant Bit) = FSR/1024 (4.88mV at V
= 2.5V)
REF
REF
5. Parameter not tested. Parameter guaranteed by design, simulation, or characterization.
6. Only V and GAIN ERROR functionality tested at 2.2V and 2.6V.
OS
7. Guaranteed by functionality test.
5
HI-7151
o
AC Electrical Specifications V+ = 5V ±10%, V- = -5V ±10%, V
= 2.5V, T = 25 C, f
= 300kHz, 50% Duty Cycle,
REF
A
CLK
C
= 100pF (including stray for D0 - D9, OVR, HOLD, BUSY), Unless Otherwise Specified (Note 11)
L
o
o
o
o
o
25 C
0 C to 75 C
-40 C to 85 C
PARAMETER
Clock Input Duty Cycle
SYMBOL NOTES MIN
TYP
MAX
55
MIN
45
-
MAX
55
MIN
45
-
MAX
55
UNITS
%
D
5
9
45
-
50
-
Continuous Conversion Time
t
3tck
10
3tck
10
3tck
10
µs
SPS
9
60
-
-
60
-
60
-
µs
Slow Memory Mode Conversion
Time
t
CONV
5, 8
-
4tck
+0.9
4tck
+0.9
4tck
+0.9
µs
Continuous Throughput
t
9
-
-
f
/3
-
f
/3
-
f
/3/
sps
CYC
CLK
CLK
CLK
3
CLOCK Period
t
-
5
-
1/f
CLK
-
-
-
-
-
CK
CLOCK to HOLD Rise Delay
WR Pulse Width
WR to HOLD Delay
Busy to Data
t
CKHR
150
290
500
tck/2
170
200
-
140
525
tck/2
200
230
-
120
525
tck/2
200
230
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
5, 8, 10
5, 8
5, 8
5, 8
5, 9
5, 9
5, 13
5, 14
5
200
113
80
40
-
225
225
WRL
t
-
-
-
HOLD
t
-
-
-
BD
WR to RD Active
CLOCK to HOLD Fall Delay
HOLD to DATA change
RD LO to Active
RD HI to Inactive
HBE to DATA
t
100
100
100
WRD
CKHF
DATA
t
t
50
125
200
75
25
70
95
35
50
45
250
400
150
60
40
90
-
275
550
190
80
25
70
-
275
550
190
80
100
t
-
-
-
-
-
-
-
RD
t
-
-
RX
AD
CD
t
150
180
200
100
100
-
165
210
200
125
120
-
165
210
200
125
120
CS to DATA
t
5
-
-
RD to BUSY
t
5
-
-
BUSY
Rise Time
t
5, 12
5, 12
-
-
r
f
Fall Time
t
-
-
NOTES:
8. Slow memory mode timing.
9. Fast memory or DMA mode of operation, except the first conversion which is equal to t
10. Maximum specification to prevent multiple triggering with WR.
.
CONV
11. All input drive signals are specified with t = t ≤ 20ns and shall swing from V -0.4V to V +0.4V for all timing specifications. A signal is
IL IH
r
f
considered to change state as it crosses a 1.4V threshold (except t
and t ).
RD
RX
12. t and t load is C = 100pF (including stray capacitance) to DG and is measured from the 10 - 90% point.
r
f
L
13. t
is the time required for the data output level to change by 10% in response to RD crossing a voltage level of 1.4V. High-Z to V
is
RD
OH
is measured with R = 2.5kΩ to V+ and C = 100pF
measured with R = 2.5kΩ and C = 100pF (including stray) to DG. High-Z to V
L
L
OL
L
L
(including stray) to DG.
14. trx is the time required for the data output level to change by 10% in response to RD crossing a voltage level of 1.4V. V
to High-Z is
to High-Z is measured with R = 2.5 kΩ to V+ and C = 10pF
OH
measured with R = 2.5kΩ and C = 10pF (including stray) to DG. V
L
L
OL
L
L
(including stray) to DG.
6
HI-7151
Timing Diagrams
SMODE = +V, BUS = V+, HBE = V+ OR DG
0
t
CK
1
2
3
4
5
6
7
CLOCK
CS
WR
t
t
CKHR
WRL
HOLD
TRACK N
HOLD N
HOLD
TRACK N+1
t
INTERNAL
DATA
N DATA
RD
t
WRD
t
BUSY
BUSY
t
BD
D0-D9, OVR
DATA
N DATA
t
CONV
FIGURE 1A. SLOW MEMORY MODE (16-BIT DATA BUS)
7
HI-7151
Timing Diagrams (Continued)
SMODE = DG, BUS = DG
0
1
2
3
4
5
6
7
CLOCK
t
CD
CS
t
SPS
WR
(WR MAY BE WIRED LOW)
t
t
t
CKHF
CKHR
TRACK N+2
HOLD
HOLD N
HOLD N+1
HOLD N+2
HOLD
TRACK N
TRACK N+1
TRACK N+3
t
DATA
INTERNAL
DATA
N DATA
N+1 DATA
RD
HBE
(HBE/LBE)
t
RD
t
AD
t
RX
D0-D9, OVR
DATA
HIGH
BYTE
LOW
BYTE
HIGH
BYTE
LOW
BYTE
N DATA
N+1 DATA
BUSY
FIGURE 1B. FAST MEMORY MODE (8-BIT DATA BUS)
SMODE = +V: RD, WR, AND CS = DG
0
1
2
3
4
5
6
7
CLOCK
TRACK N
HOLD N
TRACK N+1
N-1 DATA
HOLD N+1
TRACK N+2
N DATA
HOLD N+2
HOLD
INTERNAL
DATA
N+1 DATA
BUSY
D0-D9, OVR
DATA
N-1 DATA
N DATA
N+1 DATA
FIGURE 1C. DMA MODE
8
HI-7151
5 TO 32
DECODER
(+V
)
REF
AZ
AZ
-
33
LATCH
LATCH
AZ
AZ
V
+
REF
17
26
3
DO
DATA
AZ
32
REF(+)
AMP
1R
OUTPUTS
LATCHES
AND
AZ
AZ
32 TO 5
ENCODER
OUTPUT
OUTPUT
BUFFERS
D9
BUFFERS
AZ
AZ
OVR
1R
27
7
-
BUSY
2
1
LATCH
LATCH
AZ
AZ
AG
+
4
BUS
HBE
BUS
CTRL
REF(+)
AMP
15
16
AZ
SCAZ
SCAZ
(-V
)
REF
HOLD
RD
SCAZ
9
SCAZ
(AG)
12
10
11
13
WR
CS
C
-
CONTROL
LOGIC
HOLD
-
-
+
SCAZ 32C
(-V
SMODE
+
V
+
HOLD
AMP
IN
C
H
SWITCHED
5
TRACK
BUFFER
AMP
CAP
AMP
(ANALOG INPUT)
)
CLK
SET
(AG)
REF
8
6
V+
28
2
V-
GND
DG
POWER
SUPPLY
DISTRIBUTION
1
14
(DIGITAL GROUND)
FIGURE 2. DETAILED BLOCK DIAGRAM
9
HI-7151
The 5-bit result of the first flash conversion is latched into the
Detailed Description
upper five bits of double buffered latches. It is also converted
back into an analog signal by choosing the ladder voltage
which is closest to but less than the input voltage. The
selected voltage (VTAP) is then subtracted from the input
voltage. This residue is amplified by a factor of 32 and
The HI-7151 is a high speed 10-bit A/D converter which
achieves throughput rates of 100kHz by use of a Two Step
Flash algorithm. A pipelined operation has been achieved
through the use of switched capacitor techniques which
allow the device to sample a new input voltage while a
conversion is taking place. The HI-7151 requires a single
reference input of +2.5V, which is internally inverted to -
2.5V, thereby allowing an input range of -2.5V to +2.5V. 10
bits including sign are two’s complement coded. The analog
and reference inputs are internally buffered by high speed
CMOS buffers, which greatly simplifies the external analog
drive requirements for the device.
referenced to the negative reference voltage (VSCA = (V
-
IN
-). This subtraction and amplification
VTAP) X 32 + V
REF
operation is performed by a Switched Capacitor Amplifier
(SCA). The output of the SCA falls between the positive and
negative reference voltages and can therefore be digitized
by the original 5-bit flash converter (second flash
conversion).
The 5-bit result of the second flash conversion is latched into
the lower five bits of double buffered latches. At the end of a
conversion, 10 bits of data plus an Out of Range bit are
latched into the second level of latches and can then be put
on the digital output pins.
A/D Section
The HI-7151 uses a conversion algorithm which is generally
called a “Two Step Flash” algorithm. This algorithm enables
very fast conversion rates without the penalty of high power
dissipation or high cost. A detailed functional diagram is
presented in Figure 2.
The conversion takes place in three clock cycles and is
illustrated in Figure 3. When the conversion begins, the track
and hold goes into its hold mode for 1 clock cycle. During the
first half clock cycle the comparator array is in its auto-zero
mode and it samples the input voltage. During the second
half clock cycle, the comparators make a comparison
between the input voltage and the ladder voltages. At the
beginning of the third half clock cycle, the first most
significant 5-bit result becomes available. During the first
clock cycle, the SCA was sampling the input voltage. After
the first flash result becomes available and a ladder tap
voltage has been selected the SCA amplifies the residue
between the input and ladder tap voltages. During the next
three half clock cycles, while the SCA output is settling to its
required accuracy, the comparators go into their auto-zero
mode and sample this voltage. During the sixth half clock
cycle, the comparators perform another comparison whose
5-bit result becomes available on the next clock edge.
The input voltage is first converted into a 5-bit result (plus
Out of Range information) by the flash converter. This flash
converter consists of an array of 33 auto-zeroed compara-
tors which perform a comparison between the input voltage
and subdivisions of the reference voltage. These subdivi-
sions of the reference voltage are formed by forcing the ref-
erence voltage and its negative on the two ends of a string of
32 resistors.
The reference input to the HI-7151 is buffered by a high
speed CMOS amplifier which is used to drive one end of the
resistor string. Another high speed amplifier configured in
the inverting unity gain mode inverts the reference voltage
with respect to analog ground and forces in onto the other
end of the resistor string. Both reference amplifiers are offset
trimmed at the factory in order to increase the accuracy of
the HI-7151 and to simplify its usage.
T CONVERSION
T + 1 CONVERSION
CLOCK
1
2
3
4
5
6
TRACK & HOLD
HOLD V (T)
IN
TRACK V (T + 1)
IN
HOLD V (T + 1)
IN
CONVERT
UPPER
5 BITS
CONVERT
LOWER
5 BITS
COMPARATOR
AUTO-ZERO
(AZ)
SAMPLE
(T)
SAMPLE RESIDUAL
SAMPLE
V
V
(T + 1)
IN
IN
SCA AUTO-ZERO
(SCAZ)
SAMPLE V (T)
IN
AMPLIFY RESIDUAL
SAMPLE V (T + 1)
IN
INTERNAL DATA
10-BITS + OVR
V
(T) DATA
IN
FIGURE 3. INTERNAL ADC TIMING DIAGRAM
10
HI-7151
TABLE 1. A/D OUTPUT CODE TABLE
ANALOG INPUT
) / 1024
OUTPUT DATA
LSB = 2 (V
V
= 2.500V
OVR
SIGN 9 MSB 8
7
0
1
0
0
1
0
0
6
0
1
0
0
1
0
0
5
0
1
0
0
1
0
0
4
0
1
0
0
1
0
0
3
0
1
0
0
1
0
0
2
0
1
0
0
1
0
0
1
0
1
0
0
1
0
0
LSB 0
REF
REF
≥ +V
2.500V to V+ (+OVR)
2.49512V (+Full Scale)
0.00488V
1
0
0
0
0
0
1
0
0
0
0
1
1
1
0
1
0
0
1
0
0
0
1
1
0
1
0
0
REF
+V
- 1 LSB
REF
+1 LSB
0
0.000V
-1 LSB
-0.00488V
-V
-2.500V (-Full Scale)
-2.50488V to V- (-OVR)
REF
REF
≤ -V
- 1 LSB
All of the internal amplifiers are offset trimmed at the factory
to give improved accuracy and to minimize the number of
external components. If necessary, offset error can be
adjusted either at an external interface buffer or by using
digital post correction.
Track and Hold Analog Input
A Track and Hold amplifier has been fully integrated on the
front end of the A/D converter. Because of the sampling
nature of this A/D converter, the input is required to stay
constant only during the first clock cycle. Therefore, the
Track and Hold (T/H) amplifier “holds” the input voltage only
during the first clock cycle and it acquires the input voltage
for the next conversion during the remaining two clock
cycles. The high input impedance of the T/H input amplifier
Reference Input
The reference input to the HI-7151 is buffered by a high
speed CMOS amplifier. The reference input range is 2.2V to
2.6V.
simplifies analog interfacing. Input signals up to ±V
can
REF
be directly connected to the A/D without buffering. The A/D
output code table is shown in Table 1.
Power Requirements
The timing signals for the Track and Hold amplifier are
generated internally, and are also provided externally
(HOLD) for synchronization purposes. The T/H amplifier
consists of two high speed CMOS amplifiers and an internal
hold capacitor. Its typical slew rate and bandwidth are 9V/µs
and 1.5MHz respectively. It is configured to give a very small
hold pedestal without the use of an external hold capacitor.
The hold pedestal is typically less than 100µV.
Power to the chip should be applied in the following order:
V-, V+, and V
. In applications where V+ is supplied prior
REF
to V-, the positive supply current will be approximately 2
times its nominal value until V- is applied (this is not a
latchup condition).
Initialization
In fast memory and DMA modes (after proper power, V
,
Acquisition of the analog input signal is the time required by
the T/H for its output to reach its final value within a specified
error band. This time is a function of the logic delay time, op
amp slewing time, and settling time. The T/H is in the track
mode for 2 clock cycles (6.7µs at CLK = 300kHz) but the out-
REF
and clock) up to 6 clock cycles are required for circuit initial-
ization. After circuit initialization, valid data will be available
in 3 clock cycles.
1
put typically settles to within / LSB in 1.5µs.
Microprocessor Interface
4
Aperture delay time is the time required for the T/H switch to
open following the internal hold command. This is the delay
with respect to falling edge of WR and the internal hold
command. It is equal to Thold (type) - 50ns (typ) which is
typically 30ns.
The HI-7151 can be interfaced to microprocessors through
the use of standard Write, Read, Chip Select, and HBE
control pins. The digital outputs are two’s complement
coded, three-state gated, and byte organized for bus
interface with 8- and 16-bit systems. The digital outputs (D0 -
D9, OVR, and BUSY) may be accessed under control of
BUS, byte enable input HBE, chip select, and read inputs for
a simple parallel bus interface. The microprocessor can read
the current data in the output latches in typically 75ns/byte
(trd). An over range pin (OVR) together with the MSB (D9)
pin set to either a logic 0 or 1 will indicate a positive or
negative over-range condition respectively. All digital output
buffers are capable of driving one TTL load.
Aperture uncertainty (jitter) is a range of variation in the
aperture time. The greater the aperture time the larger the
uncertainty in the analog voltage being converted. If the
aperture time is nulled out by advancing the hold command
(WR) or the signal is repetitively sampled, aperture uncer-
tainty becomes the major source of time error. The aperture
uncertainty for the T/H is typically 2ns which sets the maxi-
mum input bandwidth to 77.7kHz for 1 LSB resolution.
n
f
= 1/(π X 2 X ta),
The HI-7151 can be interfaced to a microprocessor using
one of three modes: slow memory, fast memory, and DMA
mode.
MAX
where n = resolution in bits,
ta = aperture uncertainty
11
HI-7151
TABLE 3. FAST MEMORY MODE I/O TRUTH TABLE
Slow Memory Mode
(SMODE = DG)
In slow memory mode, the conversion will be initiated by the
microprocessor by selecting the chip (CS) and pulsing WR
low. This mode is selected by hardwiring the SMODE pin to
V+. This mode is intended for use with microprocessors
(such as the 8086) which can be forced into a WAIT state.
For example, in configuration where the BUSY output is tied
to the 8086 READY input, an attempt to read the data before
the conversion is complete will force the processor into a
WAIT state until BUSY goes high, at which time the data at
the output is valid. This resembles a 10µs access time RAM.
It allows the processor to initiate a conversion, WAIT, and
READ data with a single READ instruction. When the 8-bit
bus operation is selected, high and low byte data may be
accessed in either order. An I/O truth table is presented in
Table 2 for the slow memory mode of operation.
CS WR RD BUS HBE
FUNCTION
X
0
X
X
X
Continuous Conversion, WR
May Be Tied to DG
1
X
X
X
X
Disables Only The RD
Command
0
0
X
X
0
0
1
0
X
1
D0 - D9 & OVR Enabled
High Byte Enabled: D8 - D9,
OVR (Enable 1st)
0
X
X
0
1
0
0
Low Byte Enabled: D0 - D7
(Must Enable 2nd)
X
X
X
Disables All Outputs
(High Impedance)
TABLE 2. SLOW MEMORY MODE I/O TRUTH TABLE
(SMODE = V+)
NOTE: X = Don’t Care
DMA Mode
CS WR RD BUS HBE
FUNCTION
This mode is a complete hardware mode where the HI-7151
continuously converts. The user implements hardware to
store the results in memory, bypassing the microprocessor.
This mode is recognized by the chip when SMODE is
hardwired to V+ and CS, RD, WR are hardwired to DG.
When 8-bit bus operation is selected, high and low byte data
may be accessed in either order. BUSY is continuously low
when accessed with a read command in this mode. An I/O
truth table is presented in Table 4 for the DMA mode of
operation.
0
1
0
0
0
0
X
X
X
X
X
X
0
0
0
X
X
1
0
0
X
X
X
0
Initiates a Conversion
Disables All Chip Commands
D0 - D9 and OVR Enabled
Low Byte Enabled: D0 - D7.
1
High Byte Enabled: D8 - D9,
OVR
X
X
1
X
X
Disables All Outputs
(High Impedance)
TABLE 4. DMA MODE I/O TRUTH TABLE
(SMODE = V+, CS = WR, RD = DG)
NOTE: X = Don’t Care
BUS
HBE
FUNCTION
Fast Memory Mode
1
0
0
X
0
1
D0 - D9 and OVR Enabled
Low Byte Enabled: D0 - D7
High Byte Enabled: D8 - D9, OVR
The fast memory mode of operation is selected by tying the
SMODE and WR pins to DG. In this mode, the chip performs
continuous conversions and only CS and RD are required to
read the data. Whenever the SMODE pin is low, WR is
independent of CS in starting a conversion cycle. During the
first conversion cycle, HOLD follows WR going low.
NOTE: X = Don’t Care
Optimizing System Performance
Data can be read a byte at a time or all 11 bits at once. The
internal logic disables the output latches from being updated
during a read after the high byte data is accessed. It will
continue to be disabled until after the low byte data is
accessed. THEREFORE, WHEN 8-BIT BUS OPERATION
IS SELECTED, THE DATA MUST BE ACCESSED HIGH
BYTE FIRST, LOW BYTE NEXT. If the low byte is accessed
first followed by high byte, the results from the next conver-
sion cycle will be lost because the updating of the output
latch is disabled. BUSY is continuously low when accessed
with a read command in this mode. An I/O truth table is pre-
sented in Table 3 for the fast memory mode of operation.
The HI-7151 has three ground pins (AG, DG, GND) for
improved system accuracy. Proper grounding and bypassing
is illustrated in Figure 4. The AG pin is a ground pin that
does not carry any current and is used internally as a refer-
ence ground. The reference input and analog input should
be referenced to the analog ground (AG) pin. The digital
inputs and outputs should be referenced to the digital ground
(DG) pin. The GND pin is a return point for the supply current
of the comparator array. The comparator array is designed
such that this current is approximately constant at all times
and does not vary with input voltage. By virtue of the
switched capacitor nature of the comparators, it is necessary
to hold GND firmly at zero volts at all times. Therefore, the
system ground star connection should be located as close to
this pin as possible.
The data can be defined in time by monitoring the HOLD pin.
The conversion data can be read after HOLD has gone low.
12
HI-7151
As in any analog system, good supply bypassing is Figure 8 illustrates an application where the HI-7151 is used
necessary in order to achieve optimum system performance with an analog multiplexer to form a multi-channel data
(minimize conversion errors). The power supplies should be acquisition system. Either slow memory or fast memory
bypassed with at least a 20µF tantalum and 0.1µF ceramic modes of operation can be selected. Fast memory mode
capacitors to GND. The reference input should be bypassed should be selected for maximum throughput. Multiplexer
with a 0.1µF ceramic capacitor to AG. The capacitor leads channel acquisition should occur approximately 500ns after
should be as short as possible.
HOLD goes high. This allows 2 clocks minus 0.5µs for the
input to settle. With a 300kHz clock the input has up to 6.2µs
to settle.
The pins on the HI-7151 are arranged such that the analog
pins are well isolated from the digital pins. In spite of this
arrangement, there is always pin to pin coupling. Therefore An intelligent system which performs
a scale factor
the analog inputs to the device should not be driven from adjustment under software control with the addition of a
very high output impedance sources. PC board layout programmable gain block between the multiplexer and
should screen the analog and reference inputs with AG. HI-7151 is illustrated in Figure 9. The microprocessor first
Using a soldier mask is good practice and helps reduce performs a conversion and then checks the over-range
leakage due to moisture contamination on the PC board.
status (OVR) bit. If the OVR bit is high, the microprocessor
addresses a precision gain circuit for scale factor adjustment
and initiates another conversion. The microprocessor must
keep track of the selected scale factor.
Applications
Typical applications are illustrated in Figures 5 through 7 for
the slow memory, fast memory, and DMA modes of
operation. The output data is configured for 16-bit bus oper-
ation of these three applications. By tying BUS and DG and
connecting the HBE input to the system address decoder,
the output data can be configured for 8-bit bus systems.
The accuracy of the programmable gain amplifier should be
better than 0.05%. For optimum system performance, op
amp frequency response, settling time, and charge injection
of the analog switch must be considered.
Figure 10 illustrates the HI-7151 interfaced to FIFO
memories for use in DMA applications.
20µF
-
0.1µF
5V
P.S.
+
+
+
HI-7151
2.5V
P.S.
-5V
P.S.
V+ 28
OVR 27
D9 26
D8 25
D7 24
D6 23
D5 22
D4 21
1 GND
2 V-
0.1µF
20µF
-
-
3
V
REF
4 AG
5 V
0.1µF
ANALOG INPUT
V+
IN
6 SET
7 BUSY
8 CLK
20
9 HOLD
10 WR
D3
D2 19
D1 18
D0 17
11 CS
12 RD
16
13 SMODE
14 DG
HBE
BUS 15
FIGURE 4. GROUND AND POWER SUPPLY DECOUPLING
13
HI-7151
HI-7151
+5V
V+ 28
OVR 27
D9 26
D8 25
D7 24
D6 23
D5 22
D4 21
1 GND
2 V-
-5V
+2.56V
0V
3
V
REF
4 AG
5 V
IN
ANALOG INPUT
V+
6 SET
7 BUSY
8 CLK
9 HOLD
10 WR
11 CS
300kHz CLOCK
20
D3
D2 19
D1 18
D0 17
12 RD
16
13 SMODE
14 DG
HBE
BUS 15
CS
WR
HOLD
TRACK N
HOLD N
TRACK N+1
INTERNAL
DATA
N DATA
RD
BUSY
D0-D9, OVR
DATA
N DATA
FIGURE 5. SLOW MEMORY MODE APPLICATION
14
HI-7151
HI-7151
+5V
V+ 28
OVR 27
D9 26
D8 25
D7 24
D6 23
D5 22
D4 21
1 GND
2 V-
-5V
+2.56V
0V
3
V
REF
4 AG
5 V
IN
ANALOG INPUT
V+
6 SET
7 BUSY
8 CLK
300kHz CLOCK
20
9 HOLD
10 WR
D3
D2 19
D1 18
D0 17
11 CS
12 RD
16
13 SMODE
14 DG
HBE
BUS 15
DATA
CS
WR
(WR MAY BE WIRED LOW)
HOLD N
HOLD N+1
HOLD N+2
HOLD
TRACK N
TRACK N+1
TRACK N+2
TRACK N+3
INTERNAL
DATA
N DATA
N+1 DATA
RD
D0-D9, OVR
DATA
N DATA
N+1 DATA
BUSY
FIGURE 6. FAST MEMORY MODE APPLICATION
15
HI-7151
HI-7151
+5V
1 GND
2 V-
V+ 28
OVR 27
D9 26
D8 25
D7 24
D6 23
-5V
+2.56V
0V
3
V
REF
4 AG
5 V
IN
ANALOG INPUT
V+
6 SET
7 BUSY
8 CLK
9 HOLD
10 WR
D5
22
D4 21
20
300kHz CLOCK
D3
D2 19
D1 18
11 CS
V+
D0 17
12 RD
13 SMODE
14 DG
HBE 16
BUS 15
TRACK N
HOLD N
TRACK N+1
HOLD N+1
TRACK N+2
N DATA
HOLD N+2
HOLD
INTERNAL
DATA
D0-D9, OVR
N-1 DATA
N+1 DATA
10µs
FIGURE 7. DMA MODE APPLICATION
ADDRESS BUS
DG
ADDRESS
DECODER
ADDRESS
DECODER
BUS
HBE
ANALOG
INPUTS
WR
V
IN
CS
RD
S1
S2
S3
S4
S5
S6
S7
S8
V+
V-
DG
V
REF
AG
V+
+2.56V
WR
HI-7151
ADC
(SLOW MEMORY MODE)
MICROPROCESSOR
DG528
MUX
SIGNAL
GROUND
SMOD
HOLD
BUSY
CLK
V+
+5V
-5V
RS
SYSTEM
RESET
V-
DG
300kHz
CLOCK
A0-A2, EN
SET
GND
V+
D0-D7
D8-D9, OVR
8-BIT DATA BUS
FIGURE 8. MULTI-CHANNEL DATA ACQUISITION SYSTEM
16
ADDRESS BUS
ADDRESS
DECODER
ADDRESS
DECODER
DG
BUS
HBE
CS
ANALOG
INPUTS
WR
V
IN
CS
RD
D
PROGRAMMBLE
GAIN AMP
S1
S2
S3
S4
S5
S6
S7
S8
V+
V-
DG
V
REF
AG
V+
+2.56V
WR
HI-7151
ADC
(SLOW MEMORY MODE)
MICROPROCESSOR
DG528
MUX
SIGNAL
GROUND
SMOD
HOLD
BUSY
CLK
V+
+5V
-5V
RS
SYSTEM
RESET
V-
DG
300kHz
CLOCK
D0-D2, EN
SET
GND
V+
D0-D7
D8-D9, OVR
8-BIT DATA BUS
FIGURE 9. MULTI-CHANNEL DATA ACQUISITION SYSTEM WITH PROGRAMMABLE GAIN
V+
BUS
HBE
SMODE
TO PARALLEL
DATA BUS
D0-D3
64 x 4-BIT
FIFO
V
IN
ANALOG INPUT
D8-D9, OVR
V
REF
AG
V+
+2.56V
SET
HI-7151
ADC
V+
SIGNAL
GROUND
CLK
D4-D7
64 x 4-BIT
FIFO
COMPOSITE
OUTPUT
READY
300kHz
HOLD
+5V
-5V
V-
BUSY
DG
RD
WR
CS
D8-D9, OVR
64 x 4-BIT
FIFO
GND
SHIFT IN
SHIFT
OUT
DG
FIGURE 10. DMA/FIFO DATA ACQUISITION SYSTEM
17
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