HI1-774J-5 [INTERSIL]
Complete, 12-Bit A/D Converters with Microprocessor Interface; 完整的12位与微处理器接口的A / D转换器
| 型号： | HI1-774J-5 |
| 厂家： | 
Intersil |
| 描述： | Complete, 12-Bit A/D Converters with Microprocessor Interface |
| 文件： | 总18页 (文件大小：202K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HI-574A, HI-674A,
HI-774
Complete, 12-Bit A/D Converters
with Microprocessor Interface
August 1997
Features
Description
• Complete 12-Bit A/D Converter with Reference and Clock
• Full 8-Bit, 12-Bit or 16-Bit Microprocessor Bus Interface
• Bus Access Time . . . . . . . . . . . . . . . . . . . . . . . . . . 150ns
• No Missing Codes Over Temperature
The HI-X74(A) is a complete 12-bit, Analog-to-Digital
Converter, including a +10V reference clock, three-state out-
puts and a digital interface for microprocessor control. Succes-
sive approximation conversion is performed by two monolithic
dice housed in a 28 lead package. The bipolar analog die fea-
tures the Intersil Dielectric Isolation process, which provides
enhanced AC performance and freedom from latch-up.
• Minimal Setup Time for Control Signals
• Fast Conversion Times
Custom design of each IC (bipolar analog and CMOS digital)
has yielded improved performance over existing versions of
this converter. The voltage comparator features high PSRR
plus a high speed current-mode latch, and provides precise
decisions down to 0.1 LSB of input overdrive. More than 2X
reduction in noise has been achieved by using current
instead of voltage for transmission of all signals between the
analog and digital ICs. Also, the clock oscillator is current
controlled for excellent stability over temperature.
- HI-574A (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25µs
- HI-674A (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15µs
- HI-774 (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9µs
• Digital Error Correction (HI-774)
• Low Noise, via Current-Mode Signal
Transmission Between Chips
• Byte Enable/Short Cycle (A Input)
O
- Guaranteed Break-Before-Make Action, Eliminating
Bus Contention During Read Operation. Latched by
Start Convert Input (To Set the Conversion Length)
The HI-X74(A) offers standard unipolar and bipolar input
ranges, laser trimmed for specified linearity, gain and offset
accuracy. The low noise buried zener reference circuit is
trimmed for minimum temperature coefficient.
• Supply Voltage . . . . . . . . . . . . . . . . . . . . . ±12V to ±15V
Power requirements are +5V and ±12V to ±15V, with typical
dissipation of 385mW (HI-574A/674A) and 390mW (HI-774) at
12V. All models are available in sidebrazed DIP, PDIP, and
CLCC. For additional HI-Rel screening including 160 hour burn-
in, specify “-8” suffix. For MIL-STD-883 compliant parts, request
HI-574A/883, HI-674A/883, and HI-774/883 data sheets.
Applications
• Military and Industrial Data Acquisition Systems
• Electronic Test and Scientific Instrumentation
• Process Control Systems
Pinouts
(PDIP, SBDIP)
TOP VIEW
(CLCC)
TOP VIEW
+5V SUPPLY, V
LOGIC
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
STATUS, STS
DB11 MSB
DB10
DATA MODE SEL, 12/8
3
CHIP SEL, CS
BYTE ADDR/SHORT
4
DB9
CYCLE, A
O
44
43 42 41 40
6
5
4
3
2
1
5
DB8
READ/CONVERT, R/C
CHIP ENABLE, CE
7
39
38
NC
NC
NC
NC
6
DB7
8
DIGITAL
+12V/+15V SUPPLY, V
CC
7
DATA
DB6
DB5
DB4
DB3
DB2
DB1
DB0
READ CONVERT, R/C
9
37 DB9
OUTPUTS
10
11
12
DB8
DB7
DB6
DB5
DB4
DB3
NC
+10V REF, REF OUT
8
CHIP ENABLE, CE
36
35
34
33
32
31
30
29
+15V SUPPLY, V
CC
+10V REFERENCE,
REF OUT
ANALOG
COMMON, AC
9
10
11
12
REFERENCE INPUT
ANALOG COMMON, AC 13
-12V/-15V SUPPLY, V
EE
REFERENCE INPUT,
14
REF IN
-15V SUPPLY, V
EE
BIPOLAR OFFSET
BIP OFF
15
10V INPUT 13
NC 16
BIPOLAR OFFSET,
LSB
DIG COMMON,
DC
17
DB2
14
20V INPUT
BIP OFF
18 19 20 21 22 23 24 25 26 27 28
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 3096.4
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
6-952
HI-574A, HI-674A, HI-774
Ordering Information
TEMPERATURE RANGE
o
PART NUMBER
HI3-574AJN-5
HI3-574AKN-5
HI3-574ALN-5
HI1-574AJD-5
HI1-574AKD-5
HI1-574ALD-5
HI1-574ASD-2
HI1-574ATD-2
HI1-574AUD-2
HI1-574ASD/883
HI1-574ATD/883
HI1-574AUD/883
HI4-574ASE/883
HI4-574ATE/883
HI4-574AUE/883
HI3-674AJN-5
HI3-674AKN-5
HI3-674ALN-5
HI1-674AJD-5
HI1-674AKD-5
HI1-674ALD-5
HI1-674ASD-2
HI1-674ATD-2
HI1-674AUD-2
HI1-674ASD/883
HI1-674ATD/883
HI1-674AUD/883
HI4-674ASE/883
HI4-674ATE/883
HI4-674AUE/883
HI3-774J-5
INL
( C)
PACKAGE
28 Ld PDIP
PKG. NO.
E28.6
±1.0 LSB
±0.5 LSB
±0.5 LSB
±1.0 LSB
±0.5 LSB
±0.5 LSB
±1.0 LSB
±0.5 LSB
±0.5 LSB
±1.0 LSB
±0.5 LSB
±0.5 LSB
±1.0 LSB
±0.5 LSB
±0.5 LSB
±1.0 LSB
±0.5 LSB
±0.5 LSB
±1.0 LSB
±0.5 LSB
±0.5 LSB
±1.0 LSB
±0.5 LSB
±0.5 LSB
±1.0 LSB
±0.5 LSB
±0.5 LSB
±1.0 LSB
±0.5 LSB
±0.5 LSB
±1.0 LSB
±0.5 LSB
±1.0 LSB
±0.5 LSB
±0.5 LSB
±0.5 LSB
±1.0 LSB
±0.5 LSB
±0.5 LSB
0 to 75
0 to 75
28 Ld PDIP
E28.6
E28.6
D28.6
D28.6
D28.6
D28.6
D28.6
D28.6
D28.6
D28.6
D28.6
J44.A
J44.A
J44.A
E28.6
E28.6
E28.6
D28.6
D28.6
D28.6
D28.6
D28.6
D28.6
D28.6
D28.6
D28.6
J44.A
J44.A
J44.A
E28.6
E28.6
D28.6
D28.6
D28.6
D28.6
J44.A
J44.A
J44.A
0 to 70
28 Ld PDIP
0 to 75
28 Ld SBDIP
28 Ld SBDIP
28 Ld SBDIP
28 Ld SBDIP
28 Ld SBDIP
28 Ld SBDIP
28 Ld SBDIP
28 Ld SBDIP
28 Ld SBDIP
44 Ld CLCC
44 Ld CLCC
44 Ld CLCC
28 Ld PDIP
0 to 75
0 to 75
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
0 to 75
0 to 75
28 Ld PDIP
0 to 75
28 Ld PDIP
0 to 75
28 Ld SBDIP
28 Ld SBDIP
28 Ld SBDIP
28 Ld SBDIP
28 Ld SBDIP
28 Ld SBDIP
28 Ld SBDIP
28 Ld SBDIP
28 Ld SBDIP
44 Ld CLCC
44 Ld CLCC
44 Ld CLCC
28 Ld PDIP
28 Ld PDIP
28 Ld SBDIP
28 Ld SBDIP
28 Ld SBDIP
28 Ld SBDIP
44 Ld CLCC
44 Ld CLCC
44 Ld CLCC
0 to 75
0 to 75
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
0 to 75
HI3-774K-5
0 to 75
HI1-774J-5
0 to 75
HI1-774K-5
0 to 75
HI1-774U-2
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
HI1-774T/883
HI4-774S/883
HI4-774T/883
HI4-774U/883
6-953
HI-574A, HI-674A, HI-774
Functional Block Diagram
BIT OUTPUTS
MSB
LSB
12/8
NIBBLE A (NOTE)
NIBBLE B (NOTE)
NIBBLE C (NOTE)
CS
CONTROL
LOGIC
THREE-STATE BUFFERS AND CONTROL
A
O
R/C
CE
V
LOGIC
POWER-UP RESET
DIGITAL
COMMON
12 BITS
SAR
STS
CLK
OSCILLATOR
STROBE
DIGITAL CHIP
ANALOG CHIP
12 BITS
V
V
CC
EE
COMP
V
IN
REF
DAC
-
10K
V
OUT
REF
5K
+
2.5K
+10V
REF
5K
10K
-
5K
ANALOG
COMMON
BIP
20V
10V
OFF INPUT INPUT
NOTE: “Nibble” is a 4-bit digital word.
6-954
HI-574A, HI-674A, HI-774
Absolute Maximum Ratings
Thermal Information
o
o
Supply Voltage
Thermal Resistance (Typical, Note 1)
CLCC Package . . . . . . . . . . . . . . . . . .
SBDIP Package. . . . . . . . . . . . . . . . . .
θ
( C/W)
θ
( C/W)
JA
JC
V
V
V
to Digital Common . . . . . . . . . . . . . . . . . . . . . . 0V to +16.5V
to Digital Common. . . . . . . . . . . . . . . . . . . . . . . 0V to -16.5V
65
60
14
18
N/A
CC
EE
to Digital Common. . . . . . . . . . . . . . . . . . . . . . 0V to +7V
HI3-574AxN-5, HI3-674AxN-5, HI3-774xN-5 65
Maximum Junction Temperature
HI3-574AxN-5, HI3-674AxN-5, HI3-774xN-5. . . . . . . . . . . . 150 C
HI1-574AxD-2, HI1-574AxD-5. . . . . . . . . . . . . . . . . . . . . . . 175 C
HI1-674AxD-2, HI1-674AxD-5. . . . . . . . . . . . . . . . . . . . . . . 175 C
LOGIC
Analog Common to Digital Common±1V
Control Inputs
o
o
(CE, CS, A , 12/8, R/C) to Digital Common . . -0.5V to V
+0.5V
O
LOGIC
o
Analog Inputs
o
(REFIN, BIPOFF, 10VIN) to Analog Common. . . . . . . . . . ±16.5V
HI1-774xD-2, HI1-774xD-5 . . . . . . . . . . . . . . . . . . . . . . . . . 175 C
20VIN to Analog Common . . . . . . . . . . . . . . . . . . . . . . . . . . ±24V Maximum Storage Temperature Range
o
o
REFOUT . . . . Indefinite Short To Common, Momentary Short To V
HI3-574AxN-5, HI3-674AxN-5, HI3-774xN-5. . . . . .-40 C to 85 C
CC
o
o
HI1-574AxD-2, HI1-574AxD-5. . . . . . . . . . . . . . . .-65 C to 150 C
o
o
HI1-674AxD-2, HI1-674AxD-5. . . . . . . . . . . . . . . .-65 C to 150 C
HI1-774xD-2, HI1-774xD-5 . . . . . . . . . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300 C
Operating Conditions
o
o
Temperature Range
o
o
o
HI3-574AxN-5, HI1-574AxD-5 . . . . . . . . . . . . . . . . . .0 C to 75 C
o
o
HI3-674AxN-5, HI1-674AxD-5 . . . . . . . . . . . . . . . . . .0 C to 75 C
HI3-774xN-5, HI1-774xD-5 . . . . . . . . . . . . . . . . . . . . .0 C to 75 C
HI1-574AxD-2, HI1-674AxD-2, HI1-774xD-2 . . . . -55 C to 125 C
Die Characteristics
o
o
Transistor Count
HI-574A, HI-674A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1117
HI-774 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2117
o
o
o
DC and Transfer Accuracy Specifications Typical at 25 C with V
= +15V or +12V, V
LOGIC
= +5V, V
= -15V or -12V,
CC
EE
Unless Otherwise Specified
TEMPERATURE RANGE
o
o
-5 (0 C to 75 C)
PARAMETER
DYNAMIC CHARACTERISTICS
J SUFFIX
K SUFFIX
L SUFFIX
UNITS
Resolution (Max)
Linearity Error
12
12
1
12
1
Bits
o
25 C (Max)
±1
±1
± /
± /
LSB
LSB
2
2
o
o
1
1
0 C to 75 C (Max)
± /
± /
2
2
Max Resolution For Which No Missing Codes Is Guaranteed
o
25 C
HI-574A, HI-674A
HI-774
12
11
11
11
12
12
12
12
12
12
12
12
Bits
Bits
Bits
Bits
T
to T
HI-574A, HI-674A
HI-774
MIN
MAX
Unipolar Offset (Max)
Adjustable to Zero
±2
±1.5
±1
LSB
Bipolar Offset (Max)
V
V
= 0V (Adjustable to Zero)
±4
±4
±3
LSB
IN
IN
= -10V
±0.15
±0.1
±0.1
% of FS
Full Scale Calibration Error
o
25 C (Max), With Fixed 50Ω Resistor From REF OUT To REF IN
±0.25
±0.25
±0.15
% of FS
(Adjustable to Zero)
o
T
T
to T
to T
(No Adjustment At 25 C)
±0.475
±0.22
±0.375
±0.12
±0.20
±0.05
% of FS
% of FS
MIN
MIN
MAX
MAX
o
(With Adjustment To Zero 25 C)
6-955
HI-574A, HI-674A, HI-774
o
DC and Transfer Accuracy Specifications Typical at 25 C with V
= +15V or +12V, V
LOGIC
= +5V, V
= -15V or -12V,
CC
EE
Unless Otherwise Specified (Continued)
TEMPERATURE RANGE
o
o
-5 (0 C to 75 C)
PARAMETER
J SUFFIX
K SUFFIX
L SUFFIX
UNITS
Temperature Coefficients
Guaranteed Max Change, T
to T
(Using Internal Reference)
MAX
MIN
Unipolar Offset
HI-574A, HI-674A
±2
±2
±2
±2
±9
±9
±1
±1
±1
±2
±2
±5
±1
±1
±1
±1
±2
±2
LSB
LSB
LSB
LSB
LSB
LSB
HI-774
Bipolar Offset
HI-574A, HI-674A
HI-774
Full Scale Calibration
Power Supply Rejection
HI-574A, HI-674A
HI-774
Max Change In Full Scale Calibration
+13.5V < V
< +16.5V or +11.4V < V
< +12.6V
CC
±2
±1
±1
LSB
LSB
LSB
CC
1
1
1
+4.5V < V
< +5.5V
± /
± /
± /
LOGIC
2
2
2
-16.5V < V < -13.5V or -12.6V < V < -11.4V
±2
±1
±1
EE
EE
ANALOG INPUTS
Input Ranges
Bipolar
-5 to +5
-10 to +10
0 to +10
0 to +20
V
V
V
V
Unipolar
Input Impedance
10V Span
5K, ±25%
Ω
Ω
20V Span
10K, ±25%
POWER SUPPLIES
Operating Voltage Range
V
V
V
+4.5 to +5.5
+11.4 to +16.5
-11.4 to -16.5
V
V
V
LOGIC
CC
EE
Operating Current
I
I
I
7 Typ, 15 Max
11 Typ, 15 Max
21 Typ, 28 Max
mA
mA
mA
LOGIC
+15V Supply
CC
EE
-15V Supply
Power Dissipation
±15V, +15V
515 Typ, 720 Max
385 Typ
mW
mW
±12V, +5V
Internal Reference Voltage
T
to T
+10.00 ±0.05 Max
V
MIN
MAX
Output Current, Available For External Loads (External Load Should
Not Change During Conversion).
2.0 Max
mA
6-956
HI-574A, HI-674A, HI-774
o
DC and Transfer Accuracy Specifications Typical at 25 C with V
= +15V or +12V, V
= +5V, V = -15V or -12V,
EE
CC
LOGIC
Unless Otherwise Specified
TEMPERATURE RANGE
o
o
-2 (-55 C to 125 C)
PARAMETER
DYNAMIC CHARACTERISTICS
S SUFFIX
T SUFFIX
U SUFFIX
UNITS
Resolution (Max)
Linearity Error
12
12
1
12
1
Bits
o
25 C
±1
±1
± /
± /
LSB
LSB
2
2
o
o
-55 C to 125 C (Max)
±1
±1
Max Resolution For Which No Missing Codes Is Guaranteed
o
25 C
HI-574A, HI-674A
HI-774
12
11
11
11
12
12
12
12
12
12
12
12
Bits
Bits
Bits
Bits
T
to T
HI-574A, HI-674A
HI-774
MIN
MAX
Unipolar Offset (Max)
Adjustable to Zero
HI-574A, HI-674A
HI-774
±2
±2
±1.5
±2
±1
±1
LSB
LSB
Bipolar Offset (Max)
V
V
= 0V (Adjustable to Zero)
±4
±4
±3
LSB
IN
IN
= -10V
±0.15
±0.1
±0.1
% of FS
Full Scale Calibration Error
o
25 C (Max), With Fixed 50Ω Resistor From REF OUT To REF IN
±0.25
±0.25
±0.15
% of FS
(Adjustable To Zero)
o
T
T
to T
to T
(No Adjustment At 25 C)
±0.75
±0.50
±0.50
±0.25
±0.275
±0.125
% of FS
% of FS
MIN
MIN
MAX
MAX
o
(With Adjustment To Zero At 25 C)
Temperature Coefficients
Guaranteed Max Change, T
to T
(Using Internal Reference)
MAX
MIN
Unipolar Offset
Bipolar Offset
±2
±2
±1
±2
±1
±1
±5
LSB
LSB
LSB
Full Scale Calibration
Power Supply Rejection
±20
±10
Max Change In Full Scale Calibration
+13.5V < V
< +16.5V or +11.4V < V
< +12.6V
CC
±2
±1
±1
LSB
LSB
LSB
CC
1
1
1
+4.5V < V
< +5.5V
± /
± /
± /
LOGIC
2
2
2
-16.5V < V < -13.5V or -12.6V < V < -11.4V
±2
±1
±1
EE
EE
ANALOG INPUTS
Input Ranges
Bipolar
-5 to +5
-10 to +10
0 to +10
0 to +20
V
V
V
V
Unipolar
6-957
HI-574A, HI-674A, HI-774
o
DC and Transfer Accuracy Specifications Typical at 25 C with V
= +15V or +12V, V
LOGIC
= +5V, V
= -15V or -12V,
CC
EE
Unless Otherwise Specified (Continued)
TEMPERATURE RANGE
o
o
-2 (-55 C to 125 C)
PARAMETER
S SUFFIX
T SUFFIX
U SUFFIX
UNITS
Input Impedance
10V Span
5K, ±25%
Ω
Ω
20V Span
10K, ±25%
POWER SUPPLIES
Operating Voltage Range
V
V
V
+4.5 to +5.5
+11.4 to +16.5
-11.4 to -16.5
V
V
V
LOGIC
CC
EE
Operating Current
I
I
I
7 Typ, 15 Max
11 Typ, 15 Max
21 Typ, 28 Max
mA
mA
mA
LOGIC
+15V Supply
CC
EE
-15V Supply
Power Dissipation
±15V, +15V
515 Typ, 720 Max
385 Typ
mW
mW
±12V, +5V
Internal Reference Voltage
T
to T
+10.00 ±0.05 Max
V
MIN
MAX
Output current, available for external loads (External load should not
change during conversion).
2.0 Max
mA
Digital Specifications All Models, Over Full Temperature Range
PARAMETER
MIN
TYP
MAX
Logic Inputs (CE, CS, R/C, A , 412/8)
O
Logic “1”
+2.4V
-
-
+5.5V
+0.8V
±5µA
-
Logic “0”
-0.5V
Current
-
-
±0.1µA
5pF
Capacitance
Logic Outputs (DB11-DB0, STS)
Logic “0” (I
Logic “1” (I
Logic “1” (I
- 1.6mA)
-
-
+0.4V
SINK
- 500µA)
- 10µA)
+2.4V
-
-
-
SOURCE
SOURCE
+4.5V
-
±5µA
-
Leakage (High-Z State, DB11-DB0 Only)
Capacitance
-
-
±0.1µA
5pF
o
Timing Specifications (HI-574A) 25 C, Note 2, Unless Otherwise Specified
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
CONVERT MODE
t
STS Delay from CE
-
-
200
ns
DSC
6-958
HI-574A, HI-674A, HI-774
o
Timing Specifications (HI-574A) 25 C, Note 2, Unless Otherwise Specified (Continued)
SYMBOL
PARAMETER
MIN
50
50
50
50
50
0
TYP
MAX
UNITS
ns
t
CE Pulse Width
-
-
-
-
HEC
t
CS to CE Setup
ns
SSC
HSC
SRC
HRC
t
t
CS Low During CE High
R/C to CE Setup
-
-
ns
-
-
ns
t
R/C Low During CE High
-
-
ns
t
A
A
to CE Setup
-
-
ns
SAC
O
t
Valid During CE High
50
15
10
-
-
ns
HAC
O
t
Conversion Time
12-Bit Cycle T
MIN
to T
20
13
25
17
µs
C
MAX
8-Bit Cycle T
MIN
to T
µs
MAX
READ MODE
t
t
Access Time from CE
Data Valid After CE Low
Output Float Delay
CS to CE Setup
-
25
-
75
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DD
-
-
HD
t
100
150
HL
t
50
0
-
-
-
-
-
-
-
-
SSR
SRR
t
R/C to CE Setup
-
t
A
to CE Setup
50
0
-
SAR
HSR
HRR
O
t
CS Valid After CE Low
R/C High After CE Low
-
t
0
-
-
t
A
Valid After CE Low
50
300
HAR
O
t
STS Delay After Data Valid
1200
HS
o
Timing Specifications (HI-674A) 25 C, Note 2, Unless Otherwise Specified
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
CONVERT MODE
t
t
STS Delay from CE
CE Pulse Width
-
-
-
200
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
DSC
50
50
50
50
50
0
-
-
HEC
t
CS to CE Setup
-
SSC
HSC
SRC
HRC
t
t
CS Low During CE High
R/C to CE Setup
-
-
-
-
t
R/C Low During CE High
-
-
t
A
A
to CE Setup
-
-
SAC
O
t
Valid During CE High
50
9
-
-
HAC
O
t
Conversion Time
12-Bit Cycle T
MIN
to T
12
8
15
10
C
MAX
8-Bit Cycle T
MIN
to T
6
MAX
READ MODE
t
t
Access Time from CE
Data Valid After CE Low
Output Float Delay
-
25
-
75
-
150
-
ns
ns
ns
DD
HD
t
100
150
HL
6-959
HI-574A, HI-674A, HI-774
o
Timing Specifications (HI-674A) 25 C, Note 2, Unless Otherwise Specified (Continued)
SYMBOL
PARAMETER
MIN
50
0
TYP
MAX
UNITS
ns
t
CS to CE Setup
R/C to CE Setup
-
-
-
-
-
-
-
-
SSR
t
-
ns
SRR
t
A
to CE Setup
50
0
-
ns
SAR
HSR
HRR
O
t
CS Valid After CE Low
R/C High After CE Low
-
ns
t
0
-
-
ns
t
A
Valid After CE Low
50
25
ns
HAR
O
t
STS Delay After Data Valid
850
ns
HS
o
Timing Specifications (HI-774) 25 C, Into a load with R = 3kΩ and C = 50pF, Note 2, Unless Otherwise Specified
L
L
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
CONVERT MODE
t
t
STS Delay from CE
CE Pulse Width
-
50
50
50
50
50
0
100
30
20
20
0
200
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
DSC
-
-
HEC
t
CS to CE Setup
SSC
HSC
SRC
HRC
t
t
CS Low During CE High
R/C to CE Setup
-
-
t
R/C Low During CE High
20
0
-
t
A
A
to CE Setup
-
SAC
O
t
Valid During CE High
50
-
30
8.0
6.4
9
-
HAC
O
t
Conversion Time
12-Bit Cycle T
to T
(-5)
9
C
MIN
MAX
8-Bit Cycle T
to T
(-5)
MAX
-
6.8
11
8.3
MIN
12-Bit Cycle T
MIN
to T
(-2)
-
MAX
8-Bit Cycle T
MIN
to T
(-2)
-
6.8
MAX
READ MODE
t
t
Access Time from CE
Data Valid After CE Low
Output Float Delay
CS to CE Setup
-
25
-
75
35
70
0
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DD
-
HD
t
150
HL
t
50
0
-
SSR
SRR
t
R/C to CE Setup
0
-
t
A
to CE Setup
50
0
25
0
-
SAR
HSR
HRR
O
t
CS Valid After CE Low
R/C High After CE Low
-
t
0
0
-
-
t
A
Valid After CE Low
50
-
25
90
HAR
O
t
STS Delay After Data Valid
300
HS
NOTES:
1. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.
2. Time is measured from 50% level of digital transitions. Tested with a 50pF and 3kΩ load.
6-960
HI-574A, HI-674A, HI-774
Definitions of Specifications
Pin Descriptions
Linearity Error
PIN
1
SYMBOL
DESCRIPTION
Logic supply pin (+5V)
Linearity error refers to the deviation of each individual code
from a line drawn from “zero” through “full scale”. The point
used as “zero” occurs / LSB (1.22mV for 10V span) before
2
the first code transition (all zeros to only the LSB “on”). “Full
V
LOGIC
1
2
12/8
Data Mode Select - Selects between
12-bit and 8-bit output modes.
1
scale” is defined as a level 1 / LSB beyond the last code tran-
2
sition (to all ones). The deviation of a code from the true straight
line is measured from the middle of each particular code.
3
4
5
6
CS
Chip Select - Chip Select high disables
the device.
The HI-X74(A)K and L grades are guaranteed for maximum
1
A
Byte Address/Short Cycle - See Table
1 for operation.
O
nonlinearity of ± / LSB. For these grades, this means that an
2
analog value which falls exactly in the center of a given code
width will result in the correct digital output code. Values nearer
the upper or lower transition of the code width may produce the
next upper or lower digital output code. The HI-X74(A)J is
guaranteed to ±1 LSB max error. For this grade, an analog
value which falls within a given code width will result in either
the correct code for that region or either adjacent one.
R/C
CE
Read/Convert - See Table 1 for
operation.
Chip Enable - Chip Enable low disables
the device.
7
8
V
Positive Supply (+12V/+15V)
+10V Reference
CC
Note that the linearity error is not user-adjustable.
REF OUT
AC
Differential Linearity Error (No Missing Codes)
A specification which guarantees no missing codes requires
that every code combination appear in a monotonic increas-
ing sequence as the analog input level is increased. Thus
every code must have a finite width. For the HI-X74(A)K and L
grades, which guarantee no missing codes to 12-bit resolu-
tion, all 4096 codes must be present over the entire operating
temperature ranges. The HI-X74(A)J grade guarantees no
missing codes to 11-bit resolution over temperature; this
means that all code combinations of the upper 11 bits must be
present; in practice very few of the 12-bit codes are missing.
9
Analog Common
10
11
12
13
REF IN
Reference Input
V
Negative Supply (-12V/-15V).
Bipolar Offset
EE
BIP OFF
10V Input
10V Input - Used for 0V to 10V and -5V
to +5V input ranges.
14
20V Input
20V Input - Used for 0V to 20V and -10V
to +10V input ranges.
Unipolar Offset
1
The first transition should occur at a level / LSB above analog
2
common. Unipolar offset is defined as the deviation of the
actual transition from that point. This offset can be adjusted as
discussed on the following pages. The unipolar offset tempera-
ture coefficient specifies the maximum change of the transition
point over temperature, with or without external adjustment.
15
16
17
18
19
20
21
22
23
24
25
26
27
28
DC
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
STS
Digital Common
Data Bit 0 (LSB)
Data Bit 1
Bipolar Offset
Data Bit 2
Similarly, in the bipolar mode, the major carry transition
Data Bit 3
(0111 1111 1111 to 1000 0000 0000) should occur for an
1
analog value
/ LSB below analog common. The bipolar
2
Data Bit 4
offset error and temperature coefficient specify the initial
deviation and maximum change in the error over tempera-
ture.
Data Bit 5
Data Bit 6
Full Scale Calibration Error
Data Bit 7
The last transition (from 1111 1111 1110 to 1111 1111
1
1111) should occur for an analog value 1 / LSB below the
2
Data Bit 8
nominal full scale (9.9963V for 10.000V full scale). The full
scale calibration error is the deviation of the actual level at
the last transition from the ideal level. This error, which is
typically 0.05 to 0.1% of full scale, can be trimmed out as
shown in Figures 2 and 3. The full scale calibration error
over temperature is given with and without the initial error
trimmed out. The temperature coefficients for each grade
indicate the maximum change in the full scale gain from the
initial value using the internal 10V reference.
Data Bit 9
Data Bit 10
Data Bit 11 (MSB)
Status Bit - Status high implies a
conversion is in progress.
6-961
HI-574A, HI-674A, HI-774
Temperature Coefficients
Power Supplies
The temperature coefficients for full-scale calibration, unipo- Supply voltages to the HI-X74(A) (+15V, -15V and +5V) must
lar offset, and bipolar offset specify the maximum change be “quiet” and well regulated. Voltage spikes on these lines can
o
from the initial (25 C) value to the value at T
or T
.
MAX
affect the converter’s accuracy, causing several LSBs to flicker
when a constant input is applied. Digital noise and spikes from
a switching power supply are especially troublesome. If switch-
ing supplies must be used, outputs should be carefully filtered
to assure “quiet” DC voltage at the converter terminals.
MIN
Power Supply Rejection
The standard specifications for the HI-X74A assume use of
+5.00V and ±15.00V or ±12.00V supplies. The only effect of
power supply error on the performance of the device will be
a small change in the full scale calibration. This will result in
a linear change in all lower order codes. The specifications
show the maximum change in calibration from the initial
value with the supplies at the various limits.
Further, a bypass capacitor pair on each supply voltage
terminal is necessary to counter the effect of variations in
supply current. Connect one pair from pin 1 to 15 (V
LOGIC
supply), one from pin 7 to 9 (V
to Analog Common) and
CC
to Analog Common). For each
one from pin 11 to 9 (V
EE
capacitor pair, a 10µF tantalum type in parallel with a 0.1µF
ceramic type is recommended.
Code Width
A fundamental quantity for A/D converter specifications is
the code width. This is defined as the range of analog input
values for which a given digital output code will occur. The
nominal value of a code width is equivalent to 1 least signifi-
cant bit (LSB) of the full scale range or 2.44mV out of 10V for
a 12-bit ADC.
Ground Connections
Pins 9 and 15 should be tied together at the package to
guarantee specified performance for the converter. In
addition, a wide PC trace should run directly from pin 9 to
(usually) +15V common, and from pin 15 to (usually) the +5V
Logic Common. If the converter is located some distance from
the system’s “single point” ground, make only these connec-
tions to pins 9 and 15: Tie them together at the package, and
back to the system ground with a single path. This path
should have low resistance. (Code dependent currents flow in
Quantization Uncertainty
Analog-to-digital converters exhibit an inherent quantization
1
uncertainty of ± / LSB. This uncertainty is a fundamental
2
characteristic of the quantization process and cannot be
reduced for a converter of given resolution.
the V , V
and V
terminals, but not through the
HI-X74(A)’s Analog Common or Digital Common).
CC EE
LOGIC
Left-justified Data
The data format used in the HI-X74(A) is left-justified. This Analog Signal Source
means that the data represents the analog input as a frac-
HI-574A and HI-674A
4095
tion of full-scale, ranging from 0 to
binary point to the left of the MSB.
. This implies a
4096
The device chosen to drive the HI-X74A analog input will see a
nominal load of 5kΩ (10V range) or 10kΩ (20V range).
However, the other end of these input resistors may change
±400mV with each bit decision, creating abrupt changes in cur-
rent at the analog input. Thus, the signal source must maintain
its output voltage while furnishing these step changes in load
current, which occur at 1.6µs and 950ns intervals for the
HI-574A and HI-674A, respectively. This requires low output
impedance and fast settling by the signal source.
Applying the HI-X74(A)
For each application of this converter, the ground
connections, power supply bypassing, analog signal source,
digital timing and signal routing on the circuit board must be
optimized to assure maximum performance. These areas
are reviewed in the following sections, along with basic oper-
ating modes and calibration requirements.
The output impedance of an op amp, for example, has an open
loop value which, in a closed loop, is divided by the loop gain
available at a frequency of interest. The amplifier should have
acceptable loop gain at 600KHz for use with the HI-X74A. To
check whether the output properties of a signal source are
suitable, monitor the HI-X74A’s input (pin 13 or 14) with an oscil-
loscope while a conversion is in progress. Each of the twelve
disturbances should subside in 1µs or less for the HI-574A and
500ns or less for the HI-674A. (The comparator decision is
made about 1.5µs and 850ns after each code change from the
SAR for the HI-574A and HI-674A, respectively.)
Physical Mounting and Layout Considerations
Layout
Unwanted, parasitic circuit components, (L, R, and C) can
make 12-bit accuracy impossible, even with a perfect A/D
converter. The best policy is to eliminate or minimize these
parasitics through proper circuit layout, rather than try to
quantify their effects.
The recommended construction is a double-sided printed
circuit board with a ground plane on the component side.
Other techniques, such as wire-wrapping or point-to-point
wiring on vector board, will have an unpredictable effect on
accuracy.
If the application calls for a Sample/Hold to precede the
converter, it should be noted that not all Sample/Holds are
compatible with the HI-574A in the manner described above.
These will require an additional wideband buffer amplifier to
lower their output impedance. A simpler solution is to use the
Intersil HA-5320 Sample/Hold, which was designed for use
with the HI-574A.
In general, sensitive analog signals should be routed between
ground traces and kept well away from digital lines. If analog
and digital lines must cross, they should do so at right angles.
6-962
HI-574A, HI-674A, HI-774
HI-774
direction by up to 15 LSBs. This results in a total correction
range of +31 to -32 LSBs. When an 8-bit conversion is per-
The device driving the HI-774 analog input will see a nominal
load of 5kΩ (10V range) or 10kΩ (20V range). However, the
other end of these input resistors may change as much as
1
formed, the input must settle to within ± / LSB at 8-bit resolu-
2
tion (which equals ±8 LSBs at 12-bit resolution).
±400mV with each bit decision. These input disturbances With the HI-774 a conversion can be initiated before the
are caused by the internal DAC changing codes which input has completely settled, as long as it meets the con-
causes a glitch on the summing junction. This creates abrupt straints of the Figure 1 window. This allows the user to start
changes in current at the analog input causing a “kick back” conversion up to 4.8µs earlier than with a typical analog to
glitch from the input. Because the algorithm starts with the digital converter. A typical successive approximation type
MSB, the first glitches will be the largest and get smaller as ADC must have a constant input during a conversion
the conversion proceeds. These glitches can occur at 350ns because once a bit decision is made it is locked in and can-
intervals so an op amp with a low output impedance and fast not change.
settling is desirable. Ultimately the input must settle to within
the window of Figure 1 at the bit decision points in order to
achieve 12-bit accuracy.
32
The HI-774 differs from the most high-speed successive
approximation type ADC’s in that it does not require a high
performance buffer or sample and hold. With error correction
the input can settle while the conversion is underway, but
only during the first 4.8µs. The input must be within 10.76%
of the final value when the MSB decision is made. This
occurs approximately 650ns after the conversion has been
initiated. Digital error correction also loosens the bandwidth
requirements of the buffer or sample and hold. As long as
the input “kick back” disturbances settle within the window of
Figure 1 the device will remain accurate. The combined
effect of settling and the “kick back” disturbances must
remain in the Figure 1 window.
8-BIT CONVERSION
END OF
CONVERSION
(12 BIT)
16
8
1
BIT DECISION POINTS
± / LSB
2
0
~ 4.8µs
-8
LAST BIT
DECISION
(12-BIT)
-16
MSB BIT DECISION
~ 650ns
12-BIT CONVERSION
-31
1
2
3
4
5
6
7
8
CONVERSION
INITIATED
TIME (µs)
If the design is being optimized for speed, the input device
should have closed loop bandwidth to 3MHz, and a low out-
put impedance (calculated by dividing the open loop output
resistance by the open loop gain). If the application requires
a high speed sample and hold the Intersil HA-5330 or
HA-5320 are recommended.
FIGURE 1. HI-774 ERROR CORRECTION WINDOW vs TIME
STS 28
2 12/8
In any design the input (pin 13 or 14) should be checked
during a conversion to make sure that the input stays within
the correctable window of Figure 1.
HIGH BITS
24-27
3
4
5
CS
A
O
MIDDLE BITS
20-23
Digital Error Correction
OFFSET
R1
R/C
CE
100K
HI-774
LOW BITS
16-19
+15V
GAIN
-15V
6
The HI-774 features the smart successive approximation
register (SSAR) which includes digital error correction. This
has the advantage of allowing the initial input to vary within a
+31 to -32 LSB window about the final value. The input can
R2
10 REF IN
REF OUT
100K
100Ω
move during the first 4.8µs, after which it must remain stable
8
1
100Ω
within ± / LSB. With this feature a conversion can start
2
+5V
1
7
before the input has settled completely; however, it must be
within the window as described in Figure 1.
12 BIP OFF
13 10V
0V TO +10V
ANALOG
+15V
IN
The conversion cycle starts by making the first 8-bit decisions
very quickly, allowing the internal DAC to settle only to 8-bit
INPUTS
-15V 11
14 20VIN۠
0V TO +20V
accuracy. Then the converter goes through two error correc-
DIG COM 15
9 ANA
COM
1
tion cycles. At this point the input must be stable within ± /
2
LSB. These cycles correct the 8-bit word to 12-bit accuracy for
any errors made (up to +16 or -32 LSBs). This is up one count
or down two counts at 8-bit resolution. The converter then
continues to make the 4 LSB decisions, settling out to 12-bit
accuracy. The last four bits can adjust the code in the positive
†When driving the 20V (pin 14) input, minimize capacitance on pin 13.
FIGURE 2. UNIPOLAR CONNECTIONS
6-963
HI-574A, HI-674A, HI-774
adjustment is complete. Therefore, calibration is performed
STS 28
in terms of the observable code changes instead of the
midpoint between code changes.
2 12/8
HIGH BITS
24-27
3
4
5
CS
For example, midpoint of the first LSB increment should be
A
O
MIDDLE BITS
20-23
positioned at the origin, with an output code of all 0’s. To do
1
this, apply an input of + / LSB (+1.22mV for the 10V range;
2
R/C
CE
+2.44mV for the 20V range). Adjust the Offset potentiometer
R1 until the first code transition flickers between
0000 0000 0000 and 0000 0000 0001.
LOW BITS
16-19
6
GAIN
R2
Next, perform a Gain Adjust at positive full scale. Again, the
10 REF IN
REF OUT
12 BIP OFF
ideal input corresponding to the last code change is applied.
100Ω
100Ω
R1
1
8
This is 1 / LSBs below the nominal full scale (+9.9963V for
2
10V range; +19.9927V for 20V range). Adjust the Gain
potentiometer R2 for flicker between codes 1111 1111 1110
and 1111 1111 1111.
+5V 1
±5V
OFFSET
+15V 7
-15V 11
13 10V
IN
ANALOG
INPUTS
Bipolar Connections and Calibration
14 20V †
IN
±10V
Refer to Figure 3. The gain and offset errors listed under
Specifications may be adjusted to zero using potentiome-
ters R1 and R2 (see Note). If this isn’t required, either or
both pots may be replaced by a 50Ω, 1% metal film resistor.
DIG COM 15
9 ANA
COM
Connect the Analog signal to pin 13 for a ±5V range, or to
pin 14 for a ±10V range. Calibration of offset and gain is sim-
†When driving the 20V (pin 14) input, minimize capacitance on pin 13.
FIGURE 3. BIPOLAR CONNECTIONS
ilar to that for the unipolar ranges as discussed above. First
1
apply a DC input voltage / LSB above negative full scale
2
Range Connections and Calibration Procedures
(i.e., -4.9988V for the ±5V range, or -9.9976V for the ±10V
range). Adjust the offset potentiometer R1 for flicker between
The HI-X74(A) is a “complete” A/D converter, meaning it is
fully operational with addition of the power supply voltages, a
Start Convert signal, and a few external components as
shown in Figure 2 and Figure 3. Nothing more is required for
most applications.
output codes 0000 0000 0000 and 0000 0000 0001. Next,
1
apply a DC input voltage 1 / LSBs below positive full scale
2
(+4.9963V for ±5V range; +9.9927V for ±10V range). Adjust
the Gain potentiometer R2 for flicker between codes 1111
1111 1110 and 1111 1111 1111.
Whether controlled by a processor or operating in the stand-
alone mode, the HI-X74(A) offers four standard input ranges:
0V to +10V, 0V to +20V, ±5V and ±10V. The maximum errors
for gain and offset are listed under Specifications. If required,
however, these errors may be adjusted to zero as explained
below. Power supply and ground connections have been dis-
cussed in an earlier section.
NOTE: The 100Ω potentiometer R2 provides Gain Adjust for the 10V
and 20V ranges. In some applications, a full scale of 10.24V (LSB
equals 2.5mV) or 20.48V (LSB equals 5.0mV) is more convenient.
For these, replace R2 by a 50Ω, 1% metal film resistor. Then, to pro-
vide Gain Adjust for the 10.24V range, add a 200Ω potentiometer in
series with pin 13. For the 20.48V range, add a 500Ω potentiometer
in series with pin 14.
Unipolar Connections and Calibration
Controlling the HI-X74(A)
Refer to Figure 2. The resistors shown (see Note) are for
calibration of offset and gain. If this is not required, replace
R2 with a 50Ω, 1% metal film resistor and remove the net-
work on pin 12. Connect pin 12 to pin 9. Then, connect the
analog signal to pin 13 for the 0V to 10V range, or to pin 14
for the 0V to 20V range. Inputs to +20V (5V over the power
supply) are no problem - the converter operates normally.
The HI-X74(A) includes logic for direct interface to most
microprocessor systems. The processor may take full con-
trol of each conversion, or the converter may operate in the
“stand-alone” mode, controlled only by the R/C input. Full
control consists of selecting an 8-bit or 12-bit conversion
cycle, initiating the conversion, and reading the output data
when ready-choosing either 12 bits at once or 8 followed by
4, in a left-justified format. The five control inputs are all
Calibration consists of adjusting the converter’s most
negative output to its ideal value (offset adjustment), then,
adjusting the most positive output to its ideal value (gain
adjustment). To understand the procedure, note that in
principle, one is setting the output with respect to the mid-
point of an increment of analog input, as denoted by two
adjacent code changes. Nominal value of an increment is
one LSB. However, this approach is impractical because
nothing “happens” at a midpoint to indicate that an
TTL/CMOS-compatible: (12/8, CS, A , R/C and CE). Table
O
1 illustrates the use of these inputs in controlling the
converter’s operations. Also, a simplified schematic of the
internal control logic is shown in Figure 7.
6-964
HI-574A, HI-674A, HI-774
“Stand-Alone Operation”
Conversion Length
A Convert Start transition (see Table 1) latches the state of
A , which determines whether the conversion continues for
The simplest control interface calls for a singe control line
connected to R/C. Also, CE and 12/8 are wired high, CS and
O
12 bits (A low) or stops with 8 bits (A high). If all 12 bits are
O
O
A
are wired low, and the output data appears in words of
O
read following an 8-bit conversion, the last three LSBs will
12 bits each.
read ZERO and DB3 will read ONE. A is latched because it
O
The R/C signal may have any duty cycle within (and is also involved in enabling the output buffers (see “Reading
including) the extremes shown in Figures 8 and 9. In gen- the Output Data”). No other control inputs are latched.
eral, data may be read when R/C is high unless STS is also
TABLE 1. TRUTH TABLE FOR HI-X74(A) CONTROL INPUTS
high, indicating a conversion is in progress. Timing parame-
ters particular to this mode of operation are listed below
under “Stand-Alone Mode Timing”.
CE
0
CS R/C 12/8
A
OPERATION
O
X
1
0
0
↓
X
X
0
0
0
0
↓
X
X
X
X
X
X
X
X
1
X
None
None
HI-574A STAND-ALONE MODE TIMING
PARAMETER MIN TYP MAX UNITS
Low R/C Pulse Width
X
↑
X
0
1
0
1
0
1
X
0
1
SYMBOL
Initiate 12-bit conversion
Initiate 8-bit conversion
Initiate 12-bit conversion
Initiate 8-bit conversion
Initiate 12-bit conversion
Initiate 8-bit conversion
Enable 12-bit Output
t
50
-
-
-
-
-
-
-
-
200
-
ns
ns
ns
ns
ns
ns
HRL
↑
t
STS Delay from R/C
DS
1
t
Data Valid after R/C Low
25
HDR
1
↓
t
STS Delay after Data Valid 300
1200
-
HS
1
0
0
0
0
0
t
t
High R/C Pulse Width
Data Access Time
150
-
HRH
DDR
1
↓
150
1
1
1
1
Time is measured from 50% level of digital transitions. Tested with a
50pF and 3kΩ load.
1
0
Enable 8 MSBs Only
1
0
Enable 4 LSBs Plus 4 Trailing
Zeroes
HI-674A STAND-ALONE MODE TIMING
SYMBOL
PARAMETER
Low R/C Pulse Width
STS Delay from R/C
Data Valid after R/C Low
MIN TYP MAX UNITS
Conversion Start
t
50
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
HRL
A conversion may be initiated as shown in Table 1 by a logic
transition on any of three inputs: CE, CS or R/C. The last of
the three to reach the correct state starts the conversion, so
one, two or all three may be dynamically controlled. The
nominal delay from each is the same, and if necessary, all
three may change state simultaneously. However, to ensure
that a particular input controls the start of conversion, the
other two should be set up at least 50ns earlier. See the
HI-774 Timing Specifications, Convert Mode.
t
200
-
DS
t
25
HDR
t
STS Delay after Data Valid 25
850
-
HS
t
t
High R/C Pulse Width
Data Access Time
150
-
HRH
DDR
150
Time is measured from 50% level of digital transitions. Tested with a
50pF and 3kΩ load.
This variety of HI-X74(A) control modes allows a simple
interface in most system applications. The Convert Start
timing relationships are illustrated in Figure 4.
HI-774 STAND-ALONE MODE TIMING
The output signal STS indicates status of the converter by
going high only while a conversion is in progress. While STS
is high, the output buffers remain in a high impedance state
and data cannot be read. Also, an additional Start Convert
will not reset the converter or reinitiate a conversion while
STS is high.
SYMBOL
PARAMETER
Low R/C Pulse Width
STS Delay from R/C
Data Valid after R/C Low
STS Delay after Data Valid
High R/C Pulse Width
Data Access Time
MIN TYP MAX UNITS
t
50
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
HRL
t
200
-
DS
t
20
-
HDR
Reading the Output Data
t
850
-
The output data buffers remain in a high impedance state
until four conditions are met: R/C high, STS low, CE high and
CS low. At that time, data lines become active according to
HS
t
t
150
-
HRH
DDR
the state of inputs 12/8 and A . Timing constraints are
150
O
illustrated in Figure 5.
6-965
HI-574A, HI-674A, HI-774
The 12/8 input will be tied high or low in most applications,
though it is fully TTL/CMOS-compatible. With 12/8 high, all
12 output lines become active simultaneously, for interface to
a 12-bit or 16-bit data bus. The A input is ignored.
O
CE
CS
t
t
t
HSR
SSR
With 12/8 low, the output is organized in two 8-bit bytes,
selected one at a time by A . This allows an 8-bit data bus
O
to be connected as shown in Figure 6. A is usually tied to
O
t
HRR
the least significant bit of the address bus, for storing the
HI-X74(A) output in two consecutive memory locations.
(With A low, the 8 MSBs only are enabled. With A high, 4
MSBs are disabled, bits 4 through 7 are forced low, and the 4
LSBs are enabled). This two byte format is considered “left
justified data,” for which a decimal (or binary!) point is
assumed to the left of byte 1:
R/C
O
O
SRR
A
O
t
t
SAR
HAR
STS
t
BYTE 1
BYTE 2
HS
t
HD
DATA
VALID
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
DB11-DB0
•
HIGH IMPEDANCE
t
t
HL
DD
MSB
LSB
Further, A may be toggled at any time without damage to
O
See HI-774 Timing Specifications for more information.
the converter. Break-before-make action is guaranteed
between the two data bytes, which assures that the outputs
strapped together in Figure 6 will never be enabled at the
same time.
FIGURE 5. READ CYCLE TIMING
A read operation usually begins after the conversion is
complete and STS is low. For earliest access to the data,
however, the read should begin no later than (t
before STS goes low. See Figure 5.
+ t )
DD
HS
A
ADDRESS BUS
O
1
2
28
27
26
25
24
23
22
21
20
19
18
17
STS
DB11 (MSB)
t
HEC
CE
CS
12/8
t
SSC
3
4
A
O
t
HSC
t
SRC
5
R/C
DATA
BUS
6
t
HRC
7
A
O
HI-774
8
t
SAC
9
t
HAC
10
11
12
13
14
STS
t
C
t
DSC
HIGH IMPEDANCE
DB11-DB0
DB0 (LSB) 16
DIG.
15
COM.
See HI-774 Timing Specifications for more information.
FIGURE 4. CONVERT START TIMING
FIGURE 6. INTERFACE TO AN 8-BIT DATA BUS
6-966
HI-574A, HI-674A, HI-774
NIBBLE B ZERO
OVERRIDE
NIBBLE A, B
NIBBLE C
INPUT BUFFERS
12/8
READ CONTROL
CS
A
O
STATUS
R/C
CE
CURRENT
CONTROLLED
OSCILLATOR
STROBE
CLOCK
CONVERT
CONTROL
EOC9
CK
POWER UP
RESET
Q
D
RESET
Q
A
LATCH
O
EOC13
FIGURE 7. HI-774 CONTROL LOGIC
t
HRL
R/C
t
DS
STS
t
C
t
HDR
t
HS
DATA
VALID
DATA
VALID
DB11-DB0
FIGURE 8. LOW PULSE FOR R/C - OUTPUTS ENABLED AFTER CONVERSION
R/C
t
t
DS
HRH
STS
t
C
t
HDR
t
DDR
HIGH-Z
HIGH-Z
DB11-DB0
DATA
VALID
FIGURE 9. HIGH PULSE FOR R/C - OUTPUTS ENABLED WHILE R/C HIGH, OTHERWISE HIGH-Z
6-967
HI-574A, HI-674A, HI-774
Die Characteristics
DIE DIMENSIONS:
PASSIVATION:
Analog: 3070mm x 4610mm
Digital: 1900mm x 4510mm
Type: Nitride Over Silox
Nitride Thickness: 3.5kÅ ±0.5kÅ
Silox Thickness: 12kÅ ±1.5kÅ
METALLIZATION:
WORST CASE CURRENT DENSITY:
Digital Type: Nitrox
Thickness: 10kÅ ±2kÅ
5
2
1.3 x 10 A/cm
Metal 1: AlSiCu
Thickness: 8kÅ ±1kÅ
Metal 2: AlSiCu
Thickness: 16kÅ ±2kÅ
Analog Type: Al
Thickness: 16kÅ ±2kÅ
Metallization Mask Layout
HI-574A, HI-674A, HI-774
R/C
CE
DB10
DB9
V
CC
V
REFOUT
ANALOG
COMMON
DB8
DB7
DB6
DB5
ANALOG
COMMON
ANALOG
COMMON
V
REFIN
DB4
DB3
DB2
V
EE
6-968
HI-574A, HI-674A, HI-774
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
EUROPE
ASIA
Intersil Corporation
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
6-969
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