HI20203JCB [INTERSIL]
8-Bit, 160 MSPS, Ultra High-Speed D/A Converter; 8位， 160 MSPS ，超高速D / A转换器
| 型号： | HI20203JCB |
| 厂家： | 
Intersil |
| 描述： | 8-Bit, 160 MSPS, Ultra High-Speed D/A Converter |
| 文件： | 总10页 (文件大小：82K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HI20203
8-Bit, 160 MSPS,
Ultra High-Speed D/A Converter
August 1997
Features
Description
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . 160MHz The HI20203 is an 8-bit, 160MHz ultra high speed D/A con-
verter. The converter is based on an R2R switched current
source architecture that includes an input data register with
• 8-Bit (HI20203) Resolution
a complement feature and is Emitter Coupled Logic (ECL)
compatible.
• Differential Linearity Error . . . . . . . . . . . . . . . . 0.5 LSB
• Low Glitch Noise
The HI20203 is an 8-bit accurate D/A with a linearity error of
0.5 LSB.
• Analog Multiplying Function
• Low Power Consumption . . . . . . . . . . . . . . . . . .420mW
• Evaluation Board Available
For 10-bit resolution, please refer to the HI20201 data sheet.
Ordering Information
• Direct Replacement for the Sony CX20201-3, CX20202-3
PART
NUMBER
TEMP.
RANGE ( C)
o
PACKAGE
28 Ld SOIC
28 Ld PDIP
PKG. NO.
M28.3A-S
E28.6A-S
Applications
HI20203JCB
HI20203JCP
-20 to 75
• Wireless Communications
• Signal Reconstruction
• Direct Digital Synthesis
• High Definition Video Systems
• Digital Measurement Systems
• Radar
-20 to 75
Pinout
HI20203
(PDIP, SOIC)
TOP VIEW
1
2
28 AV
SS
(MSB) D7
D6
27
V
REF
3
26 AV
EE
D5
25 NC
24 NC
23 NC
22 NC
21 NC
4
D4
5
D3
6
D2
7
D1
8
D0
9
20
I
NC
OUT
10
11
12
13
14
19 NC
18 AV
NC
NC
SS
17 DV
NC
SS
16 COMPL
CLK
CLK
15 DV
EE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
File Number 4096.1
10-1
HI20203
Typical Application Circuit
HI20203
.
(28) AV
SS
D7
D6
D5
D4
D3
D2
D1
D0
D7 (MSB) (1)
1.5kΩ
1kΩ
D6 (2)
~2.7V
D5 (3)
D4 (4)
D3 (5)
D2 (6)
D1 (7)
D0 (8)
(9)
(27) V
REF
2kΩ
DIGITAL
DATA
(ECL)
TL431CP
-5.2V
(26) AV
EE
0.047µF
1.0µF
(10)
(11)
(12)
75Ω COAX CABLE
D/A OUT
(20) I
OUT
(18, 19, 21-25) NC
82Ω 82Ω
(17) DV
SS
CLK (13)
CLK (14)
CLK
1.0µF
3.6kΩ
(16) COMPL
-1.3V
0.047µF
-5.2V
131Ω
(15) DV
EE
131Ω
-5.2V
Functional Block Diagram
4 LSBs
CURRENT
CELLS
(LSB) D0
D1
R2R
NETWORK
D2
D3
INPUT
8-BIT
REGISTER
BUFFER
D4
D5
UPPER
4-BIT
ENCODER
D6
15
I
OUT
15
(MSB) D7
SWITCHED
CURRENT
CELLS
COMPL
BIAS CURRENT
GENERATOR
CLK
CLK
CLOCK
BUFFER
V
REF
AV
AV
DV
EE
DV
SS
EE
SS
10-2
HI20203
o
Absolute Maximum Ratings T = 25 C
Thermal Information
A
o
Digital Supply Voltage DV to DV
. . . . . . . . . . . . . . . . . . . -7.0V
. . . . . . . . . . . . . . . . . . -7.0V
Thermal Resistance (Typical, Note 5)
θ
( C/W)
EE
SS
to AV
JA
Analog Supply Voltage AV
DD
SS
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
67
58
Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 to DV
Reference Input Voltage . . . . . . . . . . . . . . . . . . . . . . +0.3 to AV
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20mA
V
V
EE
o
EE
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C
o
o
o
(SOIC - Lead Tips Only)
Operating Conditions
Supply Voltage
Reference Input Voltage, V
. . . . . . . . V + 0.5V to V + 1.4V
EE EE
REE
AV , DV
. . . . . . . . . . . . . . . . . . . . . . . . . . . . -4.75V to -5.45V Load Resistance, R . . . . . . . . . . . . . . . . . . . . . . . . . . . . Above 75Ω
EE
EE
L
AV - DV . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05V to +0.05V Output Voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . 0.8V to 1.2V
EE EE
O(FS)
o
o
Digital Input Voltage
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-20 C to 75 C
V
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to -0.7V
IH
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.9V to -1.6V
IL
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
o
Electrical Specifications AV = -5.2V, DV = -5.2V, AGND = 0V, DGND = 0V, R = ∞, V
= -1V, T = 25 C
A
EE
EE
L
OUT
HI20203JCB/JCP
TYP
PARAMETER
SYSTEM PERFORMANCE
Resolution
TEST CONDITION
MIN
MAX
UNITS
8
-
-
-
-
±0.5
±0.50
-
Bits
LSB
LSB
LSB
Integral Linearity Error, INL
Differential Linearity Error, DNL
f
= 160MHz (End Point)
= 160MHz
S
f
-
-
S
Offset Error, V
OS
(Note 3)
-
1.8
(Adjustable to Zero)
Full Scale Error, FSE
(Adjustable to Zero)
(Note 3)
-
-
-
-
±26
LSB
mA
Full Scale Output Current, I
20
FS
DYNAMIC CHARACTERISTICS
Throughput Rate
See Figure 11
160
-
-
-
-
MHz
pV/s
Glitch Energy, GE
R
= 75Ω
15
OUT
REFERENCE INPUT
Voltage Reference Input Range
Reference Input Current
With respect to AV
+0.5
-0.1
-
-
+1.4
-3.0
-
V
EE
V
= -4.58V
-0.4
14.0
µA
REF
Voltage Reference to Output Small
Signal Bandwidth
-3dB point 1V
P-P
Input
MHz
Output Rise Time, t
R
R
= 75Ω
-
-
1.5
1.5
-
-
ns
ns
r
LOAD
LOAD
Output Fall Time, t
= 75Ω
f
DIGITAL INPUTS
Input Logic High Voltage, V
IH
(Note 2)
(Note 2)
-1.0
-0.89
-1.75
V
V
Input Logic Low Voltage, V
-1.6
IL
10-3
HI20203
o
Electrical Specifications AV = -5.2V, DV = -5.2V, AGND = 0V, DGND = 0V, R = ∞, V
= -1V, T = 25 C (Continued)
A
EE
EE
L
OUT
HI20203JCB/JCP
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
Input Logic Current, I , I
IL IH
(For D9 thru D6, COMPL)
V
= -0.89V, V = -1.75V
IL
0.1
1.5
6.0
µA
IH
(Note 2)
Input Logic Current, I , I
IL IH
(For D5 thru D0)
V
= -0.89V, V = -1.75V
IL
0.1
0.75
3.0
µA
IH
(Note 2)
TIMING CHARACTERISTICS
Data Setup Time, t
See Figure 11
See Figure 11
See Figure 11
See Figure 11
5
1
-
-
-
-
-
-
ns
ns
ns
ns
SU
Data Hold Time, t
-
HLD
Propagation Delay Time, t
1
3.8
4.3
PD
Settling Time, t
(to / LSB)
-
SET
2
POWER SUPPLY CHARACTERISITICS
I
-60
-
-75
-90
mA
EE
Power Dissipation
75Ω load
420
470
mW
NOTES:
2. Parameter guaranteed by design or characterization and not production tested.
3. Excludes error due to reference drift.
4. Electrical specifications guaranteed only under the stated operating conditions.
Timing Diagram
CLK
CLK
DATA
t
t
HD
SU
N
N + 1
t
t
D
D
0V
N + 1
90%
N
D/A OUT
-1V
50%
10%
t
t
f
r
FIGURE 1. LADDER SETTLING TIME FULL POWER BANDWIDTH (LS)
10-4
HI20203
Typical Performance Curves
-2.0
1.05
1.00
0.95
o
= 25 C, V = -5.2V
T
A
EE
LINEAR AREA
R
= 10kΩ
L
R
= 10kΩ
L
-1.0
R
= 75Ω
L
R
= 75Ω
L
0
0.5
1.0
1.5
-20
0
20
40
60
80
o
V
- V (V)
EE
REF
AMBIENT TEMPERATURE ( C)
FIGURE 2. V
O(FS)
RATIO vs (V
REF
- V
EE
)
FIGURE 3. FULL SCALE OUTPUT VOLTAGE vs AMBIENT
TEMPERATURE
0
-10
-20
f
= 100MHz
CLK
10.0
8.0
6.0
4.0
2.0
GAIN
0
PHASE
-90
-180
10K
100K
1M
10M
100M
-50
0
50
100
o
MULTIPLYING INPUT SIGNAL FREQUENCY (Hz)
CASE TEMPERATURE ( C)
FIGURE 4. OUTPUT CHARACTERISTICS vs MULTIPLYING
INPUT SIGNAL FREQUENCY
FIGURE 5. GLITCH ENERGY vs CASE TEMPERATURE
(FULL SCALE - 1023mV)
Pin Descriptions
28 PIN SOIC
PIN NAME
PIN DESCRIPTION
1-8
D0 (LSB) - D7 (MSB) Digital Data Bit 0, the Least Significant Bit thru Digital Data Bit 7, the Most Significant Bit.
11, 12, 19,
21-25
NC
No connect, not used.
13
14
15
16
Negative Differential Clock Input.
Positive Differential Clock Input
CLK
CLK
DV
EE
Digital (ECL) Power Supply -4.75V to -7V.
COMPL
Data Complement Pin. When set to a (ECL) logic High the input data is complemented in the input
buffer. When cleared to a (ECL) logic Low the input data is not complemented.
17
18
20
26
27
28
DV
AV
Digital Ground.
SS
Analog Ground.
SS
I
Current Output Pin.
OUT
AV
Analog Supply -4.75V to -7V.
Input Reference Voltage used to set the output full scale range.
Analog Ground
EE
V
REF
AV
SS
10-5
HI20203
Detailed Description
The HI20203 is an 8-bit, current-output D/A converter. The the entire output range. By making the glitch a constant size
converter has 10 data bits but yields 8-bit performance.
over the entire output range this effectively integrates this
error out of the end application.
Architecture
In measuring the output glitch of the HI20203 the output is
terminated into a 75Ω load. The glitch is measured at the
major carry’s throughout the DACs output range.
The HI20203 is a combined R2R/segmented current source
design. The 6 least significant bits of the converter are derived by
a traditional R2R network to binary weight the 1mA current
sources. The upper 4 most significant bits are implemented as The glitch energy is calculated by measuring the area under
segmented or thermometer encoded current sources. The the voltage-time curve. Figure 7 shows the area considered
encoder converts the incoming 4 bits to 15 control lines to enable as glitch when changing the DAC output. Units are typically
the most significant current sources. The thermometer encoder specified in picoVolt/seconds (pV/s).
will convert binary to individual control lines. See Table 1.
TABLE 1. THERMOMETER ENCODER
HI20203
THERMOMETER CODE
34MHz
LOW PASS
FILTER
SCOPE
1 = ON, 0 = OFF
- I
(20) I
OUT
MSB
0
BIT 6
BIT 5
BIT 4
I
15
0
50Ω
75Ω
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
000 0000 0000 0000
000 0000 0000 0001
000 0000 0000 0011
000 0000 0000 0111
000 0000 0000 1111
000 0000 0001 1111
000 0000 0011 1111
000 0000 0111 1111
000 0000 1111 1111
000 0001 1111 1111
000 0011 1111 1111
000 0111 1111 1111
000 1111 1111 1111
001 1111 1111 1111
011 1111 1111 1111
111 1111 1111 1111
0
0
FIGURE 6. HI20203 GLITCH TEST CIRCUIT
0
0
0
0
0
1
1
1
A (mV)
GLITCH ENERGY = (a x t)/2
1
1
1
1
t (ns)
1
FIGURE 7. GLITCH ENERGY
The architecture of the HI20203 is designed to minimize glitch
while providing a manufacturable 10-bit design that does not
require laser trimming to achieve good linearity.
Setting Full Scale
The Full Scale output voltage is set by the Voltage Refer-
ence pin (27). The output voltage performance will vary as
shown in Figure 2.
Glitch
Glitch is caused by the time skew between bits of the
incoming digital data. Typically the switching time of digital
inputs are asymmetrical meaning that the turn off time is
faster than the turn on time (TTL designs). In an ECL system
where the logic levels switch from one non-saturated level to
another, the switching times can be considered close to
symmetrical. This helps to reduce glitch in the D/A. Unequal
delay paths through the device can also cause one current
source to change before another. To minimize this the Intersil
HI20203 employs an internal register, just prior to the current
sources, that is updated on the clock edge. Lastly the worst
case glitch usually happens at the major transition i.e.,
01 1111 1111 to 10 0000 0000. But in the HI20203 the glitch
is moved to the 00 0001 1111 to 11 1110 0000 transition. This
is achieved by the split R2R/segmented current source
architecture. This decreases the amount of current switching
at any one time and makes the glitch practically constant over
The output structure of the HI20203 can handle down to a
75Ω load effectively. To drive a 50Ω load Figure 8 is
suggested. Note the equivalent output load is ~75Ω.
HI20203
50Ω COAX CABLE
39Ω
D/A OUT
(20) I
OUT
100Ω
(18, 19, 21-25) NC
FIGURE 8. HI20203 DRIVING A 50Ω LOAD
10-6
HI20203
Variable Attenuator Capability
The HI20203 can be used in a multiplying mode with a variable The HI20203 incorporates a data register as shown in the
frequency input on the V pin. In order for the part to operate Functional Block Diagram. This register is updated on the
Internal Data Register
REF
correctly a DC bias must be applied and the incoming AC sig- rising edge of the CLK line. The state of the Complement bit
nal should be coupled to the V pin. See Figure 13 for the (COMPL) will determine the data coding. See Table 2.
REF
application circuit. The user must first adjust the DC reference
voltage. The incoming signal must be attenuated so as not to
exceed the maximum (+1.4V) and minimum (+0.5V) reference
input. The typical output Small Signal Bandwidth is 14MHz.
TABLE 2. INPUT CODING TABLE
OUTPUT CODE
INPUT CODE
00 0000 0000
10 0000 0000
11 1111 1111
COMPL = 1
COMPL = 0
Integral Linearity
0
-0.5
-1
-1
-0.5
0
The Integral Linearity is measured using the End Point
method. In the End Point method the gain is adjusted. A line
is then established from the zero point to the end point or
Full Scale of the converter. All codes along the transfer curve
must fall within an error band of 1 LSB of the line. Figure 10
shows the linearity test circuit.
Thermal Considerations
The temperature coefficient of the full scale output voltage
and zero offset voltage depend on the load resistance con-
nected to I
. The larger the load resistor the better (i.e.,
Differential Linearity
OUT
smaller) the temperature coefficient of the D/A. See Figure 3
in the performance curves section.
The Differential Linearity is the difference from the ideal step.
To guarantee monotonicity a maximum of 1 LSB differential
error is allowed. When more than 1 LSB is specified the con-
verter is considered to be missing codes. Figure 10 shows
the linearity test circuit.
Noise Reduction
Digital switching noise must be minimized to guarantee system
specifications. Since 1 LSB corresponds to 1mV for 10-bit
resolution, care must be taken in the layout of a circuit board.
Clock Phase Relationship
Separate ground planes should be used for DV
SS
and
The HI20203 is designed to be operated at very high speed
(i.e., 160MHz). The clock lines should be driven with
ECL100K logic for full performance. Any external data
drivers and clock drivers should be terminated with 50Ω to
minimize reflections and ringing.
AV . They should be connected back at the power supply.
SS
Separate power planes should be used for DV and AV
EE
.
EE
They should be decoupled with a 1µF tantalum capacitor
and a ceramic 0.047µF capacitor positioned as close to the
body of the IC as possible.
Test Circuits and Waveforms
S1
a
b
1
28
S2
a
a
b
a
2
27
S20
S16
a
b
b
I6
S3
a
3
26
25
24
23
22
21
20
19
18
17
16
15
I1
5.2V
b
a
b
b
S4
4.56V
4
S5
a
5
6
I2
b
a
b
a
b
a
b
S11
b
S6
S7
S8
a
7
-0.89V
-1.75V
8
1mA
S19
a
9
-0.89V OR
-1.75V
b
10
11
12
13
14
V1
S17
a
b
S12
a
b
a
S18
S14
I3
I4
a
b
a
I5
a
b
S13
S15
b
5.2V
b
-0.89V
-1.75V
FIGURE 9. CURRENT CONSUMPTION, INPUT CURRENT AND OUTPUT RESISTANCE
10-7
HI20203
Test Circuits and Waveforms (Continued)
LINEARITY ERRORS ARE MEASURED AS FOLLOWS
• • • •
• • • •
• • • •
• • • •
D/A OUT
S1
0
S2
0
S3
0
S7
0
S8
0
V
V
V
0
1
2
“1”
S1
S2
S3
1
2
28
0
0
0
0
1
0
0
0
1
0
*
27
“0”
10K
•
•
•
•
•
•
0.89V
1.75V
3
26
25
24
23
22
21
20
19
18
17
16
15
5.2V
S4
S5
S6
S7
S8
1
1
1
• • • •
1
1
V
255
4
5
INTEGRAL
DIFFERENTIAL
LINEARITY ERROR
LINEARITY ERROR
6
8-BIT
DATA
V
0
7
V
V
V
V
V
V
V
V
V
V
V
V
- V
- V
- V
- V
- V
- V
- V
- V
1
1
2
4
8
0
D/A
OUT
8
2
1
4
3
9
8
7
V
V0
10
11
12
13
14
16
32
64
128
16
32
64
15
31
63
127
V
V
V
128
•
•
•
•
•
•
1.3V
5.2V
V
255
1 SHOT
CLK
Error at individual measurement points are calculated
according to the following definition.
(V
- V )/1023 = V
/255 ≡ 1 LSB.
0(FS)
255
0
FIGURE 10. DIFFERENTIAL LINEARITY ERROR AND LINEARITY ERROR
1
B
/
HD100151
6
10kΩ
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
MSB
82
82
3
D
Q
Q
4
131
131
-5.2V
5
-5.2V CLKF
-5.2V
TO PG
6
-1.3V
7
50Ω
8
C
1
50Ω
39
CLKF
9
OUT
HD100116
TO SCOPE
82
10
11
12
13
14
LSB
100
1
470
131
82
82
A
DL
CLK
CLK
1
-5.2V
131
131
131
DL: Delay line
Capacitors are 0.047µF ceramic chip capacitors unless otherwise specified.
-1.3V
-5.2V
FIGURE 11. MAXIMUM CONVERSION RATE, RISE TIME, FALL TIME, PROPAGATION DELAY, SETUP TIME, HOLD TIME AND
SETTLING TIME
10-8
HI20203
Test Circuits and Waveforms (Continued)
Measuring Settling Time
Settling time is measured as follows. The relationship
between V and V as shown in the D/A output waveform
0(FS)
in Figure 12 is expressed as
-tτ
V = V
(1 - e ).
0(FS)
The settling time for respective accuracy of 10, 9 and 8-bit is
specified as
τ
V = 0.9995 V
0(FS)
0(FS)
0(FS)
V = 0.999 V
V = 0.999 V
which results in the following:
V
= 1V
0(FS)
V
t
t
t
= 7.60τ for 10-bit,
= 6.93τ for 9-bit, and
= 6.24τ for 8-bit,
S
S
S
Rise time (t ) and fall time (t ) are defined as the time interval
r
f
t
to slew from 10% to 90% of full scale voltage (V
):
0(FS)
V = 0.1 V
V = 0.9 V
0(FS)
0(FS)
FIGURE 12. D/A OUTPUT WAVEFORM
and calculated as t = t = 2.20τ.
r
f
The settling time is obtained by combining these expressions:
t
t
t
= 3.45t for 10-bit,
r
S
S
S
= 3.15t for 9-bit, and
r
= 6.24t for 8-bit
r
10-9
HI20203
Test Circuits and Waveforms (Continued)
Adjust so that the voltage at point B
becomes -1V with no AC input.
“1”
10kΩ
0.1µF
OSC
1
28
27
26
25
24
23
22
21
2
3
0.047µ
51
A
4
-5.2V
5
6
7
8
B
TO SCOPE
9
20
19
18
17
16
15
10
11
12
CLK
CLK
13
14
A GND
D GND
-5.2V
FIGURE 13A.
V
V
-0.62V
WAVEFORM AT POINT A
EE
EE
-0.31V
FIGURE 13B.
1V
AT 1MHz
-1V
P-P
WAVEFORM AT POINT B
FIGURE 13C.
FIGURE 13. MULTIPLYING BANDWIDTH
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10-10
相关型号：
HI20206JCP
TRIPLE, PARALLEL, 8 BITS INPUT LOADING, 0.016 us SETTLING TIME, 8-BIT DAC, PDIP42
ROCHESTER
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