HI5731BIPZ [INTERSIL]
12-Bit, 100MSPS, High Speed D/A Converter; 12位， 100MSPS ，高速D / A转换器
| 型号： | HI5731BIPZ |
| 厂家： | 
Intersil |
| 描述： | 12-Bit, 100MSPS, High Speed D/A Converter |
| 文件： | 总17页 (文件大小：529K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HI5731
®
Data Sheet
September 15, 2004
FN4070.9
12-Bit, 100MSPS, High Speed D/A
Converter
Features
• Pb-free Available as an Option
The HI5731 is a 12-bit, 100MSPS, D/A converter which is
implemented in the Intersil BiCMOS 10V (HBC-10) process.
Operating from +5V and -5.2V, the converter provides
-20.48mA of full scale output current and includes an input
data register and bandgap voltage reference. Low glitch
energy and excellent frequency domain performance are
achieved using a segmented architecture. The digital inputs
are TTL/CMOS compatible and translated internally to ECL.
All internal logic is implemented in ECL to achieve high
switching speed with low noise. The addition of laser
trimming assures 12-bit linearity is maintained along the
entire transfer curve.
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . .100MSPS
• Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .650mW
• Integral Linearity Error . . . . . . . . . . . . . . . . . . . . 0.75 LSB
• Low Glitch Energy . . . . . . . . . . . . . . . . . . . . . . . . . 3.0pV-s
• TTL/CMOS Compatible Inputs
• Improved Hold Time. . . . . . . . . . . . . . . . . . . . . . . . 0.25ns
• Excellent Spurious Free Dynamic Range
Applications
• Cellular Base Stations
• GSM Base Stations
Ordering Information
TEMP.
PKG. DWG.
#
• Wireless Communications
• Direct Digital Frequency Synthesis
• Signal Reconstruction
PART NUMBER RANGE (°C)
PACKAGE
HI5731BIP
-40 to 85
-40 to 85
28 Ld PDIP
E28.6
E28.6
HI5731BIPZ
(See Note)
28 Ld PDIP
(Pb-free)
• Test Equipment
HI5731BIB
-40 to 85
28 Ld SOIC
M28.3
M28.3
M28.3
• High Resolution Imaging Systems
• Arbitrary Waveform Generators
HI5731BIB-T
28 Ld SOIC Tape and Reel
HI5731BIBZ
(See Note)
-40 to 85
28 Ld SOIC
(Pb-free)
Pinout
HI5731-EVS
25
Evaluation Board (SOIC)
HI5731
(PDIP, SOIC)
TOP VIEW
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020C.
D11 (MSB)
1
2
3
4
5
6
7
8
9
DGND
28
27 AGND
26
D10
D9
D8
D7
D6
D5
D4
D3
REF OUT
25 CTRL OUT
24 CTRL IN
23 R
SET
22 AV
EE
OUT
21 I
20
I
OUT
19 ARTN
18 DV
D2 10
D1 11
EE
17 DGND
16 DV
D0 (LSB) 12
NC 13
CC
15 CLOCK
NC 14
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002, 2004. All Rights Reserved
HI5731
Typical Application Circuit
+5V
HI5731
0.01µF
DV
(16)
CC
D11 (MSB) (1)
D10 (2)
D9 (3)
D11
0.1µF
D10
D9
D8
D7
D6
D5
D4
D3
(24) CTRL IN
(25) CTRL OUT
D8 (4)
-5.2V (AV
)
EE
D7 (5)
(26) REF OUT
D6 (6)
D5 (7)
D/A OUT
(21) I
OUT
64Ω
D4 (8)
D3 (9)
64Ω
D2 (10)
D2
D1
D0
(20) I
OUT
D1 (11)
(23) R
SET
D0 (LSB) (12)
976Ω
(19) ARTN
(27) AGND
CLK (15)
50Ω
DGND (17, 28)
(22) AV
EE
DV (18)
EE
0.01µF
0.1µF
0.01µF
0.1µF
- 5.2V (AV
)
- 5.2V (DV
)
EE
EE
Functional Block Diagram
(LSB) D0
D1
D2
D3
8 LSBs
CURRENT
CELLS
R2R
NETWORK
D4
DATA
BUFFER/
LEVEL
12-BIT
MASTER
REGISTER
D5
ARTN
SLAVE
REGISTER
D6
SHIFTER
227Ω
227Ω
D7
D8
15
15
15
D9
D10
UPPER
4-BIT
DECODER
SWITCHED
CURRENT
CELLS
I
I
OUT
(MSB) D11
OUT
REF CELL
CTRL
IN
CLK
25Ω
+
OVERDRIVEABLE
VOLTAGE
CTRL
OUT
-
REFERENCE
AV
AGND DV
DGND DV
REF OUT
R
SET
EE
EE
CC
2
HI5731
Absolute Maximum Ratings
Thermal Information
o
Digital Supply Voltage V
to DGND . . . . . . . . . . . . . . . . . . . +5.5V
Thermal Resistance (Typical, Note 1)
θ
( C/W)
CC
JA
Negative Digital Supply Voltage DV to DGND . . . . . . . . . . -5.5V
EE
Negative Analog Supply Voltage AV to AGND, ARTN . . . . . -5.5V
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature
HI5731BIx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 C
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
50
70
EE
Digital Input Voltages (D11-D0, CLK) to DGND. . . . . DV
to -0.5V
CC
Internal Reference Output Current. . . . . . . . . . . . . . . . . . . . ±2.5mA
Voltage from CTRL IN to AV . . . . . . . . . . . . . . . . . . . . 2.5V to 0V
o
o
o
EE
Control Amplifier Output Current . . . . . . . . . . . . . . . . . . . . . ±2.5mA
Reference Input Voltage Range. . . . . . . . . . . . . . . . . .-3.7V to AV
o
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C
(SOIC - Lead Tips Only)
EE
) . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
Analog Output Current (I
OUT
Operating Conditions
o
o
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications AV , DV = -4.94 to -5.46V, V = +4.75 to +5.25V, V = Internal
REF
EE
EE
CC
o
T = 25 C for All Typical Values
A
HI5731BI
= -40 C TO 85 C
o
o
T
A
PARAMETER
SYSTEM PERFORMANCE
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Resolution
12
-
-
-
Bits
LSB
LSB
µA
Integral Linearity Error, INL
Differential Linearity Error, DNL
(Note 4) (“Best Fit” Straight Line)
(Note 4)
0.75
0.5
20
1.5
1.0
75
10
-
-
Offset Error, I
(Note 4)
-
OS
Full Scale Gain Error, FSE
Full Scale Gain Drift
(Notes 2, 4)
-
1
%
With Internal Reference
-
±150
ppm
o
FSR/ C
o
Offset Drift Coefficient
(Note 3)
(Note 3)
(Note 3)
-
-
-
20.48
-
0.05
µA/ C
Full Scale Output Current, I
-
mA
V
FS
Output Voltage Compliance Range
DYNAMIC CHARACTERISTICS
Throughput Rate
-1.25
0
100
-
-
-
-
MSPS
ns
Output Voltage Full Scale Step
To ±0.5 LSB Error Band R = 50Ω
20
L
Settling Time, t
, Full Scale
(Note 3)
SETT
Singlet Glitch Area, GE (Peak)
Doublet Glitch Area, (Net)
Output Slew Rate
R
= 50Ω (Note 3)
-
-
-
-
-
-
-
-
-
-
-
5
3
-
-
-
-
-
-
-
-
-
-
-
pV-s
pV-s
V/µs
ps
L
R = 50Ω, DAC Operating in Latched Mode (Note 3)
1,000
675
470
85
L
Output Rise Time
R = 50Ω, DAC Operating in Latched Mode (Note 3)
L
Output Fall Time
R = 50Ω, DAC Operating in Latched Mode (Note 3)
ps
L
Spurious Free Dynamic Range within a Window
(Note 3)
f
f
f
f
f
f
= 10MSPS, f
= 20MSPS, f
= 40MSPS, f
= 50MSPS, f
= 80MSPS, f
= 1.23MHz, 2MHz Span
= 5.055MHz, 2MHz Span
= 16MHz, 10MHz Span
= 10.1MHz, 2MHz Span
= 5.1MHz, 2MHz Span
dBc
dBc
dBc
dBc
dBc
dBc
CLK
CLK
CLK
CLK
CLK
CLK
OUT
OUT
OUT
OUT
OUT
77
75
80
78
= 100MSPS, f
= 10.1MHz, 2MHz Span
79
OUT
3
HI5731
Electrical Specifications AV , DV = -4.94 to -5.46V, V = +4.75 to +5.25V, V = Internal
REF
EE
EE
CC
o
T = 25 C for All Typical Values (Continued)
A
HI5731BI
= -40 C TO 85 C
o
o
T
A
PARAMETER
TEST CONDITIONS
MIN
TYP
70
MAX
UNITS
dBc
Spurious Free Dynamic Range to Nyquist
(Note 3)
f
f
f
= 40MSPS, f
= 80MSPS, f
= 2.02MHz, 20MHz Span
= 2.02MHz, 40MHz Span
-
-
-
-
-
-
CLK
CLK
CLK
OUT
OUT
70
dBc
= 100MSPS, f
OUT
= 2.02MHz, 50MHz Span
69
dBc
REFERENCE/CONTROL AMPLIFIER
Internal Reference Voltage, V
(Note 4)
(Note 3)
(Note 3)
-1.27
-
-1.23
175
-
-1.17
-
V
REF
o
Internal Reference Voltage Drift
µV/ C
Internal Reference Output Current Sink/Source
Capability
-125
+50
µA
Internal Reference Load Regulation
Input Impedance at REF OUT pin
I
= 0 to I
= -125µA
REF
-
-
-
-
-
-
50
1.4
3
-
-
-
-
-
-
µV
kΩ
REF
(Note 3)
Amplifier Large Signal Bandwidth (0.6V
Amplifier Small Signal Bandwidth (0.1V
Reference Input Impedance
)
Sine Wave Input, to Slew Rate Limited (Note 3)
Sine Wave Input, to -3dB Loss (Note 3)
(Note 3)
MHz
MHz
kΩ
P-P
)
10
12
200
P-P
Reference Input Multiplying Bandwidth (CTL IN)
R
= 50Ω, 100mV Sine Wave, to -3dB Loss at I
MHz
L
OUT
(Note 3)
DIGITAL INPUTS (D9-D0, CLK, INVERT)
Input Logic High Voltage, V
(Note 4)
(Note 4)
(Note 4)
(Note 4)
(Note 3)
2.0
-
-
V
IH
Input Logic Low Voltage, V
-
-
-
-
-
-
0.8
400
700
-
V
IL
Input Logic Current, I
Input Logic Current, I
µA
µA
pF
IH
-
IL
Digital Input Capacitance, C
3.0
IN
TIMING CHARACTERISTICS
Data Setup Time, t
See Figure 1 (Note 3)
See Figure 1 (Note 3)
See Figure 1 (Note 3)
See Figure 1 (Note 3)
3.0
0.5
-
2.0
0.25
4.5
-
-
-
-
-
ns
ns
ns
ns
SU
Data Hold Time, t
HLD
Propagation Delay Time, t
PD
CLK Pulse Width, t
, t
POWER SUPPLY CHARACTERISTICS
3.0
PW1 PW2
I
I
I
(Note 4)
(Note 4)
(Note 4)
(Note 4)
-
-
-
-
-
42
70
13
650
5
50
85
20
-
mA
mA
EEA
EED
CCD
mA
Power Dissipation
Power Supply Rejection Ratio
NOTES:
mW
µA/V
V
±5%, V ±5%
EE
-
CC
2. Gain Error measured as the error in the ratio between the full scale output current and the current through R
ratio should be 16.
(typically 1.28mA). Ideally the
SET
3. Parameter guaranteed by design or characterization and not production tested.
o
4. All devices are 100% tested at 25 C.
5. Dynamic Range must be limited to a 1V swing within the compliance range.
4
HI5731
Timing Diagrams
50%
CLK
1
GLITCH AREA =
/ (H x W)
2
V
D11-D0
HEIGHT (H)
1
± / LSB ERROR BAND
2
I
OUT
t(ps)
WIDTH (W)
t
SETT
t
PD
FIGURE 1. FULL SCALE SETTLING TIME DIAGRAM
FIGURE 2. PEAK GLITCH AREA (SINGLET) MEASUREMENT
METHOD
t
t
PW2
PW1
50%
CLK
t
t
SU
t
SU
SU
t
t
t
HLD
HLD
HLD
D11-D0
t
PD
I
OUT
t
t
PD
PD
FIGURE 3. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
5
HI5731
Typical Performance Curves
680
-1.21
CLOCK FREQUENCY DOES NOT
ALTER POWER DISSIPATION
-1.23
-1.25
-1.27
640
600
560
-1.29
-50
-30
-10
10
30
50
70
90
-50
-30
-10
10
30
50
70
90
TEMPERATURE
TEMPERATURE
FIGURE 4. TYPICAL POWER DISSIPATION OVER
TEMPERATURE
FIGURE 5. TYPICAL REFERENCE VOLTAGE OVER
TEMPERATURE
1.5
0.8
0.4
0.5
-0.5
1.5
0.0
-0.4
-0.8
400
1000
1600
2200
2800
3400
4000
0
600
1200
1800
2400
3000
3600
4200
CODE
CODE
FIGURE 6. TYPICAL INL
FIGURE 7. TYPICAL DNL
ATTEN 20dB
RL -10.0dBm
∆MKR -87.33dB
28
-73kHz
10dB/
f
= 10MSPS
C
24
20
16
12
S
C
-40
-20
-0
20
40
60
80
100
TEMPERATURE
CENTER 1.237MHz
SPAN 2.000MHz
FIGURE 8. OFFSET CURRENT OVER TEMPERATURE
FIGURE 9. SPURIOUS FREE DYNAMIC RANGE = 87.3dBc
6
HI5731
Typical Performance Curves (Continued)
ATTEN 20dB
RL -10.0dBm
∆MKR -75.17dB
ATTEN 20dB
RL -10.0dBm
∆MKR -76.16dB
-53kHz
10dB/
-70kHz
10dB/
f
= 40MSPS
f
= 20MSPS
C
C
S
C
C
CENTER 5.055MHz
SPAN 2.000MHz
CENTER 16.00MHz
SPAN 10.00MHz
FIGURE 10. SPURIOUS FREE DYNAMIC RANGE = 76.16dBc
FIGURE 11. SPURIOUS FREE DYNAMIC RANGE = 75.17dBc
ATTEN 20dB
RL -10.0dBm
∆MKR -81.67dB
ATTEN 20dB
RL -10.0dBm
∆MKR -77.00dB
-953kHz
-93kHz
10dB/
10dB/
f
= 50MSPS
f
= 80MSPS
C
C
S
C
C
CENTER 10.100MHz
SPAN 2.000MHz
CENTER 5.097MHz
SPAN 2.000MHz
FIGURE 12. SPURIOUS FREE DYNAMIC RANGE = -81.67dBc
FIGURE 13. SPURIOUS FREE DYNAMIC RANGE = 77dBc
ATTEN 20dB
RL -10.0dBm
∆MKR -85.60dB
ATTEN 20dB
RL -10.0dBm
∆MKR -85.50dB
-33kHz
10dB/
73kHz
10dB/
f
= 100MSPS
C
f
= 100MSPS
C
S
C
S
C
CENTER 2.027MHz
SPAN 2.000MHz
CENTER 5.000MHz
SPAN 2.000MHz
FIGURE 14. SPURIOUS FREE DYNAMIC RANGE = -85.60dBc
FIGURE 15. SPURIOUS FREE DYNAMIC RANGE = 85.5dBc
7
HI5731
Typical Performance Curves (Continued)
ATTEN 20dB
RL -10.0dBm
∆MKR -80.50dB
-807kHz
ATTEN 20dB
RL -10.0dBm
∆MKR -72.17dB
-467kHz
10dB/
10dB/
f
= 100MSPS
f
= 100MSPS
C
C
S
C
CENTER 10.133MHz
SPAN 2.000MHz
CENTER 26.637MHz
SPAN 2.000MHz
FIGURE 16. SPURIOUS FREE DYNAMIC RANGE = 80.5dBc
FIGURE 17. SPURIOUS FREE DYNAMIC RANGE = 72.17dBc
ATTEN 20dB
RL -10.0dBm
∆MKR -71.16dB
ATTEN 20dB
RL -10.0dBm
∆MKR -70.50dB
2.99MHz
1.98MHz
10dB/
10dB/
f
f
= 40MSPS
= 2.02MHz
f
f
= 80MSPS
= 2.02MHz
C
O
C
O
S
C
S
C
START FREQUENCY 500kHz
STOP FREQUENCY 20MHz
START FREQUENCY 500kHz
STOP FREQUENCY 40MHz
FIGURE 18. SPURIOUS FREE DYNAMIC RANGE = 71.16dBc
FIGURE 19. SPURIOUS FREE DYNAMIC RANGE = 70.5dBc
ATTEN 20dB
RL -10.0dBm
∆MKR -70.00dB
4.13MHz
10dB/
f
f
= 100MSPS
= 2.02MHz
C
O
S
C
START FREQUENCY 500kHz
STOP FREQUENCY 50MHz
FIGURE 20. SPURIOUS FREE DYNAMIC RANGE = 70dBc
8
HI5731
Pin Descriptions
PIN NUMBER
PIN NAME
PIN DESCRIPTION
1-12
D11 (MSB) thru Digital Data Bit 11, the Most Significant Bit thru Digital Data Bit 0, the Least Significant Bit.
D0 (LSB)
15
13, 14
16
CLK
NC
Data Clock Pin DC to 100MSPS.
No Connect.
DV
Digital Logic Supply +5V.
Digital Ground.
CC
DGND
17, 28
18
DV
-5.2V Logic supply.
EE
23
R
External resistor to set the full scale output current. I = 16 x (V
FS
/ R ). Typically 976Ω.
SET
SET
REF OUT
27
AGND
ARTN
Analog Ground supply current return pin.
Analog Signal Return for the R/2R ladder.
Current Output Pin.
19
21
I
I
OUT
OUT
20
Complementary Current Output Pin.
-5.2V Analog Supply.
22
AV
EE
24
CTRL IN
CTRL OUT
REF OUT
Input to the current source base rail. Typically connected to CTRL OUT and a 0.1µF capacitor to AV . Allows
external control of the current sources.
EE
25
26
Control Amplifier Out. Provides precision control of the current sources when connected to CTRL IN such that
I
= 16 x (V
/ R ).
FS
REF OUT
SET
-1.23V (Typ) bandgap reference voltage output. Can sink up to 125µA or be overdriven by an external
reference capable of delivering up to 2mA.
Detailed Description
The HI5731 is a 12-bit, current out D/A converter. The DAC can
convert at 100MSPS and runs on +5V and -5.2V supplies. The
architecture is an R/2R and segmented switching current cell
arrangement to reduce glitch. Laser trimming is employed to
tune linearity to true 12-bit levels. The HI5731 achieves its low
power and high speed performance from an advanced
BiCMOS process. The HI5731 consumes 650mW (typical) and
has an improved hold time of only 0.25ns (typical). The HI5731
is an excellent converter for use in communications applications
and high performance instrumentation systems.
to minimize reflections and clock noise into the part proper
termination should be used. In PCB layout clock runs should
be kept short and have a minimum of loads. To guarantee
consistent results from board to board controlled impedance
PCBs should be used with a characteristic line impedance
Z
of 50Ω.
O
To terminate the clock line, a shunt terminator to ground is
the most effective type at a 100MSPS clock rate. A typical
value for termination can be determined by the equation:
R = Z ,
T
O
Digital Inputs
for the termination resistor. For a controlled impedance
board with a Z of 50Ω, the R = 50Ω. Shunt termination is
best used at the receiving end of the transmission line or as
close to the HI5731 CLK pin as possible.
The HI5731 is a TTL/CMOS compatible D/A. Data is latched
by a Master register. Once latched, data inputs D0 (LSB)
thru D11 (MSB) are internally translated from TTL to ECL.
The internal latch and switching current source controls are
implemented in ECL technology to maintain high switching
speeds and low noise characteristics.
O
T
HI5731
DAC
Z
= 50Ω
O
CLK
Decoder/Driver
R
= 50Ω
T
The architecture employs a split R/2R ladder and
Segmented Current source arrangement. Bits D0 (LSB) thru
D7 directly drive a typical R/2R network to create the binary
weighted current sources. Bits D8 thru D11 (MSB) pass thru
a “thermometer” decoder that converts the incoming data
into 15 individual segmented current source enables. This
split architecture helps to improve glitch, thus resulting in a
more constant glitch characteristic across the entire output
transfer function.
FIGURE 21. CLOCK LINE TERMINATION
Rise and Fall times and propagation delay of the line will be
affected by the Shunt Terminator. The terminator should be
connected to DGND.
Noise Reduction
To reduce power supply noise, separate analog and digital
power supplies should be used with 0.1µF and 0.01µF
ceramic capacitors placed as close to the body of the
Clocks and Termination
The internal 12-bit register is updated on the rising edge of
the clock. Since the HI5731 clock rate can run to 100MSPS,
9
HI5731
HI5731 as possible on the analog (AV ) and digital (DV
EE
supplies. The analog and digital ground returns should be
)
required. The lower input bandwidth can be calculated using
the following formula:
EE
connected together back at the device to ensure proper
1
-------------------------------------------
C
=
.
IN
operation on power up. The V
power pin should also be
CC
(2π)(1400)(f
)
IN
decoupled with a 0.1µF capacitor.
For multiplying frequencies above 100kHz, the CTRL IN pin
can be driven directly as seen in Figure 24.
Reference
The internal reference of the HI5731 is a -1.23V (typical)
bandgap voltage reference with 175µV/ C of temperature
HI5731
o
CTRL OUT
drift (typical). The internal reference is connected to the
C
2
Control Amplifier which in turn drives the segmented current
cells. Reference Out (REF OUT) is internally connected to
the Control Amplifier. The Control Amplifier Output (CTRL
OUT) should be used to drive the Control Amplifier Input
200Ω
AV
EE
V
C
1
IN
CTRL IN
50Ω
(CTRL IN) and a 0.1µF capacitor to analog V . This
EE
improves settling time by providing an AC ground at the
current source base node. The Full Scale Output Current is
FIGURE 24. HIGH FREQUENCY MULTIPLYING BANDWIDTH
CIRCUIT
controlled by the REF OUT pin and the set resistor (R
The ratio is:
).
SET
The nominal input/output relationship is defined as:
I
(Full Scale) = (V ) x 16,
/R
OUT
REF OUT SET
∆V
IN
-------------
.
∆I
=
OUT
The internal reference (REF OUT) can be overdriven with a
more precise external reference to provide better
performance over temperature. Figure 22 illustrates a typical
external reference configuration.
80Ω
In order to prevent the full scale output current from
exceeding 20.48mA, the R resistor must be adjusted
SET
according to the following equation:
16V
REF
-----------------------------------------------------------------------------------------------
.
R
=
SET
HI5731
V
IN(PEAK)
-----------------------------
(FULL SCALE) –
I
OUT
80Ω
-1.25V
R
(26) REF OUT
The circuit in Figure 24 can be tuned to adjust the lower
cutoff frequency by adjusting capacitor values. Table 1 below
illustrates the relationship.
-5.2V
FIGURE 22. EXTERNAL REFERENCE CONFIGURATION
TABLE 1. CAPACITOR SELECTION
Multiplying Capability
f
C1
C2
1µF
IN
The HI5731 can operate in two different multiplying
configurations. For frequencies from DC to 100kHz, a signal
100kHz
>1MHz
0.01µF
0.001µF
0.1µF
of up to 0.6V
can be applied directly to the REF OUT pin
P-P
as shown in Figure 23.
Also, the input signal must be limited to 1V
distortion in the DAC output current caused by excessive
modulation of the internal current sources.
to avoid
P-P
HI5731
CTRL OUT
CTRL IN
0.01µF
Outputs
AV
EE
The outputs I
and I
are complementary current
outputs. Current is steered to either I or I in
OUT
OUT
REF OUT
RSET
OUT
OUT
C
(OPTIONAL)
IN
V
IN
proportion to the digital input code. The sum of the two
currents is always equal to the full scale current minus one
LSB. The current output can be converted to a voltage by
using a load resistor. Both current outputs should have the
same load resistor (64Ω typically). By using a 64Ω load on
FIGURE 23. LOW FREQUENCY MULTIPLYING BANDWIDTH
CIRCUIT
the output, a 50Ω effective output resistance (R
) is
OUT
achieved due to the 227Ω (±15%) parallel resistance seen
looking back into the output. This is the nominal value of the
R2R ladder of the DAC. The 50Ω output is needed for
matching the output with a 50Ω line. The load resistor should
The signal must have a DC value such that the peak
negative voltage equals -1.25V. Alternately, a capacitor can
be placed in series with REF OUT if DC multiplying is not
10
HI5731
be chosen so that the effective output resistance (R
matches the line resistance. The output voltage is:
)
as glitch when changing the DAC output. Units are typically
specified in picoVolt-seconds (pV-s).
OUT
V
= I
OUT
x R .
OUT
OUT
HI5731
I
is defined in the reference section. I
is not trimmed
OUT
OUT
to 12 bits, so it is not recommended that it be used in
conjunction with I in a differential-to-single-ended
100MHz
LOW PASS
FILTER
SCOPE
(21) I
OUT
OUT
application. The compliance range of the output is from -
64Ω
50Ω
1.25V to 0V, with a 1V
range.
voltage swing allowed within this
P-P
TABLE 2. INPUT CODING vs CURRENT OUTPUT
FIGURE 25. GLITCH TEST CIRCUIT
INPUT CODE (D11-D0)
1111 1111 1111
I
(mA)
I
(mA)
OUT
OUT
-20.48
0
1000 0000 0000
-10.24
0
-10.24
-20.48
0000 0000 0000
Settling Time
a (mV)
The settling time of the HI5731 is measured as the time it
1
takes for the output of the DAC to settle to within a ± / LSB
2
GLITCH ENERGY = (a x t)/2
error band of its final value during a full scale (code 0000...
to 1111.... or 1111... to 0000...) transition. All claims made by
Intersil with respect to the settling time performance of the
HI5731 have been fully verified by the National Institute of
Standards and Technology (NIST) and are fully traceable.
t (ns)
FIGURE 26. MEASURING GLITCH ENERGY
Glitch
Applications
The output glitch of the HI5731 is measured by summing the
area under the switching transients after an update of the
DAC. Glitch is caused by the time skew between bits of the
incoming digital data. Typically, the switching time of digital
inputs are asymmetrical meaning that the turn off time is
faster than the turn on time (TTL designs). Unequal delay
paths through the device can also cause one current source
to change before another. In order to minimize this, the
Intersil HI5731 employes an internal register, just prior to the
current sources, which is updated on the clock edge. Lastly,
the worst case glitch on traditional D/A converters usually
occurs at the major transition (i.e., code 2047 to 2048).
However, due to the split architecture of the HI5731, the
glitch is moved to the 255 to 256 transition (and every
subsequent 256 code transitions thereafter). This split R/2R
segmented current source architecture, which decreases the
amount of current switching at any one time, makes the
glitch practically constant over the entire output range. By
making the glitch a constant size over the entire output range
this effectively integrates this error out of the end application.
Bipolar Applications
To convert the output of the HI5731 to a bipolar 4V swing,
the following applications circuit is recommended. The
reference can only provide 125µA of drive, so it must be
buffered to create the bipolar offset current needed to
generate the -2V output with all bits ‘off’. The output current
must be converted to a voltage and then gained up and
offset to produce the proper swing. Care must be taken to
compensate for the voltage swing and error.
5kΩ
-
-
REF OUT
(26)
+
+
5kΩ
60Ω
1
1
/
CA2904
/
CA2904
2
2
0.1µF
240Ω
240Ω
HI5731
In measuring the output glitch of the HI5731 the output is
terminated into a 64Ω load. The glitch is measured at any
one of the current cell carry (code 255 to 256 transition or
any multiple thereof) throughout the DACs output range.
50Ω
I
V
OUT
OUT
(21)
-
+
HFA1100
The glitch energy is calculated by measuring the area under
the voltage-time curve. Figure 26 shows the area considered
FIGURE 27. BIPOLAR OUTPUT CONFIGURATION
11
HI5731
1
step to settle within an / LSB error band. This is used by
2
Interfacing to the HSP45106 NCO-16
applications reconstructing highly correlated signals such as
sine waves with more than 5 points per cycle.
The HSP45106 is a 16-bit, Numerically Controlled Oscillator
(NCO). The HSP45106 can be used to generate various
modulation schemes for Direct Digital Synthesis (DDS)
applications. Figure 28 shows how to interface an HI5731 to
the HSP45106.
Glitch Area, GE, is the switching transient appearing on the
output during a code transition. It is measured as the area
under the curve and expressed as a picoVolt-time
specification (typically pV-s).
Interfacing to the HSP45102 NCO-12
The HSP45102 is a 12-bit, Numerically Controlled Oscillator
(NCO). The HSP45102 can be used to generate various
modulation schemes for Direct Digital Synthesis (DDS)
applications. Figure 29 shows how to interface an HI5731 to
the HSP45102.
Differential Gain, ∆A , is the gain error from an ideal sine
wave with a normalized amplitude.
V
Differential Phase, ∆Φ, is the phase error from an ideal sine
wave.
Signal to Noise Ratio, SNR, is the ratio of a fundamental to
This high level block diagram is that of a basic PSK
modulator. In this example the encoder generates the PSK
waveform by driving the Phase Modulation Inputs (P1, P0) of
the HSP45102. The P1-0 inputs impart a phase shift to the
carrier wave as defined in Table 2.
the noise floor of the analog output. The first 5 harmonics
1
are ignored, and an output filter of / the clock frequency is
2
used to eliminate alias products.
Total Harmonic Distortion, THD, is the ratio of the DAC
output fundamental to the RMS sum of the harmonics. The
1
TABLE 3. PHASE MODULATION INPUT CODING
first 5 harmonics are included, and an output filter of / the
2
P1
0
P0
0
PHASE SHIFT (DEGREES)
clock frequency is used to eliminate alias products.
0
Spurious Free Dynamic Range, SFDR, is the amplitude
0
1
90
difference from a fundamental to the largest harmonically or
non-harmonically related spur. A sine wave is loaded into the
1
1
0
270
180
D/A and the output filtered at / the clock frequency to
2
1
1
eliminate noise from clocking alias terms.
Intermodulation Distortion, IMD, is the measure of the
sum and difference products produced when a two tone
input is driven into the D/A. The distortion products created
will arise at sum and difference frequencies of the two tones.
IMD can be calculated using the following equation:
The data port of the HSP45102 drives the 12-bit HI5731
DAC which converts the NCO output into an analog
waveform. The output filter connected to the DAC can be
tailored to remove unwanted spurs for the desired carrier
frequency. The controller is used to load the desired center
frequency and control the HSP45102. The HI5731 coupled
with the HSP45102 make an inexpensive PSK modulator
with Spurious Free performance down to -76dBc.
20Log (RMS of Sum and Difference Distortion Products)
------------------------------------------------------------------------------------------------------------------------------------------------------
IMD =
.
(RMS Amplitude of the Fundamental)
Definition of Specifications
Integral Linearity Error, INL, is the measure of the worst
case point that deviates from a best fit straight line of data
values along the transfer curve.
Differential Linearity Error, DNL, is the measure of the
error in step size between adjacent codes along the
converter’s transfer curve. Ideally, the step size is 1 LSB from
one code to the next, and the deviation from 1 LSB is known
as DNL. A DNL specification of greater than -1 LSB
guarantees monotonicity.
Feedthru, is the measure of the undesirable switching noise
coupled to the output.
Output Voltage Full Scale Settling Time, is the time
required from the 50% point on the clock input for a full scale
1
step to settle within an ± / LSB error band.
2
Output Voltage Small Scale Settling Time, is the time
required from the 50% point on the clock input for a 100mV
12
HI5731
U2
K9
33MSPS
CLK
CLK
C11
B11
C10
MOD2
MOD1
BASEBAND
BIT
STREAM
TO RF
UP-CONVERT
STAGE
FILTER
ENCODER
U1
DV
MOD0
16
R1
64
R2
64
V
CC
CC
21
20
L1
A11
I
I
OUT
OUT
PMSEL
DACSTRB
F10
F9
F11
H11
G11
G9
1
2
3
4
5
6
7
8
9
K3
L2
L3
L4
J5
K5
L5
K6
J6
SIN15
SIN14
SIN13
SIN12
SIN11
SIN10
SIN9
SIN8
SIN7
SIN6
SIN5
SIN4
SIN3
SIN2
SIN1
SIN0
D11 (MSB)
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
ENPOREG
ENOFREG
ENCFREG
ENPHAC
ENTIREG
INHOFR
24
25
CNTRL IN
-5.2V_A
-5.2V_A
C2 0.1µF
J11
G10
INITPAC
INITTAC
CNTRL OUT
C1 0.01µF
J7
10
11
12
D10
J10
TEST
L7
L6
L8
K8
L9
L10
V
PARSER
BINFMT
CC
D0 (LSB)
REF OUT
26
23
19
CONTROLLER
K11
15
CLK
R3
R4
50
R
28
17
SET
B8
A8
B6
B7
A7
C7
C6
A6
A5
C5
A4
B4
A3
A2
B3
A1
C15_MSB
C4
DGND
DGND
976
C13
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
ARET
27
22
AV
AV
SS
EE
C2
B1
C1
D1
E3
E2
E1
F2
F3
G3
G1
G2
H1
H2
J1
COS15
COS14
COS13
COS12
COS11
COS10
COS9
COS8
COS7
COS6
COS5
COS4
COS3
COS2
COS1
COS0
18
-5.2V_A
DV
EE
-5.2V_D
HI5731
L1
-5.2V_D
-5.2V_A
10µH
C0
B10
B9
A10
E11
E9
A2
A1
A0
CS
WR
L2
10µH
K1
H10
K2
B2
V
V
PACI
TICO
CC
CC
OES
OEC
J2
HSP45106
FIGURE 28. MODULATOR USING THE HI5731 AND THE HSP45106 16-BIT NCO
13
HI5731
TO RF
UP-CONVERT
STAGE
FILTER
U2
DV
16
R1
64
R2
64
U1
V
CC
CC
21
20
I
I
OUT
OUT
16
19
20
40MSPS
CLK
6
5
4
3
2
1
2
3
4
5
6
7
8
9
CLK
OUT11
D11 (MSB)
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
I
BASEBAND
BIT
STREAM
P1
OUT10
OUT9
OUT8
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
OUT0
ENCODER
Q
P0
18
17
12
9
LOAD#
24
25
1
CNTRL IN
-5.2V_A
-5.2V_A
C2 0.1µF
28
27
26
25
24
23
TXFR#
CNTRL OUT
C1 0.01µF
ENPHAC#
SEL_L/M#
10
11
12
CONTROL
BUS
D0 (LSB)
CONTROLLER
26
23
REF OUT
15
14
13
10
11
CLK
SCLK
SD
R3
R4
50
RSET
28
17
DGND
DGND
976
19
SFTEN#
MSB/LSB#
ARET
27
22
AV
AV
SS
EE
HSP45102
18
-5.2V_A
DV
EE
-5.2V_D
HI5731
L1
10
L2
-5.2V_D
-5.2V_A
µ
H
10µH
FIGURE 29. PSK MODULATOR USING THE HI5731 AND THE HSP45102 12-BIT NCO
14
HI5731
Die Characteristics
DIE DIMENSIONS
PASSIVATION
161.5 mils x 160.7 mils x 19 mils
Type: Sandwich Passivation
Undoped Silicon Glass (USG) + Nitride
Thickness: USG - 8kÅ, Nitride - 4.2kÅ
Total 12.2kÅ + 2kÅ
METALLIZATION
Type: AlSiCu
Thickness: M1 - 8kÅ, M2 - 17kÅ
SUBSTRATE POTENTIAL (POWERED UP)
V
EED
Metallization Mask Layout
HI5731
D8
D9
D10
D11
DGND
CTRL OUT
CTRL IN
D7
D6
R
SET
D5
AV
EE
D4
I
OUT
D3
D2
I
OUT
ARTN
D1
D0
CLK
DV
DGND
DV
EE
CC
15
HI5731
Dual-In-Line Plastic Packages (PDIP)
E28.6 (JEDEC MS-011-AB ISSUE B)
N
28 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INCHES
MILLIMETERS
INDEX
1 2
3
N/2
AREA
SYMBOL
MIN
MAX
0.250
-
MIN
-
MAX
6.35
-
NOTES
-B-
-C-
A
A1
A2
B
-
4
-A-
0.015
0.125
0.014
0.030
0.008
1.380
0.005
0.600
0.485
0.39
3.18
0.356
0.77
0.204
4
D
E
0.195
0.022
0.070
0.015
1.565
-
4.95
0.558
1.77
0.381
39.7
-
-
BASE
PLANE
A2
A
-
SEATING
PLANE
B1
C
8
L
C
L
-
D1
B1
eA
A1
A
D1
e
D
35.1
5
eC
C
B
D1
E
0.13
15.24
12.32
5
eB
0.010 (0.25) M
C
B S
0.625
0.580
15.87
14.73
6
NOTES:
E1
e
5
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
0.100 BSC
0.600 BSC
2.54 BSC
15.24 BSC
-
e
e
6
A
B
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
-
0.700
0.200
-
17.78
5.08
7
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
L
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated in
N
28
28
JEDEC seating plane gauge GS-3.
Rev. 1 12/00
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
e
6. E and
are measured with the leads constrained to be perpendic-
A
-C-
ular to datum
.
7. e and e are measured at the lead tips with the leads unconstrained.
B
C
e
must be zero or greater.
C
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
16
HI5731
Small Outline Plastic Packages (SOIC)
M28.3 (JEDEC MS-013-AE ISSUE C)
N
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
0.25(0.010)
M
B M
H
AREA
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
MAX
2.65
0.30
0.51
0.32
18.10
7.60
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
0.1043
0.0118
0.0200
0.0125
-
-
1
2
3
L
9
SEATING PLANE
A
0.0091
0.6969
0.2914
-
0.7125 17.70
3
-A-
o
h x 45
D
0.2992
7.40
4
0.05 BSC
1.27 BSC
-
-C-
α
µ
H
h
0.394
0.01
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
0.016
6
0.25(0.010) M
C A M B S
N
α
28
28
7
o
o
o
o
0
8
0
8
-
NOTES:
Rev. 0 12/93
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. How-
ever, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
17
相关型号：
HI5740
3V， Dual 10-Bit， 20/ 40/60 MSPS A/D Converter with Internal Voltage Reference (2 pages) FN4821
ETC
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