HI5767EVAL1_技术文档

HI5767

Data Sheet

February 2000

File Number 4319.4

10-Bit, 20/40/60 MSPS A/D Converter with

Internal Voltage Reference

Features

• Sampling Rate . . . . . . . . . . . . . . . . . . . . . 20/40/60 MSPS

• 8.8 Bits at f = 10MHz, f = 40MSPS

The HI5767 is a monolithic, 10-bit, analog-to-digital

converter fabricated in a CMOS process. It is designed for

high speed applications where wide bandwidth and low

power consumption are essential. Its high sample clock

rate is made possible by a fully differential pipelined

architecture with both an internal sample and hold and

internal band-gap voltage reference.

IN

S

• Low Power at 40MSPS. . . . . . . . . . . . . . . . . . . . . .310mW

• Wide Full Power Input Bandwidth. . . . . . . . . . . . . 250MHz

• On-Chip Sample and Hold

• Internal 2.5V Band-Gap Voltage Reference

• Fully Differential or Single-Ended Analog Input

• Single Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . +5V

• TTL/CMOS Compatible Digital Inputs

The 250MHz Full Power Input Bandwidth and superior high

frequency performance of the HI5767 converter make it an

excellent choice for implementing Digital IF architectures in

communications applications.

• CMOS Compatible Digital Outputs. . . . . . . . . . . 3.0V/5.0V

• Offset Binary or Two’s Complement Output Format

The HI5767 has excellent dynamic performance while

consuming only 310mW power at 40MSPS. Data output

latches are provided which present valid data to the output

bus with a latency of 7 clock cycles.

Applications

• Digital Communication Systems

• QAM Demodulators

The HI5767 is offered in 20MSPS, 40MSPS and 60MSPS

sampling rates.

• Professional Video Digitizing

• Medical Imaging

Ordering Information

TEMP.

SAMPLING

RATE

(MSPS)

• High Speed Data Acquisition

PART

NUMBER

RANGE

PKG.

NO.

o

( C)

PACKAGE

Pinout

HI5767/2CB

HI5767/4CB

HI5767/6CB

HI5767/2CA

HI5767/2IA

0 to 70 28 Ld SOIC

0 to 70 28 Ld SSOP

-40 to 85 28 LD SSOP

0 to 70 28 Ld SSOP

M28.3

20

40

60

20

40

60

HI5767 (SOIC, SSOP)

TOP VIEW

M28.3

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

DV

CC1

D0

D1

D2

D3

D4

DV

M28.15

DGND

3

DV

CC1

4

DGND

HI5767/4CA

HI5767/6CA

HI5767EVAL1

HI5767EVAL2

5

AV

CC

6

AGND

CC2

7

V

CLK

DGND

D5

25

Evaluation Board

REFIN

8

V

REFOUT

9

V

+

IN

10

11

12

13

14

V

-

D6

IN

V

D7

DC

AGND

D8

AV

CC

D9

OE

DFS

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

HI5767

Functional Block Diagram

CLK

CLOCK

V

BIAS

DC

V

-

IN

V

REFOUT

V

+

IN

REFERENCE

V

REFIN

S/H

STAGE 1

DFS

OE

2-BIT

FLASH

2-BIT

DAC

+

∑

-

DV

CC2

X2

D9 (MSB)

D8

D7

D6

DIGITAL DELAY

AND

STAGE 8

D5

DIGITAL ERROR

CORRECTION

D4

D3

2-BIT

FLASH

2-BIT

DAC

D2

D1

+

D0 (LSB)

∑

-

X2

DGND2

STAGE 9

2-BIT

FLASH

AV

AGND DV

CC1

DGND1

CC

2

HI5767

Typical Application Schematic

HI5767

V

(7)

REFIN

REFOUT

(8)

0.1µF

(LSB) (28) D0

(27) D1

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

(26) D2

(25) D3

(24) D4

(20) D5

(19) D6

(18) D7

(17) D8

AGND (12)

AGND (6)

DGND

AGND

BNC

DGND1 (2)

DGND1 (4)

DGND2 (21)

(MSB) (16) D9

10µF AND 0.1µF CAPS

ARE PLACED AS CLOSE

TO PART AS POSSIBLE

V

+

-

(1) DV

CC1

V

+ (9)

(11)

IN

(3) DV

CC1

DC

IN

V

- (10) (23) DV

IN

CC2

+5V

+

0.1µF

10µF

CLOCK

CLK (22)

DFS (15)

OE (14)

(13) AV

CC

(5) AV

+5V

CC

+

0.1µF

10µF

Pin Descriptions

PIN NO.

15

NAME

DESCRIPTION

PIN NO.

NAME

DESCRIPTION

DFS

D9

Data Format Select Input

Data Bit 9 Output (MSB)

Data Bit 8 Output

1

2

DV

Digital Supply (+5.0V)

Digital Ground

CC1

DGND1

DV

16

17

D8

3

Digital Supply (+5.0V)

Digital Ground

CC1

DGND1

AV

18

D7

Data Bit 7 Output

4

19

D6

Data Bit 6 Output

5

Analog Supply (+5.0V)

Analog Ground

CC

AGND

20

D5

Data Bit 5 Output

6

21

DGND2

CLK

Digital Ground

7

V

+2.5V Reference Voltage Input

+2.5V Reference Voltage Output

Positive Analog Input

REFIN

22

Sample Clock Input

Digital Output Supply (+3.0V or +5.0V)

Data Bit 4 Output

8

V

REFOUT

23

DV

CC2

9

V +

IN

24

D4

10

11

12

13

14

V

-

Negative Analog Input

IN

DC

25

D3

D2

D1

D0

Data Bit 3 Output

V

DC Bias Voltage Output

Analog Ground

26

Data Bit 2 Output

AGND

AV

27

Data Bit 1 Output

Analog Supply (+5.0V)

CC

OE

28

Data Bit 0 Output (LSB)

Digital Output Enable Control Input

3

HI5767

o

Absolute Maximum Ratings T = 25 C

Thermal Information

A

o

Supply Voltage, AV

CC

or DV

to AGND or DGND . . . . . . . . . . .6V

Thermal Resistance (Typical, Note 1)

θ_JA( C/W)

CC

DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .

75

100

Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to DV

Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AV

CC

o

CC

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150 C

Maximum Storage Temperature Range . . . . . . . . .-65 C to 150 C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C

o

Operating Conditions

(SOIC - Lead Tips Only)

Temperature Range

o

HI5767/xCx (Typ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 70 C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. θ is measured with the component mounted on an evaluation PC board in free air.

JA

Electrical Speciﬁcations AV = DV

= 5.0V, DV

CC2

= 3.0V; V

= V ; f = 40MSPS at 50% Duty Cycle;

REFOUT S

CC

CC1

REFIN

o

C = 10pF; T = 25 C; Differential Analog Input; Typical Values are Test Results at 25 C,

L

A

Unless Otherwise Speciﬁed

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

ACCURACY

Resolution

10

-

Bits

LSB

Integral Linearity Error, INL

f

= 1MHz Sinewave

±0.75

±0.35

±1.75

±1.0

IN

Differential Linearity Error, DNL

(Guaranteed No Missing Codes)

= 1MHz Sinewave

-

IN

Offset Error, V

OS

f

= DC

-40

-

40

-

LSB

IN

Full Scale Error, FSE

4

IN

DYNAMIC CHARACTERISTICS

Minimum Conversion Rate

No Missing Codes

-

0.5

1

MSPS

Maximum Conversion Rate

HI5767/2

No Missing Codes

20

40

60

-

MSPS

HI5767/4

HI5767/6

Effective Number of Bits, ENOB

HI5767/2

f

= 20MSPS, f = 10MHz

IN

8.7

8.55

8.1

9

-

Bits

S

HI5767/4

= 40MSPS, f = 10MHz

IN

8.8

8.4

HI5767/6

= 60MSPS, f = 10MHz

IN

Signal to Noise and Distortion Ratio, SINAD

RMS Signal

= -------------------------------------------------------------

RMS Noise + Distortion

HI5767/2

f

= 20MSPS, f = 10MHz

IN

-

55.9

54.7

53.8

-

dB

S

HI5767/4

= 40MSPS, f = 10MHz

IN

HI5767/6

= 60MSPS, f = 10MHz

IN

Signal to Noise Ratio, SNR

RMS Signal

= -------------------------------

RMS Noise

HI5767/2

HI5767/4

HI5767/6

f

= 20MSPS, f = 10MHz

IN

-

55.9

55

-

dB

S

= 40MSPS, f = 10MHz

IN

= 60MSPS, f = 10MHz

IN

54

Total Harmonic Distortion, THD

HI5767/2

f

= 20MSPS, f = 10MHz

IN

-

-71

-65

-

dBc

S

HI5767/4

= 40MSPS, f = 10MHz

IN

4

HI5767

Electrical Speciﬁcations AV = DV

= 5.0V, DV

CC2

= 3.0V; V

= V ; f = 40MSPS at 50% Duty Cycle;

REFOUT S

CC

CC1

REFIN

o

C = 10pF; T = 25 C; Differential Analog Input; Typical Values are Test Results at 25 C,

L

A

Unless Otherwise Speciﬁed (Continued)

TEST CONDITIONS

= 60MSPS, f = 10MHz

PARAMETER

MIN

TYP

MAX

UNITS

HI5767/6

f

-

-64.5

-

dBc

S

IN

2nd Harmonic Distortion

HI5767/2

f

= 20MSPS, f = 10MHz

IN

-

-76

-73

-70

-

dBc

S

HI5767/4

HI5767/6

= 40MSPS, f = 10MHz

IN

= 60MSPS, f = 10MHz

IN

3rd Harmonic Distortion

HI5767/2

f

= 20MSPS, f = 10MHz

IN

-

-80

-69

-67

-

dBc

S

HI5767/4

HI5767/6

= 40MSPS, f = 10MHz

IN

= 60MSPS, f = 10MHz

IN

Spurious Free Dynamic Range, SFDR

HI5767/2

f

= 20MSPS, f = 10MHz

IN

-

76

69

67

64

0.5

0.2

1

-

dBc

S

1

HI5767/4

= 40MSPS, f = 10MHz

IN

HI5767/6

= 60MSPS, f = 10MHz

IN

dBc

Intermodulation Distortion, IMD

Differential Gain Error

Differential Phase Error

Transient Response

= 1MHz, f = 1.02MHz

2

dBc

= 17.72MHz, 6 Step, Mod Ramp

%

S

Degree

Cycle

(Note 2)

Over-Voltage Recovery

ANALOG INPUT

0.2V Overdrive (Note 2)

1

Maximum Peak-to-Peak Differential Analog Input

Range (V + - V -)

IN IN

-

±0.5

-

V

Maximum Peak-to-Peak Single-Ended

Analog Input Range

1.0

Analog Input Resistance, R

(Note 3)

-

1

10

-

MΩ

pF

IN

Analog Input Capacitance, C

-

+10

-

IN

Analog Input Bias Current, I + or I -

(Note 3)

-10

-

µA

B

Differential Analog Input Bias Current

= (I + - I -)

±0.5

I

BDIFF

B

Full Power Input Bandwidth, FPBW

-

250

-

MHz

V

Analog Input Common Mode Voltage Range

Differential Mode (Note 2)

0.25

4.75

(V + + V -) / 2

IN IN

INTERNAL REFERENCE VOLTAGE

Reference Voltage Output, V

(Loaded)

-

2.5

1

-

2

-

V

REFOUT

Reference Output Current, I

mA

REFOUT

o

Reference Temperature Coefficient

120

ppm/ C

REFERENCE VOLTAGE INPUT

Reference Voltage Input, V

-

2.5

1

-

V

REFIN

Total Reference Resistance, R

kΩ

mA

REFIN

Reference Input Current, I

REFIN

DC BIAS VOLTAGE

DC Bias Voltage Output, V

Maximum Output Current

-

3.0

-

V

DC

0.2

mA

5

HI5767

Electrical Speciﬁcations AV = DV

= 5.0V, DV

CC2

= 3.0V; V

= V ; f = 40MSPS at 50% Duty Cycle;

REFOUT S

CC

CC1

REFIN

o

C = 10pF; T = 25 C; Differential Analog Input; Typical Values are Test Results at 25 C,

L

A

Unless Otherwise Speciﬁed (Continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNITS

DIGITAL INPUTS

Input Logic High Voltage, V

CLK, DFS, OE

2.0

-

V

IH

Input Logic Low Voltage, V

0.8

V

IL

Input Logic High Current, I

CLK, DFS, OE, V = 5V

IH

-10.0

-

+10.0

-

µA

pF

IH

Input Logic Low Current, I

CLK, DFS, OE, V = 0V

IL

-

IL

Input Capacitance, C

7

IN

DIGITAL OUTPUTS

Output Logic High Voltage, V

I

= 100µA; DV

= 5V

4.0

-

0.8

10

-

V

OH

CC2

Output Logic Low Voltage, V

= 100µA; DV

= 0/5V; DV

OL

CC2

Output Three-State Leakage Current, I

V

= 5V

-10

2.4

-

±1

-

µA

V

OZ

O

CC2

Output Logic High Voltage, V

I

= 100µA; DV

= 3V

OH

CC2

Output Logic Low Voltage, V

= 100µA; DV

= 0/5V; DV

-

0.5

10

-

V

OL

CC2

Output Three-State Leakage Current, I

V

= 3V

CC2

-10

-

±1

10

µA

pF

O

Output Capacitance, C

OUT

TIMING CHARACTERISTICS

Aperture Delay, t

-

5

-

ns

AP

Aperture Jitter, t

AJ

-

ps

RMS

Data Output Hold, t

-

5

-

ns

H

Data Output Delay, t

-

6

-

OD

Data Output Enable Time, t

-

5

-

ns

EN

-

5

-

ns

DIS

Data Latency, t

For a Valid Sample (Note 2)

Data Invalid Time (Note 2)

-

7

20

-

Cycles

ns

LAT

Power-Up Initialization

-

Sample Clock Pulse Width (Low)

Sample Clock Pulse Width (High)

Sample Clock Duty Cycle Variation

f

= 40MSPS

11.3

-

12.5

±5

S

-

ns

-

%

POWER SUPPLY CHARACTERISTICS

Analog Supply Voltage, AV

4.75

5.0

5.25

V

CC

Digital Supply Voltage, DV

4.75

5.25

CC1

Digital Output Supply Voltage, DV

At 3.0V

At 5.0V

2.7

3.0

3.3

V

CC2

4.75

5.0

5.25

V

Supply Current, I

CC

f

= 1MHz and DFS = “0”

-

62

-

mA

mW

LSB

IN

Power Dissipation

310

±0.7

±0.1

IN

Offset Error Sensitivity, ∆V

AV

or DV

= 5V ±5%

OS

CC

Gain Error Sensitivity, ∆FSE

CC

NOTES:

2. Parameter guaranteed by design or characterization and not production tested.

3. With the clock low and DC input.

6

HI5767

Timing Waveforms

ANALOG

INPUT

t

AP

t

AJ

CLOCK

INPUT

1.5V

t

OD

t

H

2.4V

0.5V

DATA

OUTPUT

DATA N

DATA N-1

FIGURE 1. INPUT TO OUTPUT TIMING

Typical Performance Curves

9.5

59

53

47

41

60

55

50

45

40

f

= 1MHz

IN

9.0

8.5

8.0

7.5

7.0

6.5

f

= 5MHz

f

= 1MHz

IN

f

= 5MHz

IN

f

= 10MHz

IN

f = 10MHz

IN

f

= 15MHz

IN

f

= 15MHz

IN

o

T

= 25 C

T

= 25 C

A

10

20

30

40

50

60

70

80

10

20

30

40

50

60

70

80

SAMPLING FREQUENCY (MSPS)

FIGURE 2. EFFECTIVE NUMBER OF BITS (ENOB) AND

SINAD vs SAMPLING FREQUENCY

FIGURE 3. SNR vs SAMPLING FREQUENCY

80

75

80

75

70

65

60

55

50

f

= 1MHz

IN

f = 5MHz

IN

f

= 1MHz

f

= 5MHz

IN

70

65

60

55

50

f

= 15MHz

IN

f

= 10MHz

IN

f

= 10MHz

IN

f

= 15MHz

IN

o

T

= 25 C

T

= 25 C

A

10

20

30

40

50

60

70

80

10

20

30

40

50

60

70

80

SAMPLING FREQUENCY (MSPS)

FIGURE 4. -THD vs SAMPLING FREQUENCY

FIGURE 5. SFDR vs SAMPLING FREQUENCY

7

HI5767

Typical Performance Curves (Continued)

9.5

9.1

9.0

8.9

8.8

8.7

8.6

8.5

8.4

8.3

20MSPS

9.0

20MSPS

8.5

8.0

7.5

7.0

6.5

6.0

5.5

40MSPS

60MSPS

o

T

= 25 C, f = 10MHz

IN

A

DIFFERENTIAL ANALOG INPUT

40MSPS

60MSPS

o

= 25 C, f = 10MHz

T

A

IN

30

35

40

45

50

55

CLK

60

65

70

0.25 0.75 1.25 1.75 2.25 2.75 3.25 3.75 4.25 4.75

DUTY CYCLE (%, t /t

)

V

CM

(V)

H

FIGURE 6. EFFECTIVE NUMBER OF BITS (ENOB) vs

SAMPLE CLOCK DUTY CYCLE

FIGURE 7. EFFECTIVE NUMBER OF BITS (ENOB) vs

ANALOG INPUT COMMON MODE VOLTAGE

80

9.2

20MSPS

I

70

60

50

40

30

20

10

0

CC

9.0

AI

8.8

CC

40MSPS

8.6

o

T

= 25 C, 1MHz < f < 15MHz

IN

A

8.4

DI

CC1

60MSPS

f

= 10MHz, V

= V

REFOUT

8.2

8.0

IN

REFIN

DIFFERENTIAL ANALOG INPUT

DI

CC2

45

10

15

20

25

30

35

40

50

55

60

-40

-20

0

20

40

60

80

o

f

(MSPS)

TEMPERATURE ( C)

S

FIGURE 8. SUPPLY CURRENT vs SAMPLE CLOCK

FREQUENCY

FIGURE 9. EFFECTIVE NUMBER OF BITS (ENOB) vs

TEMPERATURE

2.530

2.525

3.1

V

REFOUT

2.520

3.0

V

DC

2.515

2.510

2.9

-40

-20

0

20

40

60

80

-20

0

20

40

60

80

o

TEMPERATURE ( C)

FIGURE 10. INTERNAL REFERENCE VOLTAGE (V

TEMPERATURE

) vs

FIGURE 11. DC BIAS VOLTAGE (V ) vs TEMPERATURE

DC

REFOUT

8

HI5767

Typical Performance Curves (Continued)

6.5

80

70

60

50

40

30

20

I

CC

6.0

t

OD

AI

CC

5.5

5.0

4.5

60MSPS, f = 10MHz,

IN

AV

= DV

= 5V

CC

DV

CC1

= 3V

CC2

DI

CC1

10

0

DI

CC2

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

o

TEMPERATURE ( C)

FIGURE 12. DATA OUTPUT DELAY (t ) vs TEMPERATURE

OD

FIGURE 13. SUPPLY CURRENT vs TEMPERATURE

0

-10

-20

-30

Φ

C

1

H

o

= 25 C, f = 60MSPS, f = 10MHz

-40

-50

T

A

S

IN

Φ

1

C

S

V

IN+

V

OUT+

+

-

-60

Φ

2

V

+

-

OUT-

-70

IN-

S

Φ

-80

1

Φ

C

Φ

1

H

1

-90

-100

0

100 200 300 400 500 600 700 800 900 1023

FREQUENCY (BIN)

FIGURE 14. 2048 POINT FFT PLOT

FIGURE 15. ANALOG INPUT SAMPLE-AND-HOLD

9

HI5767

TABLE 1. A/D CODE TABLE

OFFSET BINARY OUTPUT CODE

(DFS LOW)

TWO’S COMPLEMENT OUTPUT CODE

(DFS HIGH)

M

S

B

L

S

B

M

S

B

L

S

B

DIFFERENTIAL

INPUT VOLTAGE

CODE CENTER

DESCRIPTION

(V + - V -)

IN IN

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

+Full Scale (+FS) -

1

0.499756V

1

0

1

/

LSB

4

1

+FS - 1 / LSB

4

3

0.498779V

732.422µV

-244.141µV

-0.498291V

-0.499268V

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

+ / LSB

4

1

- / LSB

4

3

-FS + 1 / LSB

4

-Full Scale (-FS) +

3

/

LSB

4

NOTE:

4. The voltages listed above represent the ideal center of each output code shown with V

= +2.5V.

REFIN

The output of each of the eight identical two-bit subconverter

stages is a two-bit digital word containing a supplementary bit

to be used by the digital error correction logic. The output of

each subconverter stage is input to a digital delay line which is

controlled by the internal sampling clock. The function of the

digital delay line is to time align the digital outputs of the eight

identical two-bit subconverter stages with the corresponding

output of the ninth stage flash converter before applying the

eighteen bit result to the digital error correction logic. The

digital error correction logic uses the supplementary bits to

correct any error that may exist before generating the final ten

bit digital data output of the converter.

Detailed Description

Theory of Operation

The HI5767 is a 10-bit fully differential sampling pipeline A/D

converter with digital error correction logic. Figure 16 depicts

the circuit for the front end differential-in-differential-out sample-

and-hold (S/H). The switches are controlled by an internal

sampling clock which is a non-overlapping two phase signal, Φ

1

and Φ , derived from the master sampling clock. During the

2

sampling phase, Φ , the input signal is applied to the sampling

1

capacitors, C . At the same time the holding capacitors, C ,

S

H

are discharged to analog ground. At the falling edge of Φ the

1

input signal is sampled on the bottom plates of the sampling

Because of the pipeline nature of this converter, the digital data

representing an analog input sample is output to the digital data

bus on the 7th cycle of the clock after the analog sample is

taken. This time delay is specified as the data latency. After the

data latency time, the digital data representing each

succeeding analog sample is output during the following clock

cycle. The digital output data is synchronized to the external

sampling clock by a double buffered latching technique. The

digital output data is available in two’s complement or offset

binary format depending on the state of the Data Format Select

(DFS) control input (see Table 1, A/D Code Table).

capacitors. In the next clock phase, Φ , the two bottom plates

2

of the sampling capacitors are connected together and the

holding capacitors are switched to the op-amp output nodes.

The charge then redistributes between C and C completing

S

H

one sample-and-hold cycle. The front end sample-and-hold

output is a fully-differential, sampled-data representation of the

analog input. The circuit not only performs the sample-and-hold

function but will also convert a single-ended input to a fully-

differential output for the converter core. During the sampling

phase, the V pins see only the on-resistance of a switch and

IN

C . The relatively small values of these components result in a

S

typical full power input bandwidth of 250MHz for the converter.

Internal Reference Voltage Output, V

REFOUT

The HI5767 is equipped with an internal reference voltage

generator, therefore, no external reference voltage is required.

As illustrated in the functional block diagram and the timing

diagram in Figure 1, eight identical pipeline subconverter

stages, each containing a two-bit ﬂash converter and a two-

bit multiplying digital-to-analog converter, follow the S/H

circuit with the ninth stage being a two bit ﬂash converter.

Each converter stage in the pipeline will be sampling in one

phase and amplifying in the other clock phase. Each

individual subconverter clock signal is offset by 180 degrees

from the previous stage clock signal resulting in alternate

stages in the pipeline performing the same operation.

V

must be connected to V when using the

REFIN

REFOUT

internal reference voltage.

An internal band-gap reference voltage followed by an

amplifier/buffer generates the precision +2.5V reference

voltage used by the converter. A 4:1 array of substrate

PNPs generates the “delta-V ” and a two-stage op-amp

BE

closes the loop to create an internal +1.25V band-gap

reference voltage. This voltage is then amplified by a

wideband uncompensated operational amplifier connected

10

HI5767

in a gain-of-two configuration. An external, user-supplied,

0.1µF capacitor connected from the V output pin to

the V and -V input signals are 0.5V , with -V being

IN IN P-P IN

180 degrees out of phase with V . The converter will be at

REFOUT

IN

analog ground is used to set the dominant pole and to

positive full scale when the V + input is at V + 0.25V and

IN DC

maintain the stability of the operational amplifier.

the V - input is at V

- 0.25V (V + - V - = +0.5V).

IN DC

IN IN

Conversely, the converter will be at negative full scale when

the V + input is equal to V - 0.25V and V - is at

Reference Voltage Input, V

REFIN

The HI5767 is designed to accept a +2.5V reference voltage

source at the V input pin. Typical operation of the

IN DC IN

V

+ 0.25V (V + - V - = -0.5V).

IN IN

DC

REFIN

converter requires V

The analog input can be DC coupled (Figure 18) as long as

the inputs are within the analog input common mode voltage

range (0.25V ≤ VDC ≤ 4.75V).

to be set at +2.5V. The HI5767 is

yielding a fully

REFIN

connected to V

tested with V

REFIN

REFOUT

differential analog input voltage range of ±0.5V.

V

IN

The user does have the option of supplying an external

+2.5V reference voltage. As a result of the high input

V

+

IN

VDC

impedance presented at the V

input pin, 2.5kΩ

R

REFIN

HI5767

C

typically, the external reference voltage being used is only

required to source 1mA of reference input current. In the

situation where an external reference voltage will be used

an external 0.1µF capacitor must be connected from the

V

DC

-V

IN

-

IN

V

output pin to analog ground in order to maintain

REFOUT

the stability of the internal operational amplifier.

FIGURE 17. DC COUPLED DIFFERENTIAL INPUT

In order to minimize overall converter noise it is

recommended that adequate high frequency decoupling be

The resistors, R, in Figure 18 are not absolutely necessary

but may be used as load setting resistors. A capacitor, C,

provided at the reference voltage input pin, V

.

REFIN

connected from V + to V - will help ﬁlter any high

IN IN

frequency noise on the inputs, also improving performance.

Values around 20pF are sufﬁcient and can be used on AC

coupled inputs as well. Note, however, that the value of

capacitor C chosen must take into account the highest

frequency component of the analog input signal.

Analog Input, Differential Connection

The analog input to the HI5767 is a differential input that can

be conﬁgured in various ways depending on the signal

source and the required level of performance. A fully

differential connection (Figure 17 and Figure 18) will deliver

the best performance from the converter.

Analog Input, Single-Ended Connection

The conﬁguration shown in Figure 19 may be used with a

single ended AC coupled input.

V

+

V

IN

R

HI5767

V

+

V

IN

V

DC

R

HI5767

-

VDC

-V

IN

-

IN

V

IN

FIGURE 16. AC COUPLED DIFFERENTIAL INPUT

FIGURE 18. AC COUPLED SINGLE ENDED INPUT

Since the HI5767 is powered by a single +5V analog supply,

the analog input is limited to be between ground and +5V.

For the differential input connection this implies the analog

input common mode voltage can range from 0.25V to 4.75V.

The performance of the ADC does not change signiﬁcantly

with the value of the analog input common mode voltage.

Again, with V

REFIN

connected to V

, if V is a 1V

IN P-P

REFOUT

sinewave, then V + is a 1.0V

sinewave riding on a positive

IN P-P

voltage equal to VDC. The converter will be at positive full scale

when V + is at VDC + 0.5V (V + - V - = +0.5V) and will be at

IN IN IN

negative full scale when V + is equal to VDC - 0.5V (V + - V -

IN IN IN

= -0.5V). Sufficient headroom must be provided such that the

A DC voltage source, V , equal to 3.2V (typical), is made

DC

input voltage never goes above +5V or below AGND. In this case,

VDC could range between 0.5V and 4.5V without a significant

change in ADC performance. The simplest way to produce VDC

available to the user to help simplify circuit design when using

an AC coupled differential input. This low output impedance

voltage source is not designed to be a reference but makes an

excellent DC bias source and stays well within the analog

input common mode voltage range over temperature.

is to use the DC bias source, V , output of the HI5767.

DC

The single ended analog input can be DC coupled

(Figure 20) as long as the input is within the analog input

common mode voltage range.

For the AC coupled differential input (Figure 17) and with

V

connected to V

, full scale is achieved when

REFIN

REFOUT

11

HI5767

The part should be mounted on a board that provides separate

low impedance connections for the analog and digital supplies

and grounds. For best performance, the supplies to the HI5767

should be driven by clean, linear regulated supplies. The board

should also have good high frequency decoupling capacitors

mounted as close as possible to the converter. If the part is

powered off a single supply, then the analog supply should be

isolated with a ferrite bead from the digital supply.

V

IN

V

+

V

IN

DC

R

HI5767

-

C

V

DC

IN

Refer to the application note “Using Intersil High Speed A/D

Converters” (AN9214) for additional considerations when

using high speed converters.

FIGURE 19. DC COUPLED SINGLE ENDED INPUT

The resistor, R, in Figure 20 is not absolutely necessary but

may be used as a load setting resistor. A capacitor, C,

connected from V + to V - will help ﬁlter any high

IN IN

Static Performance Deﬁnitions

frequency noise on the inputs, also improving performance.

Values around 20pF are sufﬁcient and can be used on AC

coupled inputs as well. Note, however, that the value of

capacitor C chosen must take into account the highest

frequency component of the analog input signal.

Offset Error (V

)

OS

1

The midscale code transition should occur at a level / LSB

above half-scale. Offset is deﬁned as the deviation of the

actual code transition from this point.

4

A single ended source may give better overall system

performance if it is ﬁrst converted to differential before

driving the HI5767.

Full-Scale Error (FSE)

The last code transition should occur for an analog input that

3

is / LSB below Positive Full Scale (+FS) with the offset

4

error removed. Full scale error is deﬁned as the deviation of

Digital Output Control and Clock Requirements

the actual code transition from this point.

The HI5767 provides a standard high-speed interface to

external TTL logic families.

Differential Linearity Error (DNL)

In order to ensure rated performance of the HI5767, the duty

cycle of the clock should be held at 50% ±5%. It must also

have low jitter and operate at standard TTL levels.

DNL is the worst case deviation of a code width from the

ideal value of 1 LSB.

Integral Linearity Error (INL)

Performance of the HI5767 will only be guaranteed at

conversion rates above 1 MSPS. This ensures proper

performance of the internal dynamic circuits. Similarly, when

power is ﬁrst applied to the converter, a maximum of 20

cycles at a sample rate above 1 MSPS will have to be

performed before valid data is available.A Data Format

Select (DFS) pin is provided which will determine the format

of the digital data outputs. When at logic low, the data will be

output in offset binary format. When at logic high, the data

will be output in two’s complement format. Refer to Table 1

for further information.

INL is the worst case deviation of a code center from a best

ﬁt straight line calculated from the measured data.

Power Supply Sensitivity

Each of the power supplies are moved plus and minus 5% and

the shift in the offset and full scale error (in LSBs) is noted.

Dynamic Performance Deﬁnitions

Fast Fourier Transform (FFT) techniques are used to evaluate

the dynamic performance of the HI5767. A low distortion sine

wave is applied to the input, it is coherently sampled, and the

output is stored in RAM. The data is then transformed into the

frequency domain with an FFT and analyzed to evaluate the

dynamic performance of the A/D. The sine wave input to the

part is typically -0.5dB down from full scale for all these tests.

The output enable pin, OE, when pulled high will three-state

the digital outputs to a high impedance state. Set the OE

input to logic low for normal operation.

OE INPUT

DIGITAL DATA OUTPUTS

Active

SNR and SINAD are quoted in dB. The distortion numbers are

quoted in dBc (decibels with respect to carrier) and DO NOT

include any correction factors for normalizing to full scale.

0

1

High Impedance

The Effective Number of Bits (ENOB) is calculated from the

SINAD data by:

Supply and Ground Considerations

The HI5767 has separate analog and digital supply and

ground pins to keep digital noise out of the analog signal

path. The digital data outputs also have a separate supply

ENOB = (SINAD - 1.76 + V

) / 6.02,

CORR

where:

V

= 0.5 dB (Typical).

CORR

pin, DV

, which can be powered from a 3.0V or 5.0V

CC2

supply. This allows the outputs to interface with 3.0V logic if

so desired.

V

adjusts the SINAD, and hence the ENOB, for the

CORR

amount the analog input signal is backed off from full scale.

12

HI5767

Signal To Noise and Distortion Ratio (SINAD)

Video Deﬁnitions

SINAD is the ratio of the measured RMS signal to RMS sum

of all the other spectral components below the Nyquist

frequency, f /2, excluding DC.

S

Differential Gain and Differential Phase are two commonly

found video speciﬁcations for characterizing the distortion of

a chrominance signal as it is offset through the input voltage

range of an ADC.

Signal To Noise Ratio (SNR)

Differential Gain (DG)

SNR is the ratio of the measured RMS signal to RMS noise at

a speciﬁed input and sampling frequency. The noise is the

Differential Gain is the peak difference in chrominance

amplitude (in percent) relative to the reference burst.

RMS sum of all of the spectral components below f /2

S

excluding the fundamental, the ﬁrst ﬁve harmonics and DC.

Differential Phase (DP)

Total Harmonic Distortion (THD)

Differential Phase is the peak difference in chrominance

phase (in degrees) relative to the reference burst.

THD is the ratio of the RMS sum of the first 5 harmonic

components to the RMS value of the fundamental input signal.

Timing Deﬁnitions

Refer to Figure 1 and Figure 2 for these deﬁnitions.

2nd and 3rd Harmonic Distortion

This is the ratio of the RMS value of the applicable harmonic

component to the RMS value of the fundamental input signal.

Aperture Delay (t

)

AP

Aperture delay is the time delay between the external

sample command (the falling edge of the clock) and the time

at which the signal is actually sampled. This delay is due to

internal clock path propagation delays.

Spurious Free Dynamic Range (SFDR)

SFDR is the ratio of the fundamental RMS amplitude to the

RMS amplitude of the next largest spectral component in the

spectrum below f /2.

S

Aperture Jitter (t

)

AJ

Intermodulation Distortion (IMD)

Aperture jitter is the RMS variation in the aperture delay due

to variation of internal clock path delays.

Nonlinearities in the signal path will tend to generate

intermodulation products when two tones, f and f , are

1

2

Data Hold Time (t )

H

Data hold time is the time to where the previous data (N - 1)

is no longer valid.

present at the inputs. The ratio of the measured signal to the

distortion terms is calculated. The terms included in the

calculation are (f +f ), (f -f ), (2f ), (2f ), (2f +f ), (2f -f ),

1

2

1 2

1

2

1

2

1 2

(f +2f ), (f -2f ). The ADC is tested with each tone 6dB

below full scale.

1

2

1

2

Data Output Delay Time (t

)

OD

Data output delay time is the time to where the new data (N)

is valid.

Transient Response

Transient response is measured by providing a full-scale

transition to the analog input of the ADC and measuring the

number of cycles it takes for the output code to settle within

10-bit accuracy.

Data Latency (t

)

LAT

After the analog sample is taken, the digital data representing

an analog input sample is output to the digital data bus on

the 7th cycle of the clock after the analog sample is taken.

This is due to the pipeline nature of the converter where the

analog sample has to ripple through the internal subconverter

stages. This delay is specified as the data latency. After the

data latency time, the digital data representing each

succeeding analog sample is output during the following

clock cycle. The digital data lags the analog input sample by 7

sample clock cycles.

Over-Voltage Recovery

Over-Voltage Recovery is measured by providing a full-scale

transition to the analog input of the ADC which overdrives

the input by 200mV, and measuring the number of cycles it

takes for the output code to settle within 10-bit accuracy.

Full Power Input Bandwidth (FPBW)

Full power input bandwidth is the analog input frequency at

which the amplitude of the digitally reconstructed output has

decreased 3dB below the amplitude of the input sine wave.

The input sine wave has an amplitude which swings from

-FS to +FS. The bandwidth given is measured at the

speciﬁed sampling frequency.

Power-Up Initialization

This time is deﬁned as the maximum number of clock cycles

that are required to initialize the converter at power-up. The

requirement arises from the need to initialize the dynamic

circuits within the converter.

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-

out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site www.intersil.com

13


型号：	HI5767EVAL1
厂家：	Intersil
描述：	10-Bit, 20/40/60 MSPS A/D Converter with Internal Voltage Reference 10位20/40/60 MSPS A / D转换器，内置电压基准转换器
文件：	总13页 (文件大小：136K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HI5767EVAL1 [INTERSIL]

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