HI5812JIB [INTERSIL]
CMOS 20 Microsecond, 12-Bit, Sampling A/D Converter with Internal Track and Hold; CMOS 20微秒， 12位，采样A / D转换器，内置跟踪保持
| 型号： | HI5812JIB |
| 厂家： | 
Intersil |
| 描述： | CMOS 20 Microsecond, 12-Bit, Sampling A/D Converter with Internal Track and Hold |
| 文件： | 总13页 (文件大小：429K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Semiconductor
HI5812
CMOS 20 Microsecond, 12-Bit, Sampling A/D
Converter with Internal Track and Hold
August 1997
Features
Description
• Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . 20µs The HI5812 is a fast, low power, 12-bit, successive
approximation analog-to-digital converter. It can operate from
a single 3V to 6V supply and typically draws just 1.9mA when
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . .50 KSPS
operating at 5V. The HI5812 features a built-in track and hold.
• Built-In Track and Hold
The conversion time is as low as 15µs with a 5V supply.
• Guaranteed No Missing Codes Over Temperature
• Single Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . .+5V
• Maximum Power Consumption. . . . . . . . . . . . . . .25mW
• Internal or External Clock
The twelve data outputs feature full high speed CMOS three-
state bus driver capability, and are latched and held through a
full conversion cycle. The output is user selectable: (i.e.) 12-
bit, 8-bit (MSBs), and/or 4-bit (LSBs). A data ready flag, and
conversion-start inputs complete the digital interface.
An internal clock is provided and is available as an output.
The clock may also be over-driven by an external source.
Applications
• Remote Low Power Data Acquisition Systems
• Digital Audio
Ordering Information
INL (LSB)
(MAX OVER RANGE
TEMP.
• DSP Modems
PART
NUMBER
PKG.
NO.
o
• General Purpose DSP Front End
• µP Controlled Measurement System
• Professional Audio Positioner/Fader
TEMP.)
±1.5
±1.0
±1.5
±1.0
±1.5
±1.0
( C)
PACKAGE
HI5812JIP
HI5812KIP
HI5812JIB
HI5812KIB
HI5812JIJ
HI5812KIJ
-40 to 85 24 Ld PDIP
-40 to 85 24 Ld PDIP
-40 to 85 24 Ld SOIC
-40 to 85 24 Ld SOIC
E24.3
E24.3
M24.3
M24.3
-40 to 85 24 Ld CERDIP F24.3
-40 to 85 24 Ld CERDIP F24.3
Pinout
HI5812
(PDIP, CERDIP, SOIC)
TOP VIEW
DRDY
(LSB) D0
D1
1
2
3
4
5
6
7
8
9
24
V
DD
23 OEL
22 CLK
21 STRT
D2
D3
20 V
19 V
-
REF
REF
D4
+
D5
18
V
IN
D6
17 V
+
AA
D7
16
V
-
AA
D8 10
D9 11
15 OEM
14 D11 (MSB)
13 D10
V
12
SS
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
File Number 3214.4
Copyright © Harris Corporation 1997
6-1789
HI5812
Functional Block Diagram
STRT
V
DD
TO INTERNAL LOGIC
V
SS
V
IN
CLK
CLOCK
CONTROL
+
TIMING
DRDY
32C
OEM
V
+
REF
16C
8C
D11 (MSB)
50Ω
SUBSTRATE
D10
D9
D8
D7
D6
4C
2C
V
+
AA
C
V
-
32C
AA
64C
63
16C
12-BIT
12-BIT EDGE
TRIGGERED
“D” LATCHED
SUCCESSIVE
APPROXIMATION
REGISTER
8C
4C
2C
D5
D4
D3
C
C
P1
D2
D1
V
-
REF
D0 (LSB)
OEL
6-1790
HI5812
Absolute Maximum Ratings
Thermal Information
o
o
Supply Voltage
Thermal Resistance (Typical, Note 1)
CERDIP Package . . . . . . . . . . . . . . . .
PDIP Package . . . . . . . . . . . . . . . . . . .
SOIC Package. . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature
θ
( C/W)
θ
( C/W)
JA
JC
V
to V
. . . . . . . . . . . . . . . . . . . .(V -0.5V) < V < +6.5V
SS DD
60
80
75
12
N/A
N/A
DD
SS
V
+ to V -. . . . . . . . . . . . . . . . . . . . (V -0.5V) to (V +6.5V)
AA AA SS SS
V
+ to V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3V
DD
AA
Analog and Reference Inputs
, V +, V -. . . . . . . . . (V -0.3V) < V
o
V
< (V
+0.3V)
+0.3V)
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 C
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 C
Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C
Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300 C
IN REF SS INA
REF
DD
DD
o
Digital I/O Pins . . . . . . . . . . . . . . (V -0.3V) < VI/O < (V
SS
ο
o
o
Operating Conditions
(SOIC - Lead Tips Only)
Temperature Range
PDIP, SOIC, and CERDIP Packages . . . . . . . . . . . . . -40 C to 85 C
o
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
Electrical Specifications
V
= V + = 5V, V
AA
+ = +4.608V, V = V - = V
- = GND, CLK = External 750kHz,
REF
DD
REF
SS
AA
Unless Otherwise Specified
o
o
o
25 C
-40 C TO 85 C
MIN
TYP
MAX
MIN
MAX
PARAMETER
ACCURACY
TEST CONDITIONS
UNITS
Resolution
12
-
-
-
-
-
-
-
-
-
-
-
12
-
-
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
Integral Linearity Error, INL
(End Point)
J
±1.5
±1.0
±2.0
±1.0
±3.0
±2.5
±2.0
±1.0
±1.5
±1.0
±2.0
±1.0
±3.0
±2.5
±2.0
±1.0
K
J
-
-
Differential Linearity Error, DNL
-
-
K
J
-
-
Gain Error, FSE
(Adjustable to Zero)
-
-
K
J
-
-
Offset Error, V
OS
(Adjustable to Zero)
-
-
K
-
-
Power Supply Rejection, PSRR
Offset Error PSRR
Gain Error PSRR
V
V
V
= 4V
REF
= V + = 5V ±5%
0.1
0.1
±0.5
±0.5
±0.5
±0.5
LSB
LSB
DD
DD
AA
= V + = 5V ±5%
AA
DYNAMIC CHARACTERISTICS
Signal to Noise Ratio, SINAD
RMS Signal
J
f
f
= Internal Clock, f = 1kHz
IN
-
-
-
-
-
68.8
69.2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
dB
dB
S
S
= 750kHz, f = 1kHz
IN
K
J
f
f
= Internal Clock, f = 1kHz
IN
71.0
71.5
dB
dB
RMS Noise + Distortion
S
S
= 750kHz, f = 1kHz
IN
Signal to Noise Ratio, SNR
RMS Signal
f
f
= Internal Clock, f = 1kHz
IN
70.5
71.1
dB
dB
S
S
= 750kHz, f = 1kHz
IN
K
J
f
f
= Internal Clock, f = 1kHz
IN
71.5
72.1
dB
dB
RMS Noise
S
S
= 750kHz, f = 1kHz
IN
Total Harmonic Distortion, THD
f
f
= Internal Clock, f = 1kHz
IN
-73.9
-73.8
dBc
dBc
S
S
= 750kHz, f = 1kHz
IN
K
J
f
f
= Internal Clock, f = 1kHz
IN
-80.3
-79.0
dBc
dBc
S
S
= 750kHz, f = 1kHz
IN
Spurious Free Dynamic Range,
SFDR
f
f
=Internal Clock, f = 1kHz
IN
-
-
-75.4
-75.1
dB
dB
S
S
= 750kHz, f = 1kHz
IN
K
f
f
= Internal Clock, f = 1kHz
IN
-80.9
-79.6
dB
dB
S
S
= 750kHz, f = 1kHz
IN
6-1791
HI5812
Electrical Specifications
V
= V + = 5V, V
AA
+ = +4.608V, V = V - = V
- = GND, CLK = External 750kHz,
REF
DD
REF
SS
AA
Unless Otherwise Specified (Continued)
o
o
o
25 C
-40 C TO 85 C
MIN
TYP
MAX
MIN
MAX
PARAMETER
ANALOG INPUT
TEST CONDITIONS
UNITS
Input Current, Dynamic
Input Current, Static
At V = V
IN
+, 0V
-
-
-
-
-
-
-
±50
±0.4
1
±100
-
-
-
-
-
-
-
±100
µA
µA
MHz
µA
Ω
REF
Conversion Stopped
±10
±10
Input Bandwidth -3dB
Reference Input Current
-
-
-
-
-
-
-
-
-
-
160
420
380
20
Input Series Resistance, R
In Series with Input C
During Sample State
During Hold State
S
SAMPLE
HOLD
SAMPLE
Input Capacitance, C
Input Capacitance, C
pF
pF
DIGITAL INPUTS OEL, OEM, STRT
High-Level Input Voltage, V
2.4
-
-
-
0.8
±10
-
2.4
-
0.8
±10
-
V
V
IH
Low-Level Input Voltage, V
-
-
-
-
-
-
IL
Input Leakage Current, I
IL
Except CLK, V = 0V, 5V
IN
-
µA
pF
Input Capacitance, C
10
IN
DIGITAL OUTPUTS
High-Level Output Voltage, V
I
I
= -400µA
4.6
-
-
-
0.4
±10
-
4.6
-
0.4
±10
-
V
V
OH
SOURCE
Low-Level Output Voltage, V
= 1.6mA
-
-
-
-
-
-
OL
SINK
Three-State Leakage, I
Except DRDY, V
Except DRDY
= 0V, 5V
OUT
-
µA
pF
OZ
Output Capacitance, C
20
OUT
CLOCK
High-Level Output Voltage, V
I
I
= -100µA (Note 2)
4
-
-
-
-
-
4
-
-
V
V
OH
SOURCE
Low-Level Output Voltage, V
Input Current
= 100µA (Note 2)
1
1
OL
SINK
CLK Only, V = 0V, 5V
IN
-
±5
-
±5
mA
TIMING
Conversion Time (t
+ t
)
20
-
-
20
-
µs
CONV
ACQ
(Includes Acquisition Time)
Clock Frequency
Internal Clock, (CLK = Open)
External CLK (Note 2)
External CLK (Note 2)
(Note 2)
200
300
2
400
1.5
-
150
500
1.5
-
kHz
MHz
ns
0.05
0.05
Clock Pulse Width, t
, t
LOW HIGH
100
-
100
Aperture Delay, t APR
-
-
35
105
100
30
60
4
50
150
160
-
-
70
180
195
-
ns
D
Clock to Data Ready Delay, t DRDY
D1
(Note 2)
-
ns
Clock to Data Ready Delay, t DRDY
D2
(Note 2)
-
-
75
100
15
-
ns
Start Removal Time, t STRT
(Note 2)
75
85
10
-
ns
R
Start Setup Time, t STRT
SU
(Note 2)
-
-
ns
Start Pulse Width, t STRT
(Note 2)
-
-
ns
W
Start to Data Ready Delay, t DRDY
D3
(Note 2)
65
60
20
80
105
-
120
-
ns
Clock Delay from Start, t STRT
(Note 2)
-
-
ns
D
Output Enable Delay, t
(Note 2)
-
30
95
-
50
120
ns
EN
Output Disabled Delay, t
(Note 2)
-
-
ns
DIS
POWER SUPPLY CHARACTERISTICS
Supply Current, I
NOTE:
+ I
AA
-
1.9
5
-
8
mA
DD
2. Parameter guaranteed by design or characterization, not production tested.
6-1792
HI5812
Timing Diagrams
5 - 14
4
15
1
3
1
2
2
3
CLK
(EXTERNAL
OR INTERNAL)
t
LOW
t
DRDY
D1
t
HIGH
STRT
DRDY
t
DRDY
D2
DATA N - 1
D0 - D11
DATA N
HOLD N
V
IN
TRACK N
TRACK N + 1
OEL = OEM = V
SS
FIGURE 1. CONTINUOUS CONVERSION MODE
2
2
3
15
2
4
1
5
CLK
(EXTERNAL)
t
STRT
t STRT
SU
R
t
STRT
W
STRT
DRDY
t
DRDY
D3
HOLD
HOLD
TRACK
V
IN
FIGURE 2. SINGLE SHOT MODE EXTERNAL CLOCK
6-1793
HI5812
Timing Diagrams (Continued)
15
1
2
3
4
5
CLK
(INTERNAL)
t STRT
t STRT
R
D
t
STRT
W
STRT
DON’T CARE
t
DRDY
D3
DRDY
HOLD
HOLD
TRACK
V
IN
FIGURE 3. SINGLE SHOT MODE INTERNAL CLOCK
OEL OR OEM
t
1.6mA
t
DIS
EN
90%
50%
50%
D0 - D3 OR D4 - D11
HIGH IMPEDANCE
TO HIGH
+2.1V
TO
OUTPUT
PIN
50pF
HIGH
IMPEDANCE
TO LOW
-1.6mA
10%
FIGURE 4B.
FIGURE 4A.
FIGURE 4. OUTPUT ENABLE/DISABLE TIMING DIAGRAM
1.6mA
+2.1V
50pF
-400µA
FIGURE 5. GENERAL TIMING LOAD CIRCUIT
6-1794
HI5812
Typical Performance Curves
1.0
1.5
V
V
= V + = 5V
AA
A. CLK = INTERNAL
B. CLK = 750kHz
C. CLK = 1MHz
DD
V
= V + = 5V, V
AA
+ = 4.608V
REF
DD
+ = 4.608V
REF
C
0.75
0.5
0.25
0
1
C
B
A
0.5
A
A. CLK = INTERNAL
B. CLK = 750kHz
C. CLK = 1MHz
B
0
-60
-20
0
20
40
60
o
80 100 120 140
-40
-60
-20
0
20
40
60
o
80 100 120 140
-40
TEMPERATURE ( C)
TEMPERATURE ( C)
FIGURE 6. INL vs TEMPERATURE
FIGURE 7. OFFSET VOLTAGE vs TEMPERATURE
1.0
0.75
0.5
2
o
C
V
= V + = 5V, T = 25 C
V
= V + = 5V, V
AA
+ = 4.608V
REF
DD
AA
A
DD
CLK = 750kHz
1.5
1
B
FSE
A
DNL
INL
0.25
0
0.5
0
A. CLK = INTERNAL
B. CLK = 750kHz
C. CLK = 1MHz
V
OS
3
3.2
3.4
3.6
3.8
4
4.2
(V)
4.4
4.6
-60
-20
0
20
40
60
o
80 100 120 140
-40
REFERENCE VOLTAGE, V
REF
TEMPERATURE ( C)
FIGURE 9. ACCURACY vs REFERENCE VOLTAGE
FIGURE 8. DNL vs TEMPERATURE
2
1.5
1
0.5
V
= V + = 5V,
AA
A. CLK = INTERNAL
B. CLK = 750kHz
C. CLK = 1MHz
DD
V
= V + = 5V ±5%
AA
DD
V
+ = 4.608V
REF
CLK = 750kHz
+ = 4.0V
V
REF
0.375
0.25
0.125
0
C
B
0.5
0
PSRR V
OS
A
PSRR FSE
-60
-20
0
20
40
60
o
80 100 120 140
-60
-20
0
20
40
60
o
80 100 120 140
-40
-40
TEMPERATURE ( C)
TEMPERATURE ( C)
FIGURE 10. FULL SCALE ERROR vs TEMPERATURE
FIGURE 11. POWER SUPPLY REJECTION vs TEMPERATURE
6-1795
HI5812
Typical Performance Curves (Continued)
8
INPUT FREQUENCY = 1kHz
SAMPLING RATE = 50kHz
SNR = 72.1dB
SINAD = 71.4dB
EFFECTIVE BITS = 11.5
THD = -79.1dBc
0.0
V
= V + = 5V, V
AA
+ = 4.608V
REF
DD
-10.0
-20.0
-30.0
7
6
5
4
-40.0
-50.0
-60.0
-70.0
-80.0
-90.0
-100.0
PEAK NOISE = -80.9dB
SFDR = -80.9dB
INTERNAL CLOCK
3
2
1
0
-110.0
-120.0
-130.0
-140.0
-60
-20
0
20
40
60
o
80 100 120 140
-40
0
500
1000
FREQUENCY BINS
1500
2000
TEMPERATURE ( C)
FIGURE 12. SUPPLY CURRENT vs TEMPERATURE
FIGURE 13. FFT SPECTRUM
500
12
V
= V + = 5V, V
AA
+ = 4.608V
REF
DD
450
400
350
300
250
200
150
11
10
B
V
= V + = 5V
AA
DD
V
+ = 4.608V
o
REF
9
8
T
= 25 C
A
A. CLK = INTERNAL
B. CLK = 750kHz
C. CLK = 1MHz
C
A
7
-60
-20
0
20
40
60
80 100 120 140
-40
0.1
1
10
100
o
TEMPERATURE ( C)
INPUT FREQUENCY (kHz)
FIGURE 14. INTERNAL CLOCK FREQUENCY vs TEMPERATURE
FIGURE 15. EFFECTIVE BITS vs INPUT FREQUENCY
75
-80
-70
70
65
B
C
V
V
= V + = 5V
AA
DD
V
V
= V + = 5V
AA
DD
+ = 4.608V
o
REF
+ = 4.608V
o
REF
A
T
= 25 C
A
60
T
= 25 C
A
-60
-50
A. CLK =INTERNAL
B. CLK = 750kHz
C. CLK = 1MHz
A. CLK = INTERNAL
B. CLK = 750kHz
C. CLK = 1MHz
B
55
50
C
A
0.1
1
10
100
0.1
1
10
100
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
FIGURE 16. TOTAL HARMONIC DISTORTION vs INPUT
FREQUENCY
FIGURE 17. SIGNAL NOISE RATIO vs INPUT FREQUENCY
6-1796
HI5812
During the first three clock periods of a conversion cycle, the
TABLE 1. PIN DESCRIPTIONS
switchable end of every capacitor is connected to the input
and the comparator is being auto-balanced at the capacitor
common node.
PIN NO. NAME
DESCRIPTION
1
DRDY Output flag signifying new data is available.
Goes high at end of clock period 15. Goes low
when new conversion is started.
During the fourth period, all capacitors are disconnected
from the input; the one representing the MSB (D11) is
connected to the V
+ terminal; and the remaining
REF
-. The capacitor-common node, after the
2
3
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
Bit 0 (Least Significant Bit, LSB).
capacitors to V
REF
charges balance out, will indicate whether the input was
Bit 1.
1
above
period, the comparator output is stored and the MSB
capacitor is either left connected to V + (if the comparator
/
of (V
+ - V
-). At the end of the fourth
2
REF
REF
4
Bit 2.
5
Bit 3.
REF
-. This allows the next
was high) or returned to V
comparison to be at either / or / of (V
REF
6
Bit 4.
3
1
+ - V
-).
4
4
REF
REF
7
Bit 5.
At the end of periods 5 through 14, capacitors representing
D10 through D1 are tested, the result stored, and each
capacitor either left at V
8
Bit 6.
+ or at V
-.
REF
REF
9
Bit 7.
At the end of the 15th period, when the LSB (D0) capacitor is
tested, (D0) and all the previous results are shifted to the
output registers and drivers. The capacitors are reconnected
to the input, the comparator returns to the balance state, and
the data-ready output goes active. The conversion cycle is
now complete.
10
11
12
13
14
15
16
17
18
19
Bit 8.
Bit 9.
V
Digital Ground (0V).
Bit 10.
SS
D10
Analog Input
D11
Bit 11 (Most Significant Bit, MSB).
The analog input pin is a predominately capacitive load that
changes between the track and hold periods of the
conversion cycle. During hold, clock period 4 through 15, the
input loading is leakage and stray capacitance, typically less
than 5µA and 20pF.
OEM Three-State Enable for D4-D11. Active low input.
V
V
-
Analog Ground, (0V).
AA
+
Analog Positive Supply. (+5V) (See text.)
Analog Input.
AA
V
At the start of input tracking, clock period 1, some charge is
dumped back to the input pin. The input source must have
low enough impedance to dissipate the current spike by the
end of the tracking period as shown in Figure 18. The
amount of charge is dependent on supply and input
voltages. The average current is also proportional to clock
frequency.
IN
V
+
Reference Voltage Positive Input, sets 4095
code end of input range.
REF
20
21
22
V
-
Reference Voltage Negative Input, sets 0 code
end of input range.
REF
STRT Start Conversion Input Active Low, recognized
after end of clock period 15.
CLK
CLK Input or Output. Conversion functions are
synchronized to positive going edge. (See
text.)
20mA
I
IN
10mA
0mA
23
24
OEL
Three-State Enable for D0 D3. Active Low Input.
Digital Positive Supply (+5V).
V
DD
CLK
5V
Theory of Operation
0V
5V
HI5812 is a CMOS 12-Bit Analog-to-Digital Converter that
uses capacitor-charge balancing to successively approximate
the analog input. A binarily weighted capacitor network forms
the A/D heart of the device. See the block diagram for the
HI5812.
DRDY
0V
200ns/DIV.
CONDITIONS: V
= V + = 5.0V, V
AA
+ = 4.608V,
REF
DD
= 4.608V, CLK = 750kHz, T = 25 C
o
The capacitor network has a common node which is
connected to a comparator. The second terminal of each
V
IN
A
FIGURE 18. TYPICAL ANALOG INPUT CURRENT
capacitor is individually switchable to the input, V
+ or
REF
V
-.
REF
6-1797
HI5812
As long as these current spikes settle completely by end of The HI5812 is specified with a 4.608V reference, however, it
the signal acquisition period, converter accuracy will be will operate with a reference down to 3V having a slight
preserved. The analog input is tracked for 3 clock cycles. degradation in performance. A typical graph of accuracy vs
With an external clock of 750kHz the track period is 4µs.
reference voltage is presented.
Full Scale and Offset Adjustment
A simplified analog input model is presented in Figure 19.
During tracking, the A/D input (V ) typically appears as a
IN
In many applications the accuracy of the HI5812 would be
sufficient without any adjustments. In applications where
accuracy is of utmost importance full scale and offset errors
may be adjusted to zero.
380pF capacitor being charged through a 420Ω internal
switch resistance. The time constant is 160ns. To charge this
capacitor from an external “zero Ω” source to 0.5 LSB
(1/8192), the charging time must be at least 9 time constants
The V
REF
+ and V - pins reference the two ends of the
REF
or 1.4µs. The maximum source impedance (R
Max)
SOURCE
analog input range and may be used for offset and full scale
for a 4µs acquisition time settling to within 0.5LSB is 750Ω.
adjustments. In a typical system the V - might be
REF
returned to a clean ground, and the offset adjustment done
on an input amplifier. V + would then be adjusted to null
If the clock frequency was slower, or the converter was not
restarted immediately (causing a longer sample time), a
higher source impedance could be tolerated.
REF
out the full scale error. When this is not possible, the V
input can be adjusted to null the offset error, however, V
must be well decoupled.
-
-
REF
REF
V
IN
R
≈ 420Ω
SW
Full scale and offset error can also be adjusted to zero in the
C
≈ 380pF
SAMPLE
R
signal conditioning amplifier driving the analog input (V ).
SOURCE
IN
–t
ACQ
-------------------------------------------------------------
– R
SW
R
=
Control Signal
SOURCE(MAX)
–(N + 1)
C
In[2
]
SAMPLE
The HI5812 may be synchronized from an external source
by using the STRT (Start Conversion) input to initiate conver-
sion, or if STRT is tied low, may be allowed to free run. Each
conversion cycle takes 15 clock periods.
FIGURE 19. ANALOG INPUT MODEL IN TRACK MODE
Reference Input
The input is tracked from clock period 1 through period 3,
then disconnected as the successive approximation takes
The reference input V
impedance source and be well decoupled.
+ should be driven from a low
REF
place. After the start of the next period 1 (specified by t
data), the output is updated.
D
As shown in Figure 20, current spikes are generated on the
reference pin during each bit test of the successive approxi-
mation part of the conversion cycle as the charge-balancing
capacitors are switched between V
periods 5 - 14). These current spikes must settle completely
during each bit test of the conversion to not degrade the
accuracy of the converter. Therefore V
should be well bypassed. Reference input V - is normally
connected directly to the analog ground plane. If V - is
The DRDY (Data Ready) status output goes high (specified
by t DRDY) after the start of clock period 1, and returns
D1
- and V
+ (clock
REF
REF
low (specified by t DRDY) after the start of clock period 2.
D2
The 12 data bits are available in parallel on three-state bus
driver outputs. When low, the OEM input enables the most
significant byte (D4 through D11) while the OEL input
+ and V -
REF
REF
REF
enables the four least significant bits (D0 - D3). t
specify the output enable and disable times.
and t
EN
DIS
REF
biased for nulling the converters offset it must be stable
during the conversion cycle.
If the output data is to be latched externally, either the trailing
edge of data ready or the next falling edge of the clock after
data ready goes high can be used.
20mA
When STRT input is used to initiate conversions, operation is
slightly different depending on whether an internal or
external clock is used.
I
10mA
0mA
REF+
CLK
Figure 3 illustrates operation with an internal clock. If the
STRT signal is removed (at least t STRT) before clock
R
5V
0V
period 1, and is not reapplied during that period, the clock
will shut off after entering period 2. The input will continue to
track and the DRDY output will remain high during this time.
5V
0V
DRDY
A low signal applied to STRT (at least t STRT wide) can
W
now initiate a new conversion. The STRT signal (after a
delay of (t STRT)) causes the clock to restart.
D
2µs/DIV.
Depending on how long the clock was shut off, the low
portion of clock period 2 may be longer than during the
remaining cycles.
CONDITIONS: V
= V + = 5.0V, V
AA REF
= 2.3V, CLK = 750kHz, T = 25 C
A
+ = 4.608V,
o
DD
V
IN
FIGURE 20. TYPICAL REFERENCE INPUT CURRENT
6-1798
HI5812
The input will continue to track until the end of period 3, the Except for V +, which is a substrate connection to V , all
AA
DD
and V
same as when free running.
pins have protection diodes connected to V
.
DD
SS
Input transients above V
the digital supplies.
or below V will get steered to
DD
SS
Figure 2 illustrates the same operation as above but with an
external clock. If STRT is removed (at least t STRT) before
R
clock period 2, a low signal applied to STRT will drop the The V + and V - terminals supply the charge-balancing
AA AA
DRDY flag as before, and with the first positive-going clock comparator only. Because the comparator is autobalanced
edge that meets the (t STRT) setup time, the converter will between conversions, it has good low-frequency supply
SU
continue with clock period 3.
rejection. It does not reject well at high frequencies however;
V
- should be returned to a clean analog ground and V
+
AA AA
Clock
should be RC decoupled from the digital supply as shown in
Figure 22.
The HI5812 can operate either from its internal clock or from
one externally supplied. The CLK pin functions either as the
clock output or input. All converter functions are synchro-
nized with the rising edge of the clock signal.
There is approximately 50Ω of substrate impedance
between V
part of a low-pass RC filter to attenuate switching supply
and V +. This can be used, for example, as
DD
AA
noise. A 10µF capacitor from V + to ground would
attenuate 30kHz noise by approximately 40dB. Note that
Figure 21 shows the configuration of the internal clock. The
clock output drive is low power: if used as an output, it
should not have more than 1 CMOS gate load applied, and
stray wiring capacitance should be kept to a minimum.
AA
back-to-back diodes should be placed from V
to V + to
DD
AA
handle supply to capacitor turn-on or turn-off current spikes.
Dynamic Performance
The internal clock will shut down if the A/D is not restarted
after a conversion. The clock could also be shut down with
an open collector driver applied to the CLK pin. This should
only be done during the sample portion (the first three clock
periods) of a conversion cycle, and might be useful for using
the device as a digital sample and hold.
Fast Fourier Transform (FFT) techniques are used to
evaluate the dynamic performance of the A/D. A low distor-
tion sine wave is applied to the input of the A/D converter.
The input is sampled by the A/D and its output stored in
RAM. The data is than transformed into the frequency
domain with a 4096 point FFT and analyzed to evaluate the
converters dynamic performance such as SNR and THD.
See typical performance characteristics.
If an external clock is supplied to the CLK pin, it must have
sufficient drive to overcome the internal clock source. The
external clock can be shut off, but again, only during the
sample portion of a conversion cycle. At other times, it must
be above the minium frequency shown in the specifications.
Signal-To-Noise Ratio
In the above two cases, a further restriction applies in that The signal to noise ratio (SNR) is the measured RMS signal
the clock should not be shut off during the third sample to RMS sum of noise at a specified input and sampling
period for more than 1ms. This might cause an internal frequency. The noise is the RMS sum of all except the
charge-pump voltage to decay.
fundamental and the first five harmonic signals. The SNR is
dependent on the number of quantization levels used in the
converter. The theoretical SNR for an N-bit converter with no
differential or integral linearity error is: SNR = (6.02N + 1.76)
dB. For an ideal 12-bit converter the SNR is 74dB.
Differential and integral linearity errors will degrade SNR.
If the internal or external clock was shut off during the
conversion time (clock cycles 4 through 15) of the A/D, the
output might be invalid due to balancing capacitor droop.
An external clock must also meet the minimum t
and
LOW
times shown in the specifications. A violation may
t
HIGH
cause an internal miscount and invalidate the results.
Sinewave Signal Power
SNR = 10 Log
Total Noise Power
Signal-To-Noise + Distortion Ratio
INTERNAL
ENABLE
SINAD is the measured RMS signal to RMS sum of noise
plus harmonic power and is expressed by the following:
CLOCK
CLK
OPTIONAL
EXTERNAL
CLOCK
Sinewave Signal Power
SINAD = 10 Log
100kΩ
18pF
Noise + Harmonic Power (2nd - 6th)
Effective Number of Bits
FIGURE 21. INTERNAL CLOCK CIRCUITRY
The effective number of bits (ENOB) is derived from the
SINAD data;
Power Supplies and Grounding
and V are the digital supply pins: they power all
V
SINAD - 1.76
DD
SS
internal logic and the output drivers. Because the output
drivers can cause fast current spikes in the V and V
ENOB =
6.02
DD
SS
lines, V
should have a low impedance path to digital
SS
ground and V
should be well bypassed.
DD
6-1799
HI5812
Total Harmonic Distortion
Spurious-Free Dynamic Range
The total harmonic distortion (THD) is the ratio of the RMS The spurious-free dynamic range (SFDR) is the ratio of the
sum of the second through sixth harmonic components to fundamental RMS amplitude to the RMS amplitude of the
the fundamental RMS signal for a specified input and next largest spur or spectral component. If the harmonics
sampling frequency.
are buried in the noise floor it is the largest peak.
Total Harmonic Power (2nd - 6th Harmonic)
Sinewave Signal Power
SFDR = 10 Log
THD = 10 Log
Sinewave Signal Power
Highest Spurious Signal Power
TABLE 2. CODE TABLE
BINARY OUTPUT CODE
INPUT VOLTAGE†
= 4.608V
V
MSB
LSB
REF+
CODE
DESCRIPTION
V
= 0.0V
DECIMAL
COUNT
REF-
(V)
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Full Scale (FS)
4.6069
4.6058
3.4560
2.3040
1.1520
0.001125
0
4095
4094
3072
2048
1024
1
1
1
1
1
0
0
0
1
1
1
0
1
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
1
0
FS - 1 LSB
3
/
/
/
FS
FS
FS
4
2
4
1
1
1 LSB
Zero
0
†The voltages listed above represent the ideal lower transition of each output code shown as a function of the reference voltage.
+5V
0.1µF
4.7µF
10µF
0.1µF
0.1µF
0.01µF
V
+
V
DD
AA
D11
.
.
.
OUTPUT
DATA
D0
V
REF
V
REF+
4.7µF
0.001µF
DRDY
OEM
OEL
ANALOG
INPUT
V
V
IN
STRT
CLK
750kHz CLOCK
V
V
SS
REF-
AA-
FIGURE 22. GROUND AND SUPPLY DECOUPLING
6-1800
HI5812
Die Characteristics
DIE DIMENSIONS:
3200µm x 3940µm
METALLIZATION:
PASSIVATION:
Type: PSG
Thickness: 13kÅ ±2.5kÅ
WORST CASE CURRENT DENSITY:
Type: AlSi
Thickness: 11kÅ ±1kÅ
5
2
1.84 x 10 A/cm
Metallization Mask Layout
HI5812
D0
(LSB)
D1
DRDY
V
OEL
DD
CLK
D2
D3
STRT
V
-
REF
D4
D5
D6
V
V
+
REF
D7
D8
IN
V
+
-
AA
V
AA
D9
V
D10
D11
(MSB)
OEM
SS
6-1801
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