HIP0060AB [INTERSIL]
1.5A, 50V Quad Low Side Power Driver with Serial Bus Control and Fault Protection; 1.5A ， 50V四路低端电源驱动器，带有串行总线控制和故障保护
| 型号： | HIP0060AB |
| 厂家： | 
Intersil |
| 描述： | 1.5A, 50V Quad Low Side Power Driver with Serial Bus Control and Fault Protection |
| 文件： | 总7页 (文件大小：53K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIP0060
1.5A, 50V Quad Low Side Power Driver
with Serial Bus Control and Fault Protection
July 1997
Features
Description
• Quad NDMOS Output Drivers in a High Voltage Power
BiMOS Process
The HIP0060 is a 5V logic controlled Quad Low Side Power
Driver. The outputs are individually protected for over-current
(OC), over-temperature (OT) and over-voltage (OV). If an OC
• Over-Stress Protection - Each Output
short circuit in the output load is sensed (I ) in one output
S
- Over-Current Limiting . . . . . . . . . . . . . . . . . .1.5A Min
power driver, that output current will be independently limited
while the other outputs remain in operation. Over-current is
limited by direct gate feedback. Over-voltage protection is pro-
vided by a drain-to-gate zener diode that clamps inductive
switching pulses.
- Internal Zener Drain-to-Gate Over-Voltage Clamp
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50V Typ
- Thermal Shutdown Protection
- Open-Load Detection
The output drivers are individually controlled through a Gate
Control Latch. Temperature is sensed at each output. If a ther-
mal fault exists, a status flag is set and the output is latched
off. Open-load (OL) and over-temperature (OT) faults sets a
status flag bit as diagnostic output to the SPI bus. For all fault
bits (8), an ORed one-shot interrupt signal is output to the INT
pin. An RST reset clears the fault flags and disables all out-
puts while active. The Serial Peripheral Interface (SPI) bus
pins are the Serial Input (SI), Serial Output (SO), Serial Data
Clock (SCK) and the Chip Select (CS).
• Low Quiescent Current . . . . . . . . . . . . . . . . 10mA Max
• Serial Diagnostic Link with SPI Bus
• Diagnostic Interrupt Fault Flag
• 5V CMOS Logic Input Control
• Common Reset for Fault Bits and Output Drivers
• Ambient Operating
Temperature Range. . . . . . . . . . . . . . . . -40 C to 125 C
o
o
The HIP0060 is fabricated in a Power BiMOS IC process, and
is intended for use in automotive and other applications having
a wide range of temperature and electrical stress conditions. It
is particularly suited for driving lamps, relays, and solenoids in
applications where low operating power, high breakdown volt-
age, and higher output current at high temperatures is required.
Applications
• Automotive and Industrial Systems
• Fuel Injection Drivers
• Solenoids, Relays and Lamp Drivers
• Logic and µP Controlled Drivers
• Robotic Controls
Ordering Information
TEMP.
PKG.
NO.
o
PART NUMBER RANGE ( C)
PACKAGE
24 Ld SOIC
HIP0060AB
-40 to 125
M24.3
Pinout
Block Diagram
HIP0060 (SOIC)
TOP VIEW
CHANNEL A
(1 OF 4)
OVER TEMP.
DETECTOR
V
OPEN LOAD
DETECTOR
DD
+5V
OUTA
GATE
CONTROL
LATCH
1
2
24
23
22
21
20
GND
V
DD
INT
INA
RST
IND
INA
3
OUTA
GND
GND
GND
GND
OUTB
INB
4
OUTD
GND
+
OVER
CURRENT
LIMIT
O.T.
BIT
O.L.
BIT
I
S
5
6
19 GND
18 GND
RST
7
SCK
SI
8
17
16
15
14
13
GND
OUTC
INC
INT
8-BIT SPI
(SERIAL
DIAG.
8 ORed O.T./O.L.
FAULT INPUTS,
ONE-SHOT
9
SO
CS
2
10
11
REG)
2
MULTI OUTPUT
SO
SI
2
2
2
2
SCK
CS 12
TO
B, C, D
FROM B, C, D
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 4045
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
HIP0060
Absolute Maximum Ratings
Thermal Information
o
Max Output Voltage, V
OUT
(Note 2). . . . . . . . . . . . . . . . . . . . . V
OC
Thermal Resistance (Typical, Notes 1, 4)
θ
( C/W)
JA
Max Output Load Current, I
(Per Output, Note 3) . . . . . . . . I
LOAD
Logic Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V
CL
SOIC - PC Board Mount, Min. Copper . . . . . . . . . .
SOIC - PC Board Mount, 2 sq. in. Copper . . . . . . . .
Maximum Storage Temperature Range -55 C to 150 C
60
35
o
o
Logic Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
DD
o
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C
(SOIC - Lead Tips Only)
Operating Conditions
o
o
Ambient Temperature Range . . . . . . . . . . . . . . . . . -40 C to 125 C
Junction Temperature Range . . . . . . . . . . . . . . . . -40 C to 150 C
o
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
2. The MOSFET Output Drain is internally clamped with a Drain-to-Gate zener diode that turns on the MOSFET; holding the Drain at the
Output Clamp voltage V
.
OC
3. The output drive is protected by an internal current limit. The I over-current limiting threshold parameter specification defines the max-
CL
imum current. The maximum current with all outputs ON may be further limited by dissipation.
4. Device dissipation is based on thermal resistance capability of the package in a normal operating environment. The junction to ambient
o
thermal resistance of 60 C/W is defined here as a PC Board mounted device with minimal copper. With approximately 2 square inches
o
of copper area as a heat sink, it is practical to achieve 35 C/W thermal resistance. Further reduction in the thermal resistance can be
achieved with additional PC Board Copper ground area or an external heat sink structure next to the ground leads at the center of the
package.
o
o
Electrical Specifications
V
= 4.5V to 5.5V, V = 0V, T = -40 C to 125 C; Unless Otherwise Specified
DD
SS
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
OUTPUTS DRIVERS (DR0 TO DR7)
Output Channel Resistance
Over-Current Limiting Threshold
Output Clamping Voltage
r
I
= 0.5A
OUT
-
1.5
40
-
-
0.8
3.5
60
-
Ω
A
DSON
I
-
CL
V
50
85
V
OC
OC
o
Output Clamping Energy
E
1ms Single Pulse Width, T = 25 C,
A
mJ
(Refer to Figure 3 for SOA Limits).
Output OFF Leakage Current
Open-Load Fault Threshold
Output Rise Time
I
V
V
= 14.5V
-
4
1
1
-
-
-
-
-
-
-
180
200
12
µA
kΩ
µs
µs
µs
µs
LK
OUT
OUT
R
= 14.5V, Output Off
OLD
t
R
R
R
R
= 30Ω, V
= 30Ω, V
= 30Ω, V
= 30Ω, V
= 14.5V
= 14.5V
= 14.5V
= 14.5V
R
L
L
L
L
OUT
OUT
OUT
OUT
Output Fall Time
t
12
F
Turn-On Delay
t
12
ON
Turn-Off Delay
t
-
12
OFF
POWER SUPPLY
Power On Reset Threshold
Logic Supply Current
V
3.2
-
-
-
4.4
10
V
DD(POR)
V
I
All Outputs ON or OFF
mA
DD
DD
LOGIC INPUTS (INx, SI, SCK, RST, CS)
High Level Input Voltage
Low Level Input Voltage
Input Hysteresis
V
0.7xV
-
-
-
-
-
-
-
-
-
V
V
IH
DD
V
0.2xV
-
IL
DD
V
0.8
-
V
ILHYS
High Output Voltage, SO, INT
Low Output Voltage, SO
Input Pull-Down Current, INx
Reset Input Pull-Up Current, RST
V
Current Sink = 1.6mA
0.4
-
V
OL
V
Current Source = -0.8mA
V
-0.8
V
OH
DD
I
75
20
250
120
µA
µA
INPD
I
RPU
2
HIP0060
o
o
Electrical Specifications
PARAMETER
V
= 4.5V to 5.5V, V = 0V, T = -40 C to 125 C; Unless Otherwise Specified (Continued)
DD
SS
A
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIAGNOSTIC
Pulse Width, INT
t
3
-
-
-
25
16
µs
µs
INT
Fault Response Time
t
FAULT
OVER-TEMPERATURE PROTECTION
Over-Temperature Shutdown
SERIAL PERIPHERAL INTERFACE TIMING (Capacitance Each Pin, C = 200pF)
o
T
160
-
-
C
SD
L
SCK Period
t
500
200
-
-
-
-
ns
ns
CYC
SCK Clock High/Low Time
t
WSCKH,
t
WSCKL
SCK Rise/Fall Time
t
t
,
-
-
-
30
-
ns
ns
rSCK
fSCK
Enable Lead/Lag Time
t
,
250
LEAD
t
LAG
Output Data Valid Time
Data Setup Time
Disable Time
t
-
-
-
-
-
-
170
30
ns
ns
ns
V
t
SU
t
250
DIS
OL (Open-Load) Fault Mode
Description of Diagnostics
An open-load fault mode sequence consists of setting a sta-
tus flag (the OL Bit) when an output open load condition is
detected. If the output impedance is greater than a preset
threshold, as detected when the input is off; the status bit is
set. The OL Bit is reset on the next falling edge of the IN
input signal. The off-on detection sequence will repeat as
long as the output impedance is higher than the detection
threshold, as detected in the off state.
OC (Over-Current) Fault Mode
In a short circuit or over-current fault condition when an out-
put is switched on, the output current is limited to the I
CL
maximum as defined in the Electrical Specifications. An OC
fault condition does not shutdown the output. The current is
sensed and feedback is directed to the gate of the MOS Out-
put Driver. The gate voltage is reduced to maintained the
specified level of current limiting. In this mode, the drain volt-
age will increase and cause increased dissipation.
Diagnostic action for an OL fault mode differs from the OT
fault mode by not forcing an output shutdown through the
Gate Controlled Latch. Also, because the OL fault is
detected in the off state, the status flag is reset on the falling
edge of the input instead of the rising edge. The OL output
information to the Serial Diagnostic Register and the INT pin
is the same as the OT fault mode action.
OT (Over-Temperature) Fault Mode
Under a high dissipation over-temperature fault condition,
the output temperature is detected and compared to a preset
threshold level. When the OT threshold is exceeded, thermal
shutdown for that output occurs. The Gate Control Latch
drive to the output is switched off and a status flag (the OT
Bit) for the fault is set. The output shutdown action is inde-
pendent of the IN input state. However, the Gate Control
Latch and OL Bit will be reset on the next rising edge of the IN
input and, if the fault still exists, the shutdown action will repeat.
ORed Fault Bits
It is important to note that the trigger input to the one-shot is
locked-out for the tINT duration and any fault that may have
occurred in the tINT window will not be displayed at the INT
output. However, all 8 fault bits may still be read as data from
the SO output when clock by the SCK input. The INT fault
output is provided as an interrupt signal to flag the immedi-
ate occurrence of a fault and take appropriate action as
defined by the microcontroller to the SPI bus and the users
programming. The INT fault output may be ORed with other
ICs to provide a system microcontroller interrupt to indicate
the presence of a fault.
Diagnostic action for an OT fault includes feedback of the
fault status to the Serial Diagnostic Register for a SPI bus
data output. Also, as shown in the Block Diagram, the OT
fault status bit information is ORed into a one-shot that
drives an open drain to provide an INT interrupt signal out-
put. The INT output has a specified timing from the one-shot
multi and is defined in the Electrical Specifications as tINT
.
3
HIP0060
Serial Diagnostic Link
HIP0060 devices may be linked in cascade for the purposes
of SPI control. Serial data is clocked in and out of each
HIP0060 and then back to the host microcontroller. All linked
devices have a common control sequence. When CS goes
low, fault data is shifted to the Serial Diagnostic Register.
SCK must be low when CS goes low. Also, when CS goes
low, SO changes from a three-state to a low state and
remains low until SCK goes high. Serial data is transferred
by SCK. After the serial data is transferred, SCK must
remain low as CS goes high. The serial data transfer must
be a continuous sequence while CS is low.
A serial diagnostic link via the SPI bus provides the means
to clock fault data in and out of the fault register to the micro-
controller. When the microcontroller receives an INT inter-
rupt signal, data is clocked from the Serial Diagnostic
Register to determine what fault bit has been set. Appropri-
ate action for the fault may then be taken, as defined by the
programming of the microcontroller.
Serial Diagnostic Register
Fault bits consist of one OT bit and one OL bit for each
switching channel (A, B, C and D). Data is transferred out
of SO MSB first on the rising edge of SCK after CS goes
low. Data is shifted into the input shift register on the falling
edge of SCK. The defined order of the DO0 to DO7 fault
bits is as follows:
Serial Peripheral Interface
The Serial Peripheral Interface (SPI) bus is system con-
trolled by a host micro. The SPI bus controls the Serial Diag-
nostic Link with the CS (Chip Select), SCK, SI, SO and RST
(Reset) lines. Figures 4 and 5 define the timing and protocol
for the bus.
BIT
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
NAME
OTA
OTB
OTC
OTD
OLA
OLB
OLC
OLD
CONDITION REQUIRED TO SET BIT
Reset Operation
OT in Output Driver A, T ≥ T
J
LIM
LIM
LIM
LIM
The RST input is an active low reset input. When RST is low,
the internal diagnostic flags are cleared but not the shift reg-
ister. When RST is low, all outputs and output switches are
disabled. To clear the shift register, CS is switched from high
to low during or after a reset while there are no active faults,
jamming data from the cleared fault flags into the shift regis-
tor. The RST input has an internal pull-up to sustain a logic
high when floating.
OT in Output Driver B, T ≥ T
J
OT in Output Driver C, T ≥ T
J
OT in Output Driver D, T ≥ T
J
OL in Output Driver A, OFF Load > R
OL in Output Driver B, OFF Load > R
OL in Output Driver C, OFF Load > R
OL in Output Driver D, OFF Load > R
OLD
OLD
OLD
OLD
The V
DD
POR function. When the V
input is the power supply to the 5V logic and the
is less than the V
DD
DD(POR)
threshold, the output drivers are shutoff. To insure that the
diagnostic link shift register is correct after V is less than
DD
, a manual reset must be executed.
V
DD(POR)
V
DD
+5V
SOLENOID
RELAY
4.7kΩ
INT
OUTA
V
BATT
RST
INA
INB
INC
IND
OUTB
OUTC
HIP0060
LAMP
OUTD
M
V
BATT
MOTOR
FIGURE 1. TYPICAL HIP0060 APPLICATION AS A LOW SIDE SWITCH FOR INDUCTIVE LOADS, LAMPS AND SMALL LINEAR
MOTORS OR STEPPER MOTORS
4
HIP0060
V
+5V
DD
+14.5V
4.7kΩ
RST
4.7kΩ
30Ω
30Ω
30Ω
30Ω
OUTA
OUTB
OUTC
INA
INB
INC
IND
INT
50Ω
5V, 100µs
HIP0060
(TIMING TEST
CIRCUIT)
2% DUTY CYCLE
FUNCTION GEN.
OUTD
GND
5V
0V
3V
V
IN
1V
t
t
OFF
ON
t
t
f
r
14.5V
0V
90%
90%
V
OUT
10%
10%
FIGURE 2. INPUT TO OUTPUT SWITCHING TIME DIAGRAM FOR EACH SWITCHING CHANNEL. THE CONDITIONS SHOWN
REFER TO THE TIMING TEST CIRCUIT
10000
1000
100
SAFE OPERATING AREA
BELOW LINE
10
0.1
1
10
100
TIME (ms)
o
FIGURE 3. MAXIMUM SINGLE PULSE ENERGY SAFE OPERATING AREA FOR EACH CLAMPED OUTPUT DRIVER, T = 25 C
A
5
HIP0060
Timing Diagrams
CS
SCK
(CPOL = 0, CPHA = 1)
MSB
6
5
4
3
2
1
LSB
INTERNAL STROBE FOR DATA CAPTURE
FIGURE 4. DATA AND CLOCK TIMING DIAGRAM
CS
t
t
t
t
SCK
r
SCK
t
f
LAG
LEAD
CYC
SCK
t
WSCKH
t
WSCKL
t
SU
DI7
DI6
DI1
D10
SI
t
DIS
SO
DO7
DO6
DO1
DO0
(THREE-STATE)
t
V
FIGURE 5. BYTE TIMING DIAGRAM WITH ASYNCHRONOUS RESET. REFER TO THE ELECTRICAL SPECIFICATION FOR THE
HIGH AND LOW INPUT AND OUTPUT THRESHOLD LEVELS SHOWN FOR TIMING REFERENCE
6
HIP0060
Small Outline Plastic Packages (SOIC)
M24.3 (JEDEC MS-013-AD ISSUE C)
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
N
INDEX
AREA
M
M
B
0.25(0.010)
H
INCHES MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
MAX
2.65
0.30
0.51
0.32
15.60
7.60
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
0.1043
0.0118
0.020
-
1
2
3
-
L
9
SEATING PLANE
A
0.0091
0.5985
0.2914
0.0125
-
-A-
o
0.6141 15.20
3
D
h x 45
0.2992
7.40
4
-C-
0.05 BSC
1.27 BSC
-
α
H
h
0.394
0.010
0.016
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
M
M
S
B
0.25(0.010)
C
A
N
α
24
24
7
o
o
o
o
NOTES:
0
8
0
8
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
7
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