HIP2121FRTBZ_技术文档

100V, 2A Peak, High Frequency Half-Bridge Drivers with

Adjustable Dead Time Control and PWM Input

HIP2120, HIP2121

Features

• 9 Ld TDFN “B” Package Compliant with 100V Conductor

Spacing Guidelines per IPC-2221

The HIP2120 and HIP2121 are 100V, high frequency, half-bridge

MOSFET driver ICs. They are based on the popular ISL2100A and

ISL2101A half-bridge drivers.

• Break-Before-Make Dead-Time Prevents Shoot-through and is

adjustable up to 220ns

These drivers have a programmable dead-time to insure

break-before-make operation between the high-side and low-side

drivers. The dead-time is adjustable up to 250ns.

• Bootstrap Supply Max Voltage to 114VDC

• Wide Supply Voltage Range (8V to 14V)

• Supply Undervoltage Protection

A single PWM logic input controls both bridge outputs (HO, LO). An

enable pin (EN), when low, drives both outputs to a low state. All

• CMOS Compatible Input Thresholds with Hysteresis (HIP2120)

• 1.6Ω/1Ω Typical Output Pull-up/Pull-down Resistance

• On-Chip 1Ω Bootstrap Diode

logic inputs are V tolerant and the HIP2120 has CMOS inputs

DD

with hysteresis for superior operation in noisy environments.

The HIP2120 has hysteretic inputs with thresholds that are

proportional to V . The HIP2121 has 3.3V logic/TTL compatible

inputs.

DD

Applications

• Telecom Half-Bridge DC/DC Converters

• UPS and Inverters

Two package options are provided. The 10 Ld 4x4 DFN package has

standard pinouts. The 9 Ld 4x4 DFN package omits pin 2 to comply

with 100V conductor spacing per IPC-2221.

• Motor Drives

• Class-D Amplifiers

• Forward Converter with Active Clamp

Related Literature

• FN7670 “HIP2122, HIP2123 100V, 2A Peak, High Frequency

Half-Bridge Driver with Delay Timers”

200

160

140

120

100

100V max

HIP2120/21

HALF BRIDGE

VDD

PWM

EN

HB

SECONDARY

CIRCUITS

HO

HS

80

60

PWM

CONTROLLER

RDT

VSS

FEEDBACK

WITH

ISOLATION

LO

40

EPAD

20

8

16

24

DT

32 40 48 56 64 80

(kΩ)

R

FIGURE 1. TYPICAL APPLICATION

FIGURE 2. DEAD-TIME vs TIMING RESISTOR

December 23, 2011

FN7668.0

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

1

HIP2120, HIP2121

Block Diagram

VDD

HB

HO

HS

HIP2120,

HIP2121

UNDER

LEVEL

VOLTAGE

SHIFT

HIP2121

HIP2120/21

PWM

RDT

DELAY

UNDER

VOLTAGE

Optional

inversion

for future

part

LO

numbers

DELAY

VSS

EN

EPAD IS

ELECTRICALLY

ISOLATED

HIP2121

HIP2120/21

EPAD

Pin Configurations

HIP2120, HIP2121

(10 LD 4X4 TDFN)

TOP VIEW

(9 LD 4X4 TDFN)

TOP VIEW

VDD

1

10 LO

VDD

HB

HO

HS

1

2

3

4

5

10 LO

9

8

7

6

VSS

PWM

9

8

7

6

VSS

EPAD

HB

HO

HS

3

4

5

PWM

EN

RDT

NC

RDT

FN7668.0

December 23, 2011

2

HIP2120, HIP2121

Pin Descriptions

10 LD

9 LD

SYMBOL

VDD

DESCRIPTION

1

Positive supply voltage for lower gate driver. Decouple this pin with a ceramic capacitor to

VSS.

2

3

HB

High-side bootstrap supply voltage referenced to HS. Connect the positive side of the

bootstrap capacitor to this pin. Bootstrap diode is on-chip.

3

4

5

HO

HS

High-side output. Connect to gate of high-side power MOSFET.

High-side source connection. Connect to source of high-side power MOSFET. Connect

negative side of bootstrap capacitor to this pin.

8

7

8

7

PWM

EN

PWM input. For PWM = 1, HO = 1 and LO = 0. For PWM = 0, HO = 0 and LO = 1.

Output enable, when low, HO = LO = 0

9

VSS

LO

Negative voltage supply, which will generally be ground.

Low-side output. Connect to gate of low-side power MOSFET.

No Connect. This pin is isolated from all other pins.

10

5

10

-

NC

6

RDT

A resistor connected between this pin and VSS adds additional delay time to the falling and

rising edges of the PWM input.

-

EPAD

Exposed pad. Connect to ground or float. The EPAD is electrically isolated from all other

pins.

Ordering Information

PART NUMBER

PART

TEMP. RANGE

(°C)

PACKAGE

(Pb-Free)

PKG.

DWG. #

(Notes 1, 2, 4)

MARKING

HIP 2120AZ

HIP 2121AZ

HIP 2120BZ

HIP 2121BZ

INPUT

CMOS

HIP2120FRTAZ

-40 +125

10 Ld 4x4 TDFN

L10.4x4

HIP2121FRTAZ

3.3V/TTL

CMOS

10 Ld 4x4 TDFN

9 Ld 4x4 TDFN

L10.4x4

L9.4x4

HIP2120FRTBZ (Note 3)

HIP2121FRTBZ (Note 3)

NOTES:

3.3V/TTL

1. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. “B” package option has alternate pin assignments for compliance with 100V Conductor Spacing Guidelines per IPC-2221. Note that Pin 2 is omitted

for additional spacing.

4. For Moisture Sensitivity Level (MSL), please see device information page for HIP2120, HIP2121. For more information on MSL please see tech brief

TB363.

FN7668.0

December 23, 2011

3

HIP2120, HIP2121

Table of Contents

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Maximum Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Functional Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Selecting the Boot Capacitor Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Typical Application Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Transients on HS Node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

PC Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

EPAD Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

L9.4x4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

L10.4x4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

FN7668.0

December 23, 2011

4

HIP2120, HIP2121

Absolute Maximum Ratings

Thermal Information

Supply Voltage, V , V - V (Notes 5, 6) . . . . . . . . . . . . . . . -0.3V to 18V

Thermal Resistance (Typical)

θ

_JA(°C/W)

42

θ

_JC(°C/W)

DD HB HS

PWM and EN Input Voltage (Note 6) . . . . . . . . . . . . . . .-0.3V to VDD + 0.3V

Voltage on LO (Note 6). . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to VDD + 0.3V

Voltage on HO (Note 6) . . . . . . . . . . . . . . . . . . . . . VHS - 0.3V to VHB + 0.3V

Voltage on HS (Continuous) (Note 6) . . . . . . . . . . . . . . . . . . . . . -1V to 110V

Voltage on HB (Note 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118V

10 Ld TDFN (Notes 7, 8) . . . . . . . . . . . . . . .

9 Ld TDFN (Notes 7, 8) . . . . . . . . . . . . . . . .

Max Power Dissipation at +25°C in Free Air

10 Ld TDFN (Notes 7, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0W

9 Ld TDFN (Notes 7, 8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1W

Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

4

42

Average Current in V to HB Diode . . . . . . . . . . . . . . . . . . . . . . . . . 100mA

DD

Maximum Recommended Operating

Conditions

ESD Ratings

Human Body Model Class 2 (Tested per JESD22-A114E). . . . . . . . . . 3000V

Machine Model Class B (Tested per JESD22-A115-A). . . . . . . . . . . . . . 300V

Charged Device Model Class IV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000V

Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V to 14V

DD

Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 100V

Voltage on HS . . . . . . . . . . . . . . . . . . . . . .(Repetitive Transient) -5V to 105V

Voltage on HB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V + 8V to V + 14V and

HS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V - 1V to V + 100V

DD DD

HS Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <50V/ns

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

5. The HIP2120 and HIP2121 are capable of derated operation at supply voltages exceeding 14V. Figure 20 shows the high-side voltage derating curve

for this mode of operation.

6. All voltages referenced to V unless otherwise specified.

SS

7. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech

JA

Brief TB379.

8. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Electrical Specifications

V

= V = 12V, V = V = 0V, R = 0 , PWM = 0V, No Load on LO or HO, Unless Otherwise Specified.

HB SS HS DT

DD

Boldface limits apply over the operating temperature range, -40°C to +125°C.

K

T

= +25°C

T = -40°C to +125°C

A

PARAMETERS

SYMBOL

TEST CONDITIONS

MIN

TYP MAX MIN (Note 9) MAX (Note 9) UNITS

SUPPLY CURRENTS

I

R

= 80k

-

470 850

-

900

2.2

3

µA

mA

µA

DD80

DT

V

Quiescent Current

Operating Current

DD

I

= 8k

1.0

2.5

3.4

65

2.1

3

DD8k

I

f = 500kHz, R = 80k

DT

DDO80k

I

f = 500kHz, R = 8k

DT

4

DDO8k

Total HB Quiescent Current

Total HB Operating Current

I

LI = HI = 0V

f = 500kHz

115

2.5

1.5

150

3

HB

I

2.0

0.05

1.2

mA

µA

HBO

HB to V Current, Quiescent

SS

I

LI = HI = 0V; V = V = 114V

HB HS

10

1.6

HBS

HB to V Current, Operating

SS

I

f = 500kHz; V = V = 114V

mA

HBSO

HB

HS

INPUT PINS

Low Level Input Voltage

Threshold

V

HIP2120 (CMOS)

HIP2121 (3.3V/TTL)

HIP2120 (CMOS)

3.7

4.4

1.8

-

2.7

1.2

5.3

-

IL

V

Low Level Input Voltage

Threshold

1.4

-

High Level Input Voltage

Threshold

V

-

6.54 7.93

8.2

2.4

IH

V

High Level Input Voltage

Threshold

HIP2121 ((3.3V/TTL)

1.8

2.2

FN7668.0

December 23, 2011

5

HIP2120, HIP2121

Electrical Specifications

V

= V = 12V, V = V = 0V, R = 0 , PWM = 0V, No Load on LO or HO, Unless Otherwise Specified.

DD

HB

SS

HS

DT

K

Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)

T

= +25°C

T = -40°C to +125°C

A

PARAMETERS

SYMBOL

TEST CONDITIONS

HIP2120 (CMOS)

MIN

TYP MAX MIN (Note 9) MAX (Note 9) UNITS

Input Voltage Hysteresis

V

-

2.2

-

V

IHYS

Input Pull-down Resistance

UNDERVOLTAGE PROTECTION

R

210

100

500

kΩ

I

V

Rising Threshold

V

6.8

7.3

0.6

6.9

0.6

7.8

6.5

8.1

V

DD

DDR

DDH

HBR

HBH

Threshold Hysteresis

-

6.2

-

7.5

-

5.9

-

7.8

-

HB Rising Threshold

HB Threshold Hysteresis

BOOTSTRAP DIODE

Low Current Forward Voltage

High Current Forward Voltage

Dynamic Resistance

V

I

= 100mA

-

0.6

0.7

0.8

0.7

0.9

1

-

0.8

1

V

DL

VDD-HB

V

DH

R

1.5

Ω

D

LO GATE DRIVER

Low Level Output Voltage

High Level Output Voltage

Peak Pull-Up Current

V

I

= 100mA

-

0.25

2

0.4

-

0.5

V

A

OLL

OHL

LO

V

= -100mA, V

= 0V

= V - V

DD LO

0.4

0.5

LO

OHL

I

V

-

LO

Peak Pull-Down Current

HO GATE DRIVER

I

= 12V

2

OLL

Low Level Output Voltage

High Level Output Voltage

Peak Pull-Up Current

V

I

= 100mA

-

0.25

2

0.4

-

0.5

V

A

OLH

OHH

HO

V

= -100mA, V

= 0V

= V - V

HB HO

0.4

0.5

HO

OHH

I

V

-

HO

Peak Pull-Down Current

I

= 12V

2

OLH

Switching Specifications

V

= V = 12V, V = V = 0V, RDT = 0kΩ, No Load on LO or HO, Unless Otherwise Specified. Boldface

HB SS HS

DD

limits apply over the operating temperature range, -40°C to +125°C.

T = +25°C

T = -40°C to +125°C

J

TEST

MIN

MAX

PARAMETERS

HO Turn-Off Propagation Delay

SYMBOL

CONDITIONS

MIN

-

TYPE MAX

(Note 9)

UNITS

ns

t

32

50

300

-

60

-

PLHO

PWM Falling to HO Falling

LO Turn-Off Propagation Delay

PWM Rising to LO Falling

t

-

ns

PLLO

Minimum Dead-Time Delay (see Note 10)

HO Falling to LO Rising

R

= 80k,

DT

PWM 1 to 0

t

15

150

-

35

10

DTHLmin

DTLHmin

Minimum Dead-Time Delay (see Note 10)

LO Falling to HO Rising

R

= 80k

DT

PWM 0 to 1

25

10

Maximum Dead-Time Delay (see Note 10)

HO Falling to LO Rising

R

= 8k,

DT

PWM 1 to 0

t

220

10

-

DTHLmax

DTLHmax

Maximum Dead-Time Delay (see Note 10)

LO Falling to HO Rising

R

= 8k,

DT

PWM 0 to 1

-

Either Output Rise/Fall Time

(10% to 90%/90% to 10%)

t

C = 1nF

-

RC, FC

L

FN7668.0

December 23, 2011

6

HIP2120, HIP2121

Switching Specifications

V

= V = 12V, V = V = 0V, RDT = 0kΩ, No Load on LO or HO, Unless Otherwise Specified. Boldface

DD

HB

SS

HS

limits apply over the operating temperature range, -40°C to +125°C. (Continued)

T = +25°C

T = -40°C to +125°C

J

TEST

CONDITIONS

MIN

(Note 9)

MAX

(Note 9)

PARAMETERS

Either Output Rise/Fall Time

SYMBOL

MIN

TYPE MAX

UNITS

µs

t

C = 0.1mF

-

0.5

10

0.6

-

0.8

-

R, F

L

(3V to 9V/9V to 3V)

Bootstrap Diode Turn-On or Turn-Off Time

NOTES:

t

ns

BS

9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits are established by

characterization and are not production tested.

10. Dead-Time is defined as the period of time between the LO falling and HO rising or between HO falling and LO rising.

Timing Diagram

t_R

t_PLHO

t_PLLO

t_F

PWM

HO

90%

10%

90%

10%

LO

EN

t_DTHL

t_DTLH

FN7668.0

December 23, 2011

7

HIP2120, HIP2121

Typical Performance Curves

10.0

T = -40°C

T = +25°C

1.0

T = +125°C

T = +150°C

T = +125°C

T = +150°C

0.1

10k

100k

FREQUENCY (Hz)

1M

10k

100k

FREQUENCY (Hz)

1M

FIGURE 4. HIP2121 I OPERATING CURRENT vs FREQUENCY

DD

FIGURE 3. HIP2120 I OPERATING CURRENT vs FREQUENCY

DD

10.0

T = -40°C

T = +150°C

1.0

T = +25°C

T = -40°C

T = +150°C

T = +25°C

0.1

T = +125°C

0.01

10k

100k

1M

10k

100k

1M

FREQUENCY (Hz)

FIGURE 5. I OPERATING CURRENT vs FREQUENCY

HB

FIGURE 6. I

OPERATING CURRENT vs FREQUENCY

HBS

300

200

150

100

V

= V

= 14V

HB

DD

250

200

150

100

50

V

= V = 14V

HB

DD

V

DD

= V

= 8V

HB

V

= V

= 8V

HB

DD

V

= V

= 12V

50

DD

HB

V

= V

50

= 12V

HB

DD

50

-50

0

100

150

-50

0

100

150

TEMPERATURE (°C)

FIGURE 8. LOW LEVEL OUTPUT VOLTAGE vs TEMPERATURE

FIGURE 7. HIGH LEVEL OUTPUT VOLTAGE vs TEMPERATURE

FN7668.0

December 23, 2011

8

HIP2120, HIP2121

Typical Performance Curves (Continued)

0.70

0.65

0.60

0.55

0.50

0.45

0.40

6.7

6.5

6.3

6.1

5.9

5.7

5.5

5.3

V

DDR

V

HBH

V

HBR

V

DDH

-50

0

50

TEMPERATURE (°C)

100

150

-50

0

50

TEMPERATURE (°C)

100

150

FIGURE 10. UNDERVOLTAGE LOCKOUT HYSTERESIS vs

TEMPERATURE

FIGURE 9. UNDERVOLTAGE LOCKOUT THRESHOLD vs

TEMPERATURE

55

50

55

50

t

LPLH

t

LPLH

45

40

35

30

25

45

40

35

30

25

t

HPLH

t

HPLH

t

LPHL

t

LPHL

t

HPHL

50

t

HPHL

-50

0

100

150

-50

0

50

100

150

TEMPERATURE (°C)

FIGURE 11. HIP2120 PROPAGATION DELAYS vs TEMPERATURE

FIGURE 12. HIP2121 PROPAGATION DELAYS vs TEMPERATURE

8.0

10.0

9.5

7.5

9.0

t

MON

7.0

6.5

6.0

5.5

5.0

4.5

4.0

MON

8.5

8.0

7.5

7.0

6.5

6.0

5.5

5.0

4.5

4.0

t

MOFF

t

MOFF

-50

0

50

TEMPERATURE (°C)

100

150

-50

0

50

TEMPERATURE (°C)

100

150

FIGURE 13. HIP2120 DELAY MATCHING vs TEMPERATURE

FIGURE 14. HIP2121 DELAY MATCHING vs TEMPERATURE

FN7668.0

December 23, 2011

9

HIP2120, HIP2121

Typical Performance Curves (Continued)

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

2

4

6

8

10

12

0

2

4

6

8

10

12

V

, V

(V)

V

, V

(V)

LO HO

FIGURE 16. PEAK PULL-DOWN CURRENT vs OUTPUT VOLTAGE

FIGURE 15. PEAK PULL-UP CURRENT vs OUTPUT VOLTAGE

120

110

320

300

I

DD

280

260

240

220

200

180

160

140

120

100

80

I

100

90

80

70

60

50

40

30

20

10

0

DD

I

HB

I

HB

60

40

20

0

5

10

, V

15

20

0

5

10

15

20

V

(V)

V

, V

(V)

DD HB

FIGURE 17. HIP2120 QUIESCENT CURRENT vs VOLTAGE

FIGURE 18. HIP2121 QUIESCENT CURRENT vs VOLTAGE

1.00

0.10

0.01

120

100

80

60

40

20

0

.

-3

-4

-5

-6

1 10

.

1 10

.

1 10

.

1 10

12

13

14

15

16

0.3

0.4

0.5

0.6

0.7

0.8

V

TO V VOLTAGE (V)

FORWARD VOLTAGE (V)

HS

SS

FIGURE 19. BOOTSTRAP DIODE I-V CHARACTERISTICS

FIGURE 20. V VOLTAGE vs V VOLTAGE

HS DD

FN7668.0

December 23, 2011

10

HIP2120, HIP2121

gate charge of the driven power FET for approximately a 5% drop

in voltage after the charge has been transferred from the boot

capacitor to the gate capacitance.

Functional Description

Functional Overview

When connected to a half bridge, the output of the bridge on the

HS node follows the PWM input. In other words, when the PWM

input is high, the high-side bridge FET is turned on and the

low-side FET is off. When the PWM input is low, the low-side

bridge FET is turned on and the high-side is turned off. The

enable pin (EN), when low, drives both outputs to a low state.

The following parameters are required to calculate the value of

the boot capacitor for a specific amount of voltage droop. In this

example, the values used are arbitrary. They should be changed

to comply with the actual application.

V

= 10V

V

can be any value between 7 and 14VDC

DD

HB

= V - 0.6V

DD

High side driver bias voltage (V - boot diode

DD

When the PWM input transitions high or low, it is necessary to

insure that both bridge FETS are not on at the same time to

prevent shoot-through currents (break before make). The internal

programmable timers delay the rising edge of either output

resulting with both outputs being off before either of the bridge

= V

voltage) referenced to V

HO

HS

Period = 1ms

This is the longest expected switching period

I

= 100µA

Worst case high side driver current when

xHO = high

HB

FETs is driven on. An 8kΩ resistor connected between R and

DT

(this value is specified for V = 12V but the

DD

VSS results in a nominal dead time of 220ns. An 80kΩ results

with a minimum nominal dead time of 25ns. Resistors values

less than 8k and greater than 80k are not recommended.

error is not significant)

R

= 100kΩ

Gate-source resistor

(usually not needed)

GS

The high-side driver bias is established by the boot capacitor

connected between HB and HS. The charge on the boot capacitor

is provided by the internal boot diode that is connected to VDD.

The current path to charge the boot capacitor occurs when the

low-side bridge FET is on. This charge current is limited in

amplitude by the inherent resistance of the boot diode and by the

drain-source voltage of the low-side FET. Assuming that the on

time of the low-side FET is sufficiently long to fully charge the

boot capacitor, the boot voltage will charge very close to VDD

(less the boot diode drop and the low-side FET on voltage).

Ripple= 5%

Desired ripple voltage on the boot cap (larger

ripple is not recommended)

I

= 100nA

From the FET vendor’s datasheet

From Figure 21

gate_leak

Qgate80V = 64nC

12

I

= 33A

D

V

= 80V

DS

10

8

When the PWM input transitions high, the high-side bridge FET is

driven on after the dead time. Because the HS node is connected

to the source of the high-side FET, the HS node will rise almost to

the level of the bridge voltage (less the conduction voltage across

the bridge FET). Because the boot capacitor voltage is referenced

V

= 50V

DS

V

= 20V

DS

6

4

to the source voltage of the high-side FET, the HB node is V

DD

volts above the HS node and the boot diode is reversed biased.

Because the high-side driver circuit is referenced to the HS node,

the HO output is now approximately VHB + VBRIDGE above

ground.

2

0

10

20

30

40

50

60

70

80

QG TOTAL GATE CHARGE (nC)

During the low to high transition of the HS node, the boot

capacitor sources the necessary gate charge to fully enhance the

high-side bridge FET gate. After the gate is fully charged, the boot

capacitor no longer sources the charge to the gate but continues

to provide bias current to the high-side driver. It is clear that the

charge of the boot capacitor must be substantially larger than

the required charge of the high-side FET and high-side driver

otherwise the boot voltage will sag excessively. If the boot

capacitor value is too small for the required maximum of on-time

of the high-side FET, the high-side UV lockout may engage

resulting with an unexpected operation.

FIGURE 21. TYPICAL GATE CHARGE OF A POWER FET

The following equations calculate the total charge required for

the Period. This equation assumes that all of the parameters are

constant during the period duration. The error is insignificant if

the ripple is small.

Q = Q

gate80V

+ Period x (I + V /R + I

HB HO GS

)

gate_leak

c

C

= Q /(Ripple * VDD)

c

boot

= 0.52µF

If the gate to source resistor is removed (R is usually not needed

GS

or recommended), then:

Application Information

Selecting the Boot Capacitor Value

C

= 0.33µF

boot

The boot capacitor value is chosen not only to supply the internal

bias current of the high-side driver but also, and more

significantly, to provide the gate charge of the driven FET without

causing the boot voltage to sag excessively. In practice, the boot

capacitor should have a total charge that is about 20 times the

FN7668.0

December 23, 2011

11

HIP2120, HIP2121

8V TO 15V

100V MAX

VDD

HB

HI

DRIVER

HO

HS

PWM

CONTROLLER

EN

LO

DRIVER

RDT

VSS

ISL78420

FIGURE 22. TYPICAL HALF BRIDGE APPLICATION

Typical Application Circuit

Figure 22 is an example of how the HIP2120/21 can be

configured for a half bridge power supply application.

H O

H S

IN D U C T IV E

L O A D

Depending on the application, the switching speed of the bridge

FETs can be reduced by adding series connected resistors

between the xHO outputs and the FET gates. Gate-Source

resistors are recommended on the low-side FETs to prevent

unexpected turn-on of the bridge should the bridge voltage be

applied before VDD. Gate-source resistors on the high-side FETs

are not usually required if low-side gate-source resistors are

used. If relatively small gate-source resistors are used on the

high-side FETs, be aware that they will load the boot capacitor,

which will then require a larger value for the boot capacitor.

-

+

L O

-

+

V S S

FIGURE 23. PARASITIC INDUCTANCE CAUSES TRANSIENTS ON HS

NODE

There are several ways of reducing the amplitude of this

transient. If the bridge FETs are turned off more slowly to reduce

di/dt, the amplitude will be reduced but at the expense of more

switching losses in the FETs. Careful PCB design will also reduce

the value of the parasitic inductance. However, these two

solutions by themselves may not be sufficient. Figure 19

illustrates a simple method for clamping the negative transient.

A fast PN junction, 1A diode is connected between xHS and VSS

as shown. It is important that this diode be placed as close as

possible to the xHS and VSS pins to minimize the parasitic

inductance of this current path. Because this clamping diode is

essentially in parallel with the body diode of the low-side FET, a

small value resistor is necessary to limit current when the body

diode of the low-side bridge FET is conducting during the dead

time.

Transients on HS Node

An important operating condition that is frequently overlooked by

designers is the negative transient on the xHS pins that occurs

when the high side bridge FET turns off. The Absolute Maximum

transient allowed on the xHS pin is -6V but it is wise to minimize

the amplitude to lower levels. This transient is the result of the

parasitic inductance of the low-side drain-source conductor on

the PCB. Even the parasitic inductance of the low-side FET

contributes to this transient.

When the high-side bridge FET turns off (see Figure 23), because

of the inductive characteristics the load, the current that was

flowing in the high-side FET (blue) must rapidly commutate to

flow through the low-side FET (red). The amplitude of the

negative transient impressed on the xHS node is (di/dt x L) where

L is the total parasitic inductance of the low-side FET

drain-source path and di/dt is the rate at which the high-side FET

is turned off. With the increasing power levels of power supplies

and motor, clamping this transient become more and more

significant for the proper operation of the HIP2120/21.

Please note that a similar transient with a positive polarity occurs

when the low-side FET turns off. This is less frequently a problem

because xHS node is floating up toward the bridge bias voltage. The

Absolute Max voltage rating for the xHS node does need to be

observed when the positive transient occurs.

FN7668.0

December 23, 2011

12

HIP2120, HIP2121

Power Dissipation

The dissipation of the HIP2120/21 is dominated by the gate

charge required by the driven bridge FETs and the switching

frequency. The internal bias and boot diode also contribute to the

total dissipation but these losses are usually insignificant

compared to the gate charge losses.

• Keep power loops as short as possible by paralleling the

source and return traces.

• Use planes where practical; they’re usually more effective than

parallel traces.

• Planes can also be non-grounded nodes.

The calculation of the power dissipation of the HIP2120/21 is

very simple.

• Avoid paralleling high di/dt traces with low level signal lines.

High di/dt will induce currents in the low level signal lines.

GATE POWER (FOR THE HO AND LO OUTPUTS)

• When practical, minimize impedances in low level signal

circuits; the noise, magnetically induced on a 10k resistor, is

10x larger than the noise on a 1k resistor.

P

= 4 x Q x Freq x VDD

gate

where

is the charge of the driven bridge FET at VDD, and

• Be aware of magnetic fields emanating from transformers and

inductors. Core gaps in these structures are especially bad for

emitting flux.

Q

gate

Freq is the switching frequency.

• If you must have traces close to magnetic devices, align the

traces so that they are parallel to the flux lines.

BOOT DIODE DISSIPATION

I

= Q

gate

x Freq

x 0.6V

diode_avg

= I

• The use of low inductance components such as chip resistors

and chip capacitors is recommended.

P

diode diode_avg

where 0.6V is the diode conduction voltage

• Use decoupling capacitors to reduce the influence of parasitic

inductors. To be effective, these capacitors must also have the

shortest possible lead lengths. If vias are used, connect several

paralleled vias to reduce the inductance of the vias.

BIAS CURRENT

P

= I

x VDD

is the internal bias current of the HIP2120/21 at the

bias

where I

• It may be necessary to add resistance to dampen resonating

parasitic circuits. The most likely circuit will be the HO and LO

outputs. In PCB designs with long leads on the LI and HI inputs,

it may also be necessary to add series resistors with the LI and

HI inputs.

bias

switching frequency

TOTAL POWER DISSIPATION

P

= P

gate

+ P

diode bias

total

• Keep high dv/dt nodes away from low level circuits. Guard

banding can be used to shunt away dv/dt injected currents

from sensitive circuits. This is especially true for the PWM

control circuits.

OPERATING TEMPERATURES

T = P x θ + T

j

total

JA

amb

where T is the junction temperature at the operating air

j

temperature, T

, in the vicinity of the part.

x θ + T

JC PCB

• Avoid having a signal ground plane under a high dv/dt circuit.

This will inject high di/dt currents into the signal ground paths.

amb

T = P

j

total

• Do power dissipation and voltage drop calculations of the

power traces. Most PCB/CAD programs have built in tools for

calculation of trace resistance.

where T is the junction temperature with the operating

j

temperature of the PCB, T

soldered.

, measured where the EPAD is

PCB

• Large power components (Power FETs, Electrolytic capacitors,

power resistors, etc.) will have internal parasitic inductance,

which cannot be eliminated. This must be accounted for in the

PCB layout and circuit design.

PC Board Layout

The AC performance of the HIP2120/21 depends significantly on

the design of the PC board. The following layout design

guidelines are recommended to achieve optimum performance

from the HIP2120/21:

• If you simulate your circuits, consider including parasitic

components.

• Understand well how power currents flow. The high amplitude

di/dt currents of the bridge FETs will induce significant voltage

transients on the associated traces.

FN7668.0

December 23, 2011

13

HIP2120, HIP2121

Depending on the amount of power dissipated by the HIP2120/21,

EPAD Design Considerations

it may be necessary, to connect the EPAD to one or more ground

plane layers. A via array, within the area of the EPAD, will conduct

heat from the EPAD to the gnd plane on the bottom layer. If inner

PCB layers are available, it is also be desireable to connect these

additional layers with the plated-through vias.

The thermal pad of the HIP2120/21 is electrically isolated. It’s

primary function is to provide heat sinking for the IC. It is

recommended to tie the EPAD to V (GND).

SS

Figure 24 is an example of how to use vias to remove heat from

the IC substrate.

The number of vias and the size of the GND planes required for

adequate heatsinking is determined by the power dissipated by

the HIP2120/21, the air flow, and the maximum temperature of

the air around the IC.

EPAD

GND

EPAD

GND

PLANE

It is important that the vias have a low thermal resistance for

efficient heat transfer. Do not use “thermal relief” patterns to

connect the vias.

FIGURE 24. PCB VIA PATTERN

BOTTOM

LAYER

COMPONENT

LAYER

FIGURE 24. TYPICAL PCB PATTERN FOR THERMAL VIAS

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you

have the latest revision.

DATE

REVISION

FN7668.0

CHANGE

December 23, 2011

Initial Release

Products

Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products

address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.

Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a

complete list of Intersil product families.

For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on

intersil.com: HIP2120, HIP2121

To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff

FITs are available from our website at: http://rel.intersil.com/reports/search.php

For additional products, see www.intersil.com/product_tree

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time

without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be

accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN7668.0

December 23, 2011

14

HIP2120, HIP2121

Package Outline Drawing

L9.4x4

9 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE

Rev 1, 1/10

3.2 REF

4.00

A

PIN #1 INDEX AREA

6

6X 0.80 BSC

B

4

1

9X 0 . 40 ± 0.100

6

PIN 1

INDEX AREA

4.00

2.20

1.2 REF

0.15

(4X)

9

5

0.10 M C A B

C

0.05 M

9 X 0.30

4

TOP VIEW

(3.00)

3.00

BOTTOM VIEW

SEE DETAIL "X"

0 .75

(9 X 0.60)

C

0.10

C

BASE PLANE

SEATING PLANE

0.08

C

SIDE VIEW

(3.80)

(2.20)

(1.2)

4

0 . 2 REF

C

0 . 00 MIN.

0 . 05 MAX.

(9X 0.30)

(6X 0.8)

DETAIL "X"

TYPICAL RECOMMENDED LAND PATTERN

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

3.

Unless otherwise specified, tolerance : Decimal ± 0.05

4. E-Pad is offset from center.

Tiebar (if present) is a non-functional feature.

5.

6.

The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

FN7668.0

December 23, 2011

15

HIP2120, HIP2121

Package Outline Drawing

L10.4x4

10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE

Rev 1, 1/08

3.2 REF

4.00

A

PIN #1 INDEX AREA

6

8X 0.80 BSC

B

5

1

10X 0 . 40

6

PIN 1

INDEX AREA

4.00

2.60

0.15

(4X)

10

6

0.10 M C A B

C

0.05 M

10 X 0.30

4

TOP VIEW

( 3.00 )

3.00

BOTTOM VIEW

SEE DETAIL "X"

0 .75

( 10 X 0.60 )

C

0.10

C

BASE PLANE

SEATING PLANE

0.08

C

SIDE VIEW

( 3.80)

( 2.60)

0 . 2 REF

C

0 . 00 MIN.

0 . 05 MAX.

( 8X 0 . 8 )

( 10X 0 . 30 )

DETAIL "X"

TYPICAL RECOMMENDED LAND PATTERN

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

3.

Unless otherwise specified, tolerance : Decimal ± 0.05

4. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

5.

6.

The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

FN7668.0

December 23, 2011

16


型号：	HIP2121FRTBZ
厂家：	Intersil
描述：	100V, 2A Peak, High Frequency Half-Bridge Drivers with Adjustable Dead Time Control and PWM Input 100V ， 2A峰值，高频半桥，可调节死区时间控制和PWM输入驱动器驱动器
文件：	总16页 (文件大小：413K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HIP2121FRTBZ [INTERSIL]

相关型号：

HIP2122

HIP2122FRTAZ

HIP2122FRTBZ

HIP2123

HIP2123FRTAZ

HIP2123FRTBZ

HIP2500

HIP2500IB

HIP2500IP

HIP2500IP1

HIP2500IW

HIP4010