HIP2122 [INTERSIL]
100V, 2A Peak, High Frequency Half-Bridge Drivers with Rising Edge Delay Timer; 100V ， 2A峰值，高频半桥上升沿延时定时器驱动程序
| 型号： | HIP2122 |
| 厂家： | 
Intersil |
| 描述： | 100V, 2A Peak, High Frequency Half-Bridge Drivers with Rising Edge Delay Timer |
| 文件： | 总16页 (文件大小：516K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
100V, 2A Peak, High Frequency Half-Bridge Drivers with
Rising Edge Delay Timer
HIP2122, HIP2123
Features
• 9 Ld TDFN “B” Package Compliant with 100V Conductor
Spacing Guidelines per IPC-2221
The HIP2122 and HIP2123 are 100V, high frequency, half-bridge
MOSFET driver ICs. They are based on the popular ISL2100A and
ISL2101A half-bridge drivers. Like the ISL2100A, two logic
inputs, LI and HI, control both bridge outputs, LO and HO. All logic
• Break-Before-Make Dead-Time Prevents Shoot-through and is
adjustable up to 220ns
inputs are V tolerant.
DD
• Bootstrap Supply Max Voltage to 114VDC
• Wide Supply Voltage Range (8V to 14V)
• Supply Undervoltage Protection
These drivers have a programmable dead-time to insure
break-before-make operation between the high-side and low-side
drivers. The dead-time is adjustable up to 220ns. The internal
logic does not prevent both outputs from turning on
simultaneously if both inputs are high simultaneously for a time
greater than the programmed delay.
• CMOS Compatible Input Thresholds with Hysteresis (HIP2122)
• 1.6Ω/1Ω Typical Output Pull-up/Pull-down Resistance
• On-Chip 1Ω Bootstrap Diode
A single PWM logic input controls both bridge outputs (HO, LO).
An enable pin (EN), when low, drives both outputs to a low state.
Applications
• Telecom Half-Bridge DC/DC Converters
• UPS and Inverters
All logic inputs are V tolerant and the HIP2122 has CMOS
DD
inputs with hysteresis for superior operation in noisy
environments.
• Motor Drives
The HIP2122 has hysteretic inputs with thresholds that are
proportional to V . The HIP2123 has 3.3V logic/TTL compatible
inputs.
DD
• Class-D Amplifiers
• Forward Converter with Active Clamp
Two package options are provided. The 10 lead 4x4 DFN package
has standard pinouts. The 9 lead 4x4 DFN package omits pin 2 to
comply with 100V conductor spacing per IPC-2221.
Related Literature
• FN7668, HIP2120, HIP2121 “100V, 2A Peak, High Frequency
Half-Bridge Drivers with Adjustable Dead Time Control and
PWM Input”
200
160
140
120
100
HALF
BRIDGE
100V MAX
HIP2122, HIP2123
VDD
HB
HI
LI
80
SECONDARY
CIRCUITS
HO
HS
PWM
CONTROLLER
60
RDT
VSS
FEEDBACK
WITH
ISOLATION
40
20
LO
EPAD
8
16
24
32 40 48 56 64 80
RDT (kΩ)
FIGURE 1. TYPICAL APPLICATION
FIGURE 2. DEAD-TIME vs TIMING RESISTOR
December 23, 2011
FN7670.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
HIP2122, HIP2123
Block Diagram
VDD
HB
HO
HS
HIP2122,
HIP2123
UNDER
VOLTAGE
LEVEL
SHIFT
HIP2122
HIP2122/23
HO
DELAY
UNDER
VOLTAGE
RDT
OPTIONAL INVERSION
FOR FUTURE PART
NUMBERS
LO
LO
DELAY
EPAD IS
ELECTRICALLY
ISOLATED
HIP2122
HIP2122/23
VSS
EPAD
Pin Configurations
HIP2122, HIP2123
HIP2122, HIP2123
(9 LD 4X4 TDFN)
TOP VIEW
(10 LD 4X4 TDFN)
TOP VIEW
VDD
HB
HO
HS
1
2
3
4
5
10 LO
VDD
1
10 LO
9
8
7
6
VSS
9
8
7
6
VSS
EPAD
EPAD
LI
HB
HO
HS
3
4
5
LI
HI
HI
NC
RDT
RDT
FN7670.0
December 23, 2011
2
HIP2122, HIP2123
Pin Descriptions
9 LD TDFN 10 LD TDFN SYMBOL
DESCRIPTION
1
3
1
2
VDD
HB
Positive supply voltage for lower gate driver. Decouple this pin with a ceramic capacitor to VSS.
High-side bootstrap supply voltage referenced to HS. Connect the positive side of bootstrap capacitor to this pin.
Bootstrap diode is on-chip.
4
5
3
4
HO
HS
High-side output. Connect to gate of high-side power MOSFET.
High-side source connection. Connect to source of high-side power MOSFET. Connect the negative side of
bootstrap capacitor to this pin.
8
7
8
7
LI
HI
Low side driver input. For LI = 1, LO = 1 after programmed delay time; for LI = 0, LO = 0 with minimal delay.
High side driver input. For HI = 1, HO = 1 after programmed delay time; for Hi = 0, HO = 0 with minimal delay.
Negative supply input, which will generally be ground.
9
9
VSS
LO
10
-
10
5
Low-side output. Connect to gate of low-side power MOSFET.
NC
RDT
No Connect. This pin is isolated from all other pins.
6
6
A resistor connected between this pin and VSS adds additional delay time to the normal rising edge propagation
delay.
-
-
EPAD Exposed pad. Connect to ground or float. The EPAD is electrically isolated from all other pins.
Ordering Information
PART NUMBER
PART
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
(Notes 1, 2, 4)
MARKING
HIP 2122AZ
HIP 2123AZ
HIP 2122BZ
HIP 2123BZ
INPUT
CMOS
HIP2122FRTAZ
- 40 to +125
- 40 to +125
- 40 to +125
- 40 to +125
10 Ld 4x4 TDFN
L10.4x4
HIP2123FRTAZ
3.3V/TTL
CMOS
10 Ld 4x4 TDFN
9 Ld 4x4 TDFN
9 Ld 4x4 TDFN
L10.4x4
L9.4x4
L9.4x4
HIP2122FRTBZ (Note 3)
HIP2123FRTBZ (Note 3)
NOTES:
3.3V/TTL
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
PbHfree products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. “B” package option has alternate pin assignments for compliance with 100V Conductor Spacing Guidelines per IPC-2221. Note that Pin 2 is omitted
for additional spacing.
4. For Moisture Sensitivity Level (MSL), please see device information page for HIP2122, HIP2123. For more information on MSL please see tech brief
TB363.
FN7670.0
December 23, 2011
3
HIP2122, HIP2123
Table of Contents
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Maximum Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
ESD Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Switching Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Selecting the Boot Capacitor Value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Transients on HS Node . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PC Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
EPAD Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
FN7670.0
December 23, 2011
4
HIP2122, HIP2123
Absolute Maximum Ratings
Thermal Information
Supply Voltage, V , V - V (Notes 5, 6) . . . . . . . . . . . . . . . -0.3V to 18V
Thermal Resistance (Typical)
θ
JA (°C/W)
42
θ
JC (°C/W)
DD HB HS
LI and HI Input Voltage (Note 6) . . . . . . . . . . . . . . . . . . .-0.3V to VDD + 0.3V
Voltage on LO (Note 6). . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to VDD + 0.3V
Voltage on HO (Note 6) . . . . . . . . . . . . . . . . . . . . . VHS - 0.3V to VHB + 0.3V
Voltage on HS (Continuous) (Note 6) . . . . . . . . . . . . . . . . . . . . . -1V to 110V
Voltage on HB (Note 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118V
10 Ld TDFN (Notes 7, 8) . . . . . . . . . . . . . . .
9 Ld TDFN (Notes 7, 8) . . . . . . . . . . . . . . . .
Max Power Dissipation at +25°C in Free Air
10 Ld TDFN (Notes 7, 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0W
9 Ld TDFN (Notes 7, 8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1W
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
4
4
42
Average Current in V to HB Diode . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
DD
Maximum Recommended Operating
Conditions
Supply Voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V to 14V
Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 100V
Voltage on HS . . . . . . . . . . . . . . . . . . . . . .(Repetitive Transient) -5V to 105V
DD
ESD Ratings
Human Body Model Class 2 (Tested per JESD22-A114E). . . . . . . . . . 3000V
Machine Model Class B (Tested per JESD22-A115-A). . . . . . . . . . . . . . 300V
Charged Device Model Class IV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000V
Voltage on HB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V + 8V to V + 14V and
HS HS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V - 1V to V + 100V
DD DD
HS Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <50V/ns
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. The HIP2122 and HIP2123 are capable of derated operation at supply voltages exceeding 14V. Figure 20 shows the high-side voltage derating curve
for this mode of operation.
6. All voltages referenced to V unless otherwise specified.
SS
7. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
8. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications
V
= V = 12V, V = V = 0V, R = 0 , PWM= 0V, No Load on LO or HO, Unless Otherwise Specified.
HB SS HS DT
DD
Boldface limits apply over the operating temperature range, -40°C to +125°C.
K
T
= +25°C
T = -40°C to +125°C
A
A
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP MAX MIN (Note 9) MAX (Note 9) UNITS
SUPPLY CURRENTS
V
Quiescent Current
I
R
R
= 80k
-
-
-
-
-
-
-
-
470 850
-
-
-
-
-
-
-
-
900
2.2
3
µA
mA
mA
mA
µA
DD
DD80
DT
DT
I
= 8k
1.0
2.5
3.4
65
2.1
3
DD8k
V
Operating Current
I
f = 500kHz, R = 80k
DT
DD
DDO80k
I
f = 500kHz, R = 8k
DT
4
4
DDO8k
Total HB Quiescent Current
Total HB Operating Current
I
LI = HI = 0V
f = 500kHz
115
2.5
1.5
1.5
150
3
HB
I
2.0
0.05
1.2
mA
µA
HBO
HB to V Current, Quiescent
SS
I
LI = HI = 0V; V = V = 114V
HB HS
10
1.6
HBS
HB to V Current, Operating
SS
I
f = 500kHz; V = V = 114V
mA
HBSO
HB
HS
INPUT PINS
Low Level Input Voltage
Threshold
V
V
HIP2122 (CMOS)
HIP2123 (3.3V/TTL)
HIP2122 (CMOS)
3.7
4.4
1.8
-
-
2.7
1.2
5.3
-
-
IL
IL
V
V
Low Level Input Voltage
Threshold
1.4
-
High Level Input Voltage
Threshold
V
V
-
-
6.54 7.93
8.2
2.4
IH
IH
V
V
High Level Input Voltage
Threshold
HIP2123 ((3.3V/TTL)
1.8
2.2
FN7670.0
December 23, 2011
5
HIP2122, HIP2123
Electrical Specifications
V
= V = 12V, V = V = 0V, R = 0 , PWM= 0V, No Load on LO or HO, Unless Otherwise Specified.
DD
HB
SS
HS
DT
K
Boldface limits apply over the operating temperature range, -40°C to +125°C.
T
= +25°C
T = -40°C to +125°C
A
A
PARAMETERS
SYMBOL
TEST CONDITIONS
HIP2122 (CMOS)
MIN
TYP MAX MIN (Note 9) MAX (Note 9) UNITS
Input Voltage Hysteresis
V
-
-
2.2
-
-
-
-
V
IHYS
Input Pull-down Resistance
UNDERVOLTAGE PROTECTION
R
210
100
500
kΩ
I
V
V
Rising Threshold
V
V
V
V
6.8
7.3
0.6
6.9
0.6
7.8
6.5
8.1
V
V
V
V
DD
DD
DDR
DDH
HBR
HBH
Threshold Hysteresis
-
6.2
-
-
7.5
-
-
5.9
-
-
7.8
-
HB Rising Threshold
HB Threshold Hysteresis
BOOTSTRAP DIODE
Low Current Forward Voltage
High Current Forward Voltage
Dynamic Resistance
V
I
I
I
= 100mA
= 100mA
= 100mA
-
-
-
0.6
0.7
0.8
0.7
0.9
1
-
-
-
0.8
1
V
V
DL
VDD-HB
VDD-HB
VDD-HB
V
DH
R
1.5
Ω
D
LO GATE DRIVER
Low Level Output Voltage
High Level Output Voltage
Peak Pull-Up Current
V
I
I
= 100mA
-
-
-
-
0.25
0.25
2
0.4
-
-
-
-
0.5
V
V
A
A
OLL
OHL
OHL
LO
V
= -100mA, V
= 0V
= V - V
DD LO
0.4
0.5
LO
OHL
I
V
V
-
-
-
-
LO
LO
Peak Pull-Down Current
HO GATE DRIVER
I
= 12V
2
OLL
Low Level Output Voltage
High Level Output Voltage
Peak Pull-Up Current
V
I
I
= 100mA
-
-
-
-
0.25
0.25
2
0.4
-
-
-
-
0.5
V
V
A
A
OLH
OHH
OHH
HO
V
= -100mA, V
= 0V
= V - V
HB HO
0.4
0.5
HO
OHH
I
V
V
-
-
-
-
HO
HO
Peak Pull-Down Current
I
= 12V
2
OLH
FN7670.0
December 23, 2011
6
HIP2122, HIP2123
Switching Specifications
V
= V = 12V, V = V = 0V, RDT = 0kΩ, No Load on LO or HO, Unless Otherwise Specified.
DD
HB
SS
HS
T = +25°C
T = -40°C to +125°C
J
J
PARAMETERS
TEST
MIN
MAX
(see “Timing Diagram”)
SYMBOL
CONDITIONS
MIN
-
TYPE MAX
(Note 9)
(Note 9)
UNITS
ns
HO Turn-Off Propagation Delay
HI Falling to HO Falling
t
32
32
50
50
50
50
300
300
-
-
60
60
60
60
-
PLHO
LO Turn-Off Propagation Delay
LO Falling to LO Falling
t
-
-
ns
ns
ns
ns
ns
ns
PLLO
Minimum Dead-Time Delay (see Note 10)
HO Falling to LO Rising
R
= 80k,
DT
HI 1 to 0, LI 0 to 1
t
t
15
15
150
150
-
35
10
DTHLmin
DTLHmin
Minimum Dead-Time Delay (see Note 10)
LO Falling to HO Rising
R
= 80k
DT
Li 1 to 0, HI 0 to 1
25
10
Maximum Dead-Rising Delay (see Note 10)
HO Falling to LO rising
R
= 8k,
DT
HI 1 to 0, LI 0 to 1
t
t
220
220
10
-
-
-
DTHLmax
DTLHmax
Maximum Dead-Time Delay (see Note 10)
LO Falling to HO Rising
R
= 8k,
DT
Li 1 to 0, HI 0 to 1
-
Either Output Rise/Fall Time
(10% to 90%/90% to 10%)
t
t
C = 1nF
-
RC, FC
L
Either Output Rise/Fall Time
(3V to 9V/9V to 3V)
t
t
C = 0.1mF
-
-
0.5
10
0.6
-
-
-
0.8
-
µs
ns
R, F
L
Bootstrap Diode Turn-On or Turn-Off Time
NOTES:
t
BS
9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits are established by
characterization and are not production tested.
10. Dead-Time is defined as the period of time between the LO falling and HO rising or between HO falling and LO rising when the LI and HI inputs
transition simultaneously.
Timing Diagram
LI
LO
tDT
tDT
90%
10%
90%
10%
HO
HI
tR AND tF FOR LO ARE NOT
SHOWN FOR CLARITY
tR
tPL
tPH
tF
EN
FN7670.0
December 23, 2011
7
HIP2122, HIP2123
Typical Performance Curves
10.0
10.0
T = -40°C
T = -40°C
T = +25°C
T = +25°C
1.0
1.0
T = +125°C
T = +150°C
T = +125°C
T = +150°C
0.1
0.1
10k
100k
FREQUENCY (Hz)
1M
10k
100k
FREQUENCY (Hz)
1M
FIGURE 3. HIP2122 I OPERATING CURRENT vs FREQUENCY
DD
FIGURE 4. HIP2123 I OPERATING CURRENT vs FREQUENCY
DD
10.0
10.0
T = -40°C
T = +150°C
1.0
1.0
T = +25°C
T = -40°C
T = +150°C
T = +25°C
0.1
0.1
T = +125°C
T = +125°C
0.01
0.01
10k
100k
1M
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 5. I OPERATING CURRENT vs FREQUENCY
HB
FIGURE 6. I
OPERATING CURRENT vs FREQUENCY
HBS
300
250
200
150
100
50
200
V
= V
= 14V
HB
DD
V
= V
= 14V
HB
DD
150
100
50
V
DD
= V
= 8V
HB
V
= V = 8V
HB
DD
V
= V
= 12V
50
DD
HB
V
= V
50
= 12V
HB
DD
-50
0
100
150
-50
0
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 7. HIGH LEVEL OUTPUT VOLTAGE vs TEMPERATURE
FIGURE 8. LOW LEVEL OUTPUT VOLTAGE vs TEMPERATURE
FN7670.0
December 23, 2011
8
HIP2122, HIP2123
Typical Performance Curves (Continued)
6.7
6.5
6.3
6.1
5.9
5.7
5.5
5.3
0.70
0.65
0.60
0.55
0.50
0.45
0.40
V
DDR
V
HBH
V
HBR
V
DDH
-50
0
50
TEMPERATURE (°C)
100
150
-50
0
50
TEMPERATURE (°C)
100
150
FIGURE 9. UNDERVOLTAGE LOCKOUT THRESHOLD vs
TEMPERATURE
FIGURE 10. UNDERVOLTAGE LOCKOUT HYSTERESIS vs
TEMPERATURE
55
50
55
50
t
t
LPLH
LPLH
45
40
45
40
t
HPLH
t
HPLH
t
LPHL
35
30
25
35
30
25
t
LPHL
t
HPHL
50
t
HPHL
50
-50
0
100
150
-50
0
100
150
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 11. HIP2122 PROPAGATION DELAYS vs TEMPERATURE
FIGURE 12. HIP2123 PROPAGATION DELAYS vs TEMPERATURE
8.0
7.5
10.0
9.5
9.0
t
t
MON
MON
7.0
6.5
6.0
5.5
5.0
4.5
4.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
t
MOFF
t
MOFF
-50
0
50
TEMPERATURE (°C)
100
150
-50
0
50
TEMPERATURE (°C)
100
150
FIGURE 13. HIP2122 DELAY MATCHING vs TEMPERATURE
FIGURE 14. HIP2123 DELAY MATCHING vs TEMPERATURE
FN7670.0
December 23, 2011
9
HIP2122, HIP2123
Typical Performance Curves (Continued)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
2
4
6
8
10
12
0
2
4
6
8
10
12
V
, V
(V)
V
, V (V)
LO HO
LO HO
FIGURE 15. PEAK PULL-UP CURRENT vs OUTPUT VOLTAGE
FIGURE 16. PEAK PULL-DOWN CURRENT vs OUTPUT VOLTAGE
120
110
320
300
I
DD
280
260
240
220
200
180
160
140
120
100
80
I
DD
100
90
80
70
60
50
40
30
20
10
0
I
HB
I
HB
60
40
20
0
0
5
10
, V
15
20
0
5
10
, V
15
20
V
(V)
V
(V)
DD HB
DD HB
FIGURE 17. HIP2122 QUIESCENT CURRENT vs VOLTAGE
FIGURE 18. HIP2123 QUIESCENT CURRENT vs VOLTAGE
120
100
80
60
40
20
0
1.00
0.10
0.01
.
-3
-4
-5
-6
1 10
.
1 10
.
1 10
.
1 10
12
13
14
15
16
0.3
0.4
0.5
0.6
0.7
0.8
V
TO V VOLTAGE (V)
FORWARD VOLTAGE (V)
HS
SS
FIGURE 19. BOOTSTRAP DIODE I-V CHARACTERISTICS
FIGURE 20. V VOLTAGE vs V VOLTAGE
HS DD
FN7670.0
December 23, 2011
10
HIP2122, HIP2123
of the high-side FET, the high-side UV lockout may engage
resulting with an unexpected operation.
Functional Description
Functional Overview
Application Information
Selecting the Boot Capacitor Value
The HIP2122/23 have independent control inputs, LI and HI, for
each output; LO and HO. When LI is low, LO is low and likewise,
when HI is low, HO is low. The output negative transitions occur
with minimal (and fixed) propagation delays.
The boot capacitor value is chosen not only to supply the internal
bias current of the high-side driver but also, and more
significantly, to provide the gate charge of the driven FET without
causing the boot voltage to sag excessively. In practice, the boot
capacitor should have a total charge that is about 20 times the
gate charge of the driven power FET for approximately a 5% drop
in voltage after the charge has been transferred from the boot
capacitor to the gate capacitance.
The positive transitions of each output are delayed by the
programmed delay as set by RDT. With 80k, the delay is
nominally 25ns. With 8k, the delay is nominally 220ns. Resistors
values less than 8k and greater than 80k are not recommended.
The delay time as a function of R is approximately
DT
t
(ns) = 2/R .
DT
DT
Delaying the rising edge but not the falling edge of each output is
the technique that prevents shoot-thru. Please note that there is
no logic that prevents both outputs from being on if both inputs
are on simultaneously.
The following parameters are required to calculate the value of
the boot capacitor for a specific amount of voltage droop. In this
example, the values used are arbitrary. They should be changed
to comply with the actual application.
The enable pin, EN, when low, drives both outputs to a low state.
V
V
= 10V
V
can be any value between 7 and 14VDC
DD
HB
DD
When the PWM input transitions, it is necessary to insure that
both bridge FETS are not on at the same time to prevent
shoot-through currents (break before make). The programmable
dead time forces both outputs to be off before either of the
= V - 0.6V = V
DD
High side driver bias voltage (V - boot diode
voltage) referenced to V
HO
DD
HS
Period = 1ms
= 100µA
This is the longest expected switching period
bridge FETs is driven on. An 8kΩ resistor connected between R
DT
I
Worst case high side driver current when
xHO = high
(this value is specified for V = 12V but the
HB
and V results in a nominal dead time of 250ns. An 80kΩ
SS
results with a minimum nominal dead time of 50ns. Resistors
values less than 8k and greater than 80k are not recommended.
DD
error is not significant)
Dead-time as a function of R is nominally t (ns) = 2/R
.
DT DT
DT
R
= 100kΩ
Gate-source resistor
(usually not needed)
GS
The high-side driver bias is established by the boot capacitor
connected between HB and HS. The charge on the boot capacitor
is provided by the internal boot diode that is connected to V
Ripple = 5%
Desired ripple voltage on the boot capacitor
(larger ripple is not recommended)
.
DD
The current path to charge the boot capacitor occurs when the
low-side bridge FET is on. This charge current is limited in
amplitude by the inherent resistance of the boot diode and by the
drain-source voltage of the low-side FET. Assuming that the on
time of the low-side FET is sufficiently long to fully charge the
I
= 100nA
From the FET vendor’s datasheet
From Figure 21
gate_leak
Qgate80V = 64nC
boot capacitor, the boot voltage will charge very close to V
(less the boot diode drop and the low-side FET on voltage).
12
DD
I
= 33A
D
V
= 80V
DS
10
8
When the HI input transitions high, the high-side bridge FET is
driven on after the delay time. Because the HS node is connected
to the source of the high-side FET, the HS node will rise almost to
the level of the bridge voltage (less the conduction voltage across
the bridge FET). Because the boot capacitor voltage is referenced
V
= 50V
DS
V
= 20V
DS
6
4
to the source voltage of the high-side FET, the HB node is V
DD
volts above the HS node and the boot diode is reversed biased.
Because the high-side driver circuit is referenced to the HS node,
the HO output is now approximately VHB + VBRIDGE above
ground.
2
0
0
10
20
30
40
50
60
70
80
QG TOTAL GATE CHARGE (nC)
During the low to high transition of the HS node, the boot
capacitor sources the necessary gate charge to fully enhance the
high-side bridge FET gate. After the gate is fully charged, the boot
capacitor no longer sources the charge to the gate but continues
to provide bias current to the high-side driver. It is clear that the
charge of the boot capacitor must be substantially larger than
the required charge of the high-side FET and high-side driver
otherwise the boot voltage will sag excessively. If the boot
capacitor value is too small for the required maximum of on-time
FIGURE 21. TYPICAL GATE CHARGE OF A POWER FET
The following equations calculate the total charge required for
the Period. This equation assumes that all of the parameters are
constant during the period duration. The error is insignificant if
the ripple is small.
FN7670.0
December 23, 2011
11
HIP2122, HIP2123
Q = Q
gate80V
+ Period x (I + V /R + I
)
L is the total parasitic inductance of the low-side FET drain-
source path and di/dt is the rate at which the high-side FET is
turned off. With the increasing power levels of power supplies
and motor, clamping this transient become more and more
significant for the proper operation of the HIP2122/23.
c
HB HO GS gate_leak
C
C
= Q /(Ripple * VDD)
c
boot
boot
= 0.52µF
If the gate to source resistor is removed (R is usually not
GS
needed or recommended), then:
C
= 0.33µF
H O
boot
IN D U C T IV E
L O A D
H S
Typical Application Circuit
Figure 23 is an example of how the HIP2122/23 can be
configured for a half bridge power supply application.
-
+
L O
-
+
Depending on the application, the switching speed of the bridge
FETs can be reduced by adding series connected resistors
between the xHO outputs and the FET gates. Gate-Source
resistors are recommended on the low Side FETs to prevent
unexpected turn-on of the bridge should the bridge voltage be
applied before VDD. Gate-source resistors on the high side FETs
are not usually required if low-side gate-source resistors are
used. If relatively small gate-source resistors are used on the
high-side FETs, be aware that they will load the boot capacitor,
which will then require a larger value for the boot capacitor.
V S S
FIGURE 22. PARASITIC INDUCTANCE CAUSES TRANSIENTS ON HS
NODE
There are several ways of reducing the amplitude of this
transient. If the bridge FETs are turned off more slowly to reduce
di/dt, the amplitude will be reduced but at the expense of more
switching losses in the FETs. Careful PCB design will also reduce
the value of the parasitic inductance. However, these two
solutions by themselves may not be sufficient. Figure 22
illustrates a simple method for clamping the negative transient.
A fast PN junction, 1A diode is connected between xHS and VSS
as shown. It is important that this diode be placed as close as
possible to the xHS and VSS pins to minimize the parasitic
inductance of this current path. Because this clamping diode is
essentially in parallel with the body diode of the low side FET, a
small value resistor is necessary to limit current when the body
diode of the low side bridge FET is conducting during the dead
time.
Transients on HS Node
An important operating condition that is frequently overlooked by
designers is the negative transient on the xHS pins that occurs
when the high side bridge FET turns off. The Absolute Maximum
transient allowed on the xHS pin is -6V but it is wise to minimize
the amplitude to lower levels. This transient is the result of the
parasitic inductance of the low-side drain-source conductor on
the PCB. Even the parasitic inductance of the low-side FET
contributes to this transient.
Please note that a similar transient with a positive polarity occurs
when the low-side FET turns off. This is less frequently a problem
because xHS node is floating up toward the bridge bias voltage.
The Absolute Max voltage rating for the xHS node does need to
be observed when the positive transient occurs.
When the high-side bridge FET turns off (see Figure 22), because
of the inductive characteristics of the load, the current that was
flowing in the high-side FET (blue) must rapidly commutate to
flow through the low side FET (red). The amplitude of the
negative transient impressed on the xHS node is (di/dt x L) where
8-15V
100V MAX
VDD
HB
HI
DRIVER
HO
PWM
PWM
CONTROLLER
HS
LO
EN
LO
DRIVER
RDT
VSS
FIGURE 23. TYPICAL HALF BRIDGE APPLICATION
FN7670.0
December 23, 2011
12
HIP2122, HIP2123
• When practical, minimize impedances in low level signal
circuits; the noise, magnetically induced on a 10k resistor, is
10x larger than the noise on a 1k resistor.
Power Dissipation
The dissipation of the HIP2122/23 is dominated by the gate
charge required by the driven bridge FETs and the switching
frequency. The internal bias and boot diode also contribute to the
total dissipation but these losses are usually insignificant
compared to the gate charge losses.
• Be aware of magnetic fields emanating from transformers and
inductors. Core gaps in these structures are especially bad for
emitting flux.
• If you must have traces close to magnetic devices, align the
traces so that they are parallel to the flux lines.
The calculation of the power dissipation of the HIP2122/23 is
very simple.
• The use of low inductance components, such as chip resistors
and chip capacitors is recommended.
Gate Power (for the HO and LO outputs):
P
= 4 x Q x Freq x VDD
gate
gate
where
is the charge of the driven bridge FET at VDD, and
• Use decoupling capacitors to reduce the influence of parasitic
inductors. To be effective, these capacitors must also have the
shortest possible lead lengths. If vias are used, connect several
paralleled vias to reduce the inductance of the vias.
Q
gate
Freq is the switching frequency.
• It may be necessary to add resistance to dampen resonating
parasitic circuits. The most likely circuit will be the HO and LO
outputs. In PCB designs with long leads on the LI and HI inputs,
it may also be necessary to add series resistors with the LI and
HI inputs.
Boot diode dissipation:
I
= Q
gate
x Freq
x 0.6V
diode_avg
= I
P
diode diode_avg
where 0.6V is the diode conduction voltage
• Keep high dv/dt nodes away from low level circuits. Guard
banding can be used to shunt away dv/dt injected currents
from sensitive circuits. This is especially true for the PWM
control circuits.
Bias current:
P
= I
x VDD
bias
bias
where I
switching frequency
is the internal bias current of the HIP2122/23 at the
• Avoid having a signal ground plane under a high dv/dt circuit.
This will inject high di/dt currents into the signal ground paths.
bias
Total Power Dissipation:
• Do power dissipation and voltage drop calculations of the
power traces. Most PCB/CAD programs have built in tools for
calculation of trace resistance.
P
= P
gate
+ P
+ P
diode bias
total
Operating Temperatures:
T = P x θ + T
• Large power components (Power FETs, Electrolytic capacitors,
power resistors, etc.) will have internal parasitic inductance,
which cannot be eliminated. This must be accounted for in the
PCB layout and circuit design.
j
total
JA
amb
where T is the junction temperature at the operating air
j
temperature, T
, in the vicinity of the part.
x θ + T
JC PCB
amb
• If you simulate your circuits, consider including parasitic
components.
T = P
j
total
where T is the junction temperature with the operating
j
temperature of the PCB, T
soldered.
, measured where the EPAD is
PCB
EPAD Design Considerations
The thermal pad of the HIP2122/23 is electrically isolated. It’s
primary function is to provide heat sinking for the IC. It is
PC Board Layout
The AC performance of the HIP2122/23 depends significantly on
the design of the PC board. The following layout design
guidelines are recommended to achieve optimum performance
from the HIP2122/23:
recommended to tie the EPAD to V (GND).
SS
The following is an example of how to use vias to remove heat
from the IC substrate.
• Understand well how power currents flow. The high amplitude
di/dt currents of the bridge FETs will induce significant voltage
transients on the associated traces.
• Keep power loops as short as possible by paralleling the
source and return traces.
• Use planes where practical; they’re usually more effective than
parallel traces.
• Planes can also be non-grounded nodes.
• Avoid paralleling high di/dt traces with low level signal lines.
High di/dt will induce currents in the low level signal lines.
FN7670.0
December 23, 2011
13
HIP2122, HIP2123
Depending on the amount of power dissipated by the HIP2122/23,
it may be necessary, to connect the EPAD to one or more ground
plane layers. A via array, within the area of the EPAD, will conduct
heat from the EPAD to the GND plane on the bottom layer. If inner
PCB layers are available, it is also be desirable to connect these
additional layers with the plated-through vias.
EPAD
GND
PLANE
EPAD
GND
PLANE
The number of vias and the size of the GND planes required for
adequate heatsinking is determined by the power dissipated by
the HIP2122/23, the air flow, and the maximum temperature of
the air around the IC.
BOTTOM
LAYER
COMPONENT
LAYER
It is important that the vias have a low thermal resistance for
efficient heat transfer. Do not use “thermal relief” patterns to
connect the vias.
FIGURE 24. TYPICAL PCB PATTERN FOR THERMAL VIAS
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
FN7670.0
CHANGE
December 23, 2011
Initial Release
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: HIP2122, HIP2123
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
FITs are available from our website at: http://rel.intersil.com/reports/sear
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7670.0
December 23, 2011
14
HIP2122, HIP2123
Package Outline Drawing
L9.4x4
9 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 1/10
3.2 REF
4.00
A
PIN #1 INDEX AREA
6
6X 0.80 BSC
B
4
1
9X 0 . 40 ± 0.100
6
PIN 1
INDEX AREA
4.00
2.20
1.2 REF
0.15
(4X)
9
5
0.10 M C A B
C
0.05 M
9 X 0.30
4
TOP VIEW
(3.00)
3.00
BOTTOM VIEW
SEE DETAIL "X"
0 .75
(9 X 0.60)
C
0.10
C
BASE PLANE
SEATING PLANE
0.08
C
SIDE VIEW
(3.80)
(2.20)
(1.2)
4
0 . 2 REF
C
0 . 00 MIN.
0 . 05 MAX.
(9X 0.30)
(6X 0.8)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. E-Pad is offset from center.
Tiebar (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN7670.0
December 23, 2011
15
HIP2122, HIP2123
Package Outline Drawing
L10.4x4
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 1/08
3.2 REF
4.00
A
PIN #1 INDEX AREA
6
8X 0.80 BSC
B
5
1
10X 0 . 40
6
PIN 1
INDEX AREA
4.00
2.60
0.15
(4X)
10
6
0.10 M C A B
C
0.05 M
10 X 0.30
4
TOP VIEW
( 3.00 )
3.00
BOTTOM VIEW
SEE DETAIL "X"
0 .75
( 10 X 0.60 )
C
0.10
C
BASE PLANE
SEATING PLANE
0.08
C
SIDE VIEW
( 3.80)
( 2.60)
0 . 2 REF
C
0 . 00 MIN.
0 . 05 MAX.
( 8X 0 . 8 )
( 10X 0 . 30 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN7670.0
December 23, 2011
16
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SI9137DB
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