HIP5060DW [INTERSIL]
Power Control IC Single Chip PowerSupply; 电源控制IC单芯片POWERSUPPLY
| 型号： | HIP5060DW |
| 厂家： | 
Intersil |
| 描述： | Power Control IC Single Chip PowerSupply |
| 文件： | 总6页 (文件大小：609K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIP5060
®
August 1998
File Number 3207.2
Power Control IC Single Chip
PowerSupply
Features
• Single Chip Current Mode Control IC
• 60V, 10A On-Chip DMOS Transistor
• Thermal Protection
• Over-Voltage Protection
• Over-Current Protection
• 1MHz Operation or External Clock
• Synchronization Output
• On-Chip Reference Voltage - 5.1V
• Output Rise and Fall Times ~ 3ns
• Designed for 27V to 45V Operation
The HIP5060 is a complete power control IC, incorporating
both the high power DMOS transistor, CMOS logic and low
level analog circuitry on the same Intelligent Power IC. Both
the standard “Boost” and the “SEPIC” (Single-Ended
Primary Inductance Converter) power supply topologies are
easily implemented with this single control IC.
Special power transistor current sensing circuitry is
incorporated that minimizes losses due to the monitoring
circuitry. Moreover, over-temperature and over-voltage
detection circuitry is incorporated within the IC to monitor the
chip temperature and the actual power supply output
voltage. These circuits can disable the drive to the power
transistor to protect both the transistor and, most
importantly, the load from over-voltage.
Applications
• Single Chip Power Supplies
• Current Mode PWM Applications
• Distributed Power Supplies
• Multiple Output Converters
As a result of the power DMOS transistor’s current and
voltage capability (10A and 60V), power supplies with output
power capability up to 100 watts are possible.
Ordering Information
TEMPERATURE
PART NUMBER
HIP5060DY
RANGE
PACKAGE
37 Pad Chip
Wafer
o
o
0 C to +85 C
o
o
HIP5060DW
0 C to +85 C
Chip
(8) V
DDA
FLTH (37)
VREG (36)
VCMP (35)
PSOK (34)
(9) V+
(10) SLCT
(11) CKIO
(12) DGD1
SHRT (33)
PSEN (32)
TMON (31)
(13) V
(14) V
DDP
DDP
NOTE: Unused pads are for trim and test.
153 mils x 165 mils (3.88mm x 4.19mm)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1
HIP5060
Simplified Block Diagram
4µH
4µH
1.1µF
V
IN
0.1µF
100µF
0.1µF
D
V+
1
µF
4µH
0.88µF
CLOCK
VCMP
AND
CONTROL
LOGIC
GATE
DRIVERS
FLTN
PSOK
SHRT
PSEN
TMON
DGD1
30.1K
S
DG02
0.033µF
VREG
AMP
0.1µF
V
DDP
DDP
V
REFERENCE
0.1µF
VINP
AGND
SFST
CKIO SLCT
V
V
IRF1
IRF0
DDA
DDD
0.1µF
0.1µF
0.1µF
4.02K
TYPICAL SEPIC CONFIGURATION
2
HIP5060
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, V+. . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 45V
DMOS Drain Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 60V
DMOS Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20A
DC Logic Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V
Output Voltage, Logic Outputs . . . . . . . . . . . . . . . . . . . -0.3V to 16V
Input Voltage, Analog and Logic. . . . . . . . . . . . . . . . . . -0.3V to 16V
Thermal Resistance
(Solder Mounted to . . . . . . . . . . . . . . . . . . . . . . . . . 3 C/W Max
0.050” Thick Copper Heat Sink)
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +110 C
(Controlled By Thermal Shutdown Circuit)
θ
JC
o
o
o
o
Operating Junction Temperature Range . . . . . . . . . .0 C to +110 C
o
o
Storage Temperature Range . . . . . . . . . . . . . . . . . -55 C to +150 C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
o
o
Electrical Specifications V+ = 36V, T = 0 C to +110 C; Unless Otherwise Specified
J
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DEVICE PARAMETERS
I+
Supply Current
PSEN = 12V
-
19.5
-
32
mA
V
V
Internal Regulator Output
Voltage
V+ = 15V to 45V, I
OUT
= 10mA
11.0
13.2
DDA
VINP
Reference Voltage
VINP Resistance
I
= 0mA
5.01
-
5.1
5.19
-
V
VINP
R
VINP = 0
900
Ω
VINP
ERROR AMPLIFIERS
|V
IO
|
Input Offset Voltage
(VREG - VINP)
I
= 0mA
-
-
10
mV
VCMP
R
VREG
Input Resistance to GND
VREG Transconductance
VREG = 5.1V
VCMP = 1V to 8V, SFST = 11V
-
56
30
-
kΩ
IN
g
(VREG)
15
50
mS
m
I
/(VREG - VINP)
VCMP
g
(SFST)
SFST Transconductance
V
< 4.9V
0.8
-
6
mS
m
SFST
I
/(VREG - SFST)
VCMP
I
I
Maximum Source Current
Maximum Sink Current
Over-Voltage Threshold
VREG = 4.95V, VCMP = 8V
VREG = 5.25V, VCMP = 0.4V
-2.5
0.75
6.2
-
-
-
-0.75
2.5
mA
mA
V
VCMP
VCMP
OVTH
Voltage at VREG for FLTN to be
latched
6.7
CLOCK
fq
Internal Clock Frequency
SLCT = 0V, V
SLCT = 12V
= 12V
0.9
33
1.0
-
1.1
66
MHz
DDD
V
CKIN
External Clock Input Threshold
Voltages
%V
DDD
TH
DMOS TRANSISTORS
o
r
Drain-Source On-State
Resistance
I Drain = 5A, T = +25 C
J
-
-
-
0.13
100
Ω
DS(on)
I
Drain-Source Leakage Current
Drain to Source Voltage = 60V
1
µA
DSS
CURRENT CONTROLLED PWM
|V | VCMP
IO
Buffer Offset Voltage (VCMP -
IRFO = 0mA to -5mA,
VCMP = 0.2V to 7.6V
-
-
-
125
270
mV
mV
V
)
IRFO
V
IRFO
Voltage at IRFO that disables
PWM. This is due to low load
current
100
TH
3
HIP5060
o
o
Electrical Specifications V+ = 36V, T = 0 C to +110 C; Unless Otherwise Specified (Continued)
J
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
CURRENT CONTROLLED PWM (Continued)
I
IRFO
Voltage at IRFO to enable SHRT
output current. This is due to
Regulator Over Current Condi-
tion
7.4
-
8.0
V
TH
I
SHRT Output Current, During
Over-Current
V
= 8.1V
-37
4
-
-17
8
µA
SHRT
IRFO
V
SHRT
Threshold voltage on SHRT to
set FLTN latch
6
V
TH
I
I
(DMOS
)/I
DRAIN IRFI
∆I (DMOS
)/∆t = 1A/ms
)/∆t > 1A/µs
3.8
150
-
-
-
4.9
360
-
A/mA
Ω
GAIN
PEAK
DRAIN
DRAIN
R
IRFI Resistance to GND
I
= 2mA
IRFI
IRFI
t
(Note 1)
Current Comparator Response
Time
∆I (DMOS
30
ns
RS
MCPW (Note
1)
Minimum Controllable Pulse
Width
25
50
100
800
ns
MCPI
(Note 1)
Minimum Controllable DMOS
Peak Current
200
400
mA
START-UP
V+
Rising V+ Power-On Reset
Voltage
22
-
-
27
-
V
V
V+
V+
Falling V+ Power-Off Set
Voltage
15
V+ Power-On Hysteresis
9
-
-
12
V
V
V
TH
PSEN
Voltage at PSEN to Enable
Supply
0.8
2.0
r
Internal Pull-Up Resistance, to
5.1V
-
20
-
KΩ
PSEN
I
Soft-Start Charging Current
V
= 0V to 10V
-1.0
-1
-0.7
-
-0.4
1
µA
µA
SFST
SFST
I
PSOK High-State Leakage
Current
SFST = 0V, PSOK = 12V
PSOK
V
PSOK Low-State Voltage
SFST = 11V, I
PSOK
= 1mA
-
-
-
0.4
11
V
V
PSOK
V
TH
SFST
PSOK Threshold, Rising V
9.4
SFST
THERMAL MONITOR
o
TEMP
(Note 1)
Substrate Temperature for
Thermal Monitor to Trip
TMON pin open
105
-
135
C
NOTE:
1. Determined by design, not a measured parameter.
4
HIP5060
Pin Descriptions
PAD NUMBER
DESIGNATION
DESCRIPTION
1
2
3
AGND
VINP
Analog ground.
Internal 5.1V reference.
SFST
Controls the rate of rise of the output voltage. Time is determined by an internal 0.7µA current
source and an external capacitor.
4
IRFO
A resistor placed between this pad and IRFI converts the VCMP signal to a current for the current
sense comparator. The maximum current is set by the value of the resistor, according to the
equation: I
= 32/R. Where R is the value of the external resistor in KΩ and must be greater
PEAK
than 1.5KΩ but less than 10KΩ. For example, if the resistor chosen is 1.8K, the peak current will
be 17.8A. This assumes VCMP is 7.3V. Maximum output current should be kept below 20A.
5
6
7
8
9
IRFI
See IRFO
DGD2
Ground of the DMOS gate driver. This pad is used for bypassing.
Voltage input for the chip’s digital circuits. This pad also allows decoupling of this supply.
This is the analog supply and internal 12V regulator output.
V
V
DDD
DDA
V+
This is the main supply voltage input pad to the regulator IC. Because of the high peak currents
this pad must be well bypassed with at least a 0.7µF capacitor and may be composed of seven,
single 0.1µF chip capacitors.
10
11
SLCT
This pad provides for the option of using either internal 1MHz operation of for an external clock.
Floating or grounding this pad will place the internal clock at the CKIO pad. Returning this termi-
nal to V
or 12V will allow application of an external clock to the IC via the CKIO pad. There
DDD
is an internal 50K pull down
CKIO
Clock output when SLCT is floated or grounded. External clock input when SLCT is returned to
12V.
12
DGD1
This pad is the return for the digital supply.
13 & 14
V
These pads are used to decouple the high current pulses to the output driver transistors. The
capacitor should be at least a 0.1µF chip capacitor placed close to this pad and the DMOS
source pads.
DDP
15, 16, 19, 20,
23, 24, 27, 28
S
D
Source pads of the DMOS power transistor.
17, 18, 21, 22,
25, 26, 29, 30
Drain pads of the DMOS power transistor.
31
TMON
This is the thermal shut down pad than can be used to disable the thermal shutdown circuit. By
returning this pad to 12V the function is disabled. Returning this pad to ground will put the IC into
the thermal shutdown state. Normally, this pad is left floating. Thermal shutdown occurs at a
o
nominal junction temperature of +125 C.
32
PSEN
This terminal is provided to activate the converter. This terminal may be left open or returned to
5V for normal operation. When the input is low, the DMOS driver is disabled.
33
34
35
SHRT
PSOK
VCMP
25µA is internally applied to this node when there is an over-current condition.
This pad provides a delayed positive indication when the supply is enabled.
Output of the transconductance amplifier. This node is used for both gain and frequency com-
pensation of the loop.
36
37
VREG
FLTN
Input to the transconductance error amplifier is available on this pad. The other input is internally
connected to the 5.1V reference, VINP, Pad 2.
This is an open drain output that remains low when V+ is too low for proper operation. This node
and PSEN are useful in multiple converter configurations. This pad will be latched low when over-
temperature, over-voltage or over-current is experienced.
5
HIP5060
Functional Block Diagram
CKIO
V
SLCT
V
DDD
DDA
12V
REGULATOR
BIAS
CIRCUITS
V+
V
DDA
1MHz
CLOCK
BAND GAP
REFERENCE
REGULATOR
VREF =
5.1V
12V
REGULATOR
50K
VREF
V+
MONITOR
MULTIPLEXER
POWER
SUPPLY
ENABLE
V
DDP
20KΩ
+
V
PSEN
V
DDP
DDP
-
VREF
V
DDA
POWER
360KΩ
140KΩ
PSOK
SFST
VINP
SUPPLY
OK
DRAIN
0.7µA
S
GATE
DRIVERS
FLIP-FLOP
R
Q
VREF
900Ω
FAST RESET
gm
AMP
LOW
LOAD
CONTROL
+
-
+
-
CURRENT
MONITOR-
ING AMP
AND
BLANKING
LOGIC
SOURCE
VREG
11.3KΩ
VREF
98KΩ
4KΩ
FLTN
OVER
VOLTAGE
-
+
45KΩ
VREF
THERMAL
MONITOR
TMON
SHRT
+
-
SHORT
CIRCUIT
VREF
26KΩ
-
+
13KΩ
DGD2
IRFI
AGND
IRF0
VCMP
DGD1
6
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