HIP6004DCB_技术文档

HIP6004D

TM

Data Sheet

April 2000

File Number 4855

Buck and Synchronous-Rectiﬁer (PWM)

Controller and Output Voltage Monitor

Features

• Drives Two N-Channel MOSFETs

• Operates from +5V or +12V Input

The HIP6004D provides complete control and protection for

a DC-DC converter optimized for high-performance

microprocessor applications. It is designed to drive two

N-Channel MOSFETs in a synchronous-rectiﬁed buck

topology. The HIP6004D integrates all of the control, output

adjustment, monitoring and protection functions into a single

package.

• Simple Single-Loop Control Design

- Voltage-Mode PWM Control

• Fast Transient Response

- High-Bandwidth Error Ampliﬁer

- Full 0% to 100% Duty Ratio

The output voltage of the converter is easily adjusted and

precisely regulated. The HIP6004D includes a fully TTL-

compatible 5-input digital-to-analog converter (DAC) that

• Excellent Output Voltage Regulation

- ±1% Over Line Voltage and Temperature

• TTL-Compatible 5-Bit Digital-to-Analog Output

Voltage Selection

adjusts the output voltage from 1.1V

to 1.85V

in 25mV

DC

increments steps. The precision reference and voltage-mode

regulator hold the selected output voltage to within ±1% over

temperature and line voltage variations.

- 25mV Binary Steps . . . . . . . . . 1.100V

to 1.850V

DC

• Power-Good Output Voltage Monitor

The HIP6004D provides simple, single feedback loop,

voltage-mode control with fast transient response. It includes

a 200kHz free-running triangle-wave oscillator that is

adjustable from below 50kHz to over 1MHz. The error

ampliﬁer features a 15MHz gain-bandwidth product and

6V/µs slew rate which enables high converter bandwidth for

fast transient performance. The resulting PWM duty ratio

ranges from 0% to 100%.

• Over-Voltage and Over-Current Fault Monitors

- Does Not Require Extra Current Sensing Element,

Uses MOSFET’s r

DS(ON)

• Small Converter Size

- Constant Frequency Operation

- 200kHz Free-Running Oscillator Programmable from

50kHz to over 1MHz

The HIP6004D monitors the output voltage with a window

comparator that tracks the DAC output and issues a Power

Good signal when the output is within ±10%. The HIP6004D

protects against over-current and overvoltage conditions by

inhibiting PWM operation. Additional built-in overvoltage

protection triggers an external SCR to crowbar the input

supply. The HIP6004D monitors the current by using the

Applications

• Power Supply for K7™, and Other Microprocessors

•

High-Power DC-DC Regulators

Low-Voltage Distributed Power Supplies

Pinout

r

of the upper MOSFET which eliminates the need for

DS(ON)

HIP6004D

(SOIC)

a current sensing resistor.

TOP VIEW

Ordering Information

1

2

3

4

5

6

7

8

9

RT

VSEN

OCSET

SS

20

19

18

OVP

VCC

TEMP.

PKG.

NO.

o

PART NUMBER RANGE ( C)

PACKAGE

20 Ld SOIC

VID0

17 LGATE

16 PGND

HIP6004DCB

0 to 70

M20.3

VID1

NOTE: When ordering, use the entire part number. Add the sufﬁx T

to obtain the part in tape and reel, e.g., HIP6004DCB-T.

VID2

BOOT

15

VID3

14 UGATE

13 PHASE

VID4

12

COMP

PGOOD

FB 10

11 GND

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

K7™ is a trademark of Advanced Micro Devices, Inc.

HIP6004D

Typical Application

+12V

VCC

V

= +5V OR +12V

IN

HIP6004D

PGOOD

OCSET

EN

MONITOR AND

PROTECTION

SS

OVP

BOOT

RT

OSC

UGATE

PHASE

VID0

VID1

VID2

VID3

VID4

+V

OUT

D/A

LGATE

PGND

-

+

-

FB

COMP

VSEN

GND

Block Diagram

VCC

VSEN

POWER-ON

110%

RESET (POR)

+

-

PGOOD

90%

+

-

OVER-

VOLTAGE

10µA

115%

+

OVP

SS

-

SOFT-

START

+

-

OCSET

OVER-

CURRENT

BOOT

REFERENCE

200µA

4V

UGATE

PHASE

PWM

VID0

VID1

VID2

VID3

VID4

TTL D/A

CONVERTER

(DAC)

COMPARATOR

DACOUT

GATE

CONTROL

LOGIC

INHIBIT

PWM

+

-

+

-

ERROR

AMP

LGATE

PGND

GND

FB

COMP

RT

OSCILLATOR

2

HIP6004D

Absolute Maximum Ratings

Thermal Information

o

Supply Voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15V

Thermal Resistance (Typical, Note 1)

θ_JA( C/W)

CC

Boot Voltage, V

Input, Output or I/O Voltage . . . . . . . . . . . .GND -0.3V to V

ESD Classiﬁcation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 2

- V

. . . . . . . . . . . . . . . . . . . . . . . . +15V

BOOT

PHASE

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SOIC Package (with 3in of Copper) . . . . . . . . . . . .

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150 C

Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C

(SOIC - Lead Tips Only)

110

86

2

+0.3V

CC

o

Operating Conditions

o

Supply Voltage, V

CC

Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0 C to 70 C

. . . . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%

o

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. θ is measured with the component mounted on an evaluation PC board in free air.

JA

Electrical Speciﬁcations Recommended Operating Conditions, Unless Otherwise Noted

PARAMETER

VCC SUPPLY CURRENT

Nominal Supply

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

I

UGATE and LGATE Open

-

5

-

mA

CC

POWER-ON RESET

Rising VCC Threshold

Falling VCC Threshold

V

= 4.5V

-

8.2

-

10.4

V

OCSET

= 4.5V

-

OCSET

Rising V

OCSET

Threshold

1.26

OSCILLATOR

Free Running Frequency

Total Variation

RT = OPEN

185

-15

-

200

-

215

+15

-

kHz

%

6kΩ < RT to GND < 200kΩ

RT = Open

Ramp Amplitude

∆V

OSC

1.9

V

P-P

REFERENCE AND DAC

DAC (VID0-VID4) Input Low Voltage

DAC (VID0-VID4) Input High Voltage

DACOUT Voltage Accuracy

ERROR AMPLIFIER

DC Gain

-

0.8

-

V

2.0

-1.0

+1.0

%

-

88

15

6

-

dB

Gain-Bandwidth Product

Slew Rate

GBWP

SR

MHz

V/µs

COMP = 10pF

GATE DRIVERS

Upper Gate Source

I

V

- V

= 12V, V = 6V

UGATE

350

500

5.5

-

10

-

mA

Ω

UGATE

BOOT

PHASE

Upper Gate Sink

R

I

= 0.3A

-

300

-

UGATE

LGATE

Lower Gate Source

I

V

= 12V, V

= 6V

450

3.5

mA

Ω

CC

LGATE

Lower Gate Sink

R

I

= 0.3A

6.5

LGATE

PROTECTION

Over-Voltage Trip (VSEN/DACOUT)

OCSET Current Source

OVP Sourcing Current

Soft Start Current

-

170

60

-

115

200

-

120

%

µA

mA

µA

I

V

= 4.5V

230

OCSET

DC

I

= 5.5V, V

= 0V

-

OVP

SEN

OVP

I

10

SS

POWER GOOD

Upper Threshold (VSEN/DACOUT)

Lower Threshold (VSEN/DACOUT)

Hysteresis (VSEN/DACOUT)

PGOOD Voltage Low

VSEN Rising

VSEN Falling

106

-

111

%

V

89

-

94

-

Upper and Lower Threshold

= -5mA

2

V

I

-

0.5

-

PGOOD

3

HIP6004D

Typical Performance Curves

80

70

60

50

40

C

= 3300pF

GATE

1000

R

PULLUP

TO +12V

T

C

= C = C

LOWER GATE

UPPER

100

10

C

= 1000pF

GATE

30

20

10

0

R

PULLDOWN TO V

SS

T

C

= 10pF

800

GATE

10

100

SWITCHING FREQUENCY (kHz)

1000

100 200

300

400

500

600

700

900 1000

SWITCHING FREQUENCY (kHz)

FIGURE 1. R RESISTANCE vs FREQUENCY

FIGURE 2. BIAS SUPPLY CURRENT vs FREQUENCY

T

(DACOUT). The level of DACOUT sets the converter output

voltage. It also sets the PGOOD and OVP thresholds. Table

1 speciﬁes DACOUT for the all combinations of DAC inputs.

Functional Pin Descriptions

1

2

3

4

5

6

7

8

9

RT

VSEN

OCSET

SS

20

19

OVP

COMP (Pin 9) and FB (Pin 10)

18 VCC

COMP and FB are the available external pins of the error

ampliﬁer. The FB pin is the inverting input of the error

ampliﬁer and the COMP pin is the error ampliﬁer output.

These pins are used to compensate the voltage-control

feedback loop of the converter.

VID0

17 LGATE

16 PGND

15 BOOT

14 UGATE

13 PHASE

VID1

VID2

VID3

VID4

GND (Pin 11)

12

COMP

PGOOD

Signal ground for the IC. All voltage levels are measured with

respect to this pin.

FB 10

11 GND

VSEN (Pin 1)

PGOOD (Pin 12)

This pin is connected to the converter’s output voltage. The

PGOOD and OVP comparator circuits use this signal to

report output voltage status and for overvoltage protection.

PGOOD is an open collector output used to indicate the

status of the converter output voltage. This pin is pulled low

when the converter output is not within ±10% of the

DACOUT reference voltage. Exception to this behavior is

the ‘11111’ VID pin combination which disables the

converter; in this case PGOOD asserts a high level.

OCSET (Pin 2)

Connect a resistor (R

OCSET

) from this pin to the drain of the

upper MOSFET. R

, an internal 200µA current source

OCSET

(I

), and the upper MOSFET on-resistance (r

OCS

) set

PHASE (Pin 13)

DS(ON)

the converter over-current (OC) trip point according to the

following equation:

Connect the PHASE pin to the upper MOSFET source. This

pin is used to monitor the voltage drop across the MOSFET

for over-current protection. This pin also provides the return

path for the upper gate drive.

I

x R

OCSET

I

= ----------------------------------------------------

PEAK

r

DS(ON)

UGATE (Pin 14)

An over-current trip cycles the soft-start function.

Connect UGATE to the upper MOSFET gate. This pin

provides the gate drive for the upper MOSFET.

SS (Pin 3)

Connect a capacitor from this pin to ground. This capacitor,

along with an internal 10µA current source, sets the soft-

start interval of the converter.

BOOT (Pin 15)

This pin provides bias voltage to the upper MOSFET driver.

A bootstrap circuit may be used to create a BOOT voltage

suitable to drive a standard N-Channel MOSFET.

VID0-4 (Pins 4-8)

VID0-4 are the input pins to the 5-bit DAC. The states of

these ﬁve pins program the internal voltage reference

4

HIP6004D

increasing width that charge the output capacitor(s). This

PGND (Pin 16)

interval of increasing pulse width continues to t . With sufficient

output voltage, the clamp on the reference input controls the

This is the power ground connection. Tie the lower MOSFET

source to this pin.

2

output voltage. This is the interval between t and t in Figure 3.

2

3

LGATE (Pin 17)

Connect LGATE to the lower MOSFET gate. This pin

provides the gate drive for the lower MOSFET.

At t the SS voltage exceeds the DACOUT voltage and the

3

output voltage is in regulation. This method provides a rapid

and controlled output voltage rise. The PGOOD signal toggles

‘high’ when the output voltage (VSEN pin) is within ±10% of

DACOUT. The 2% hysteresis built into the power good

comparators prevents PGOOD oscillation due to nominal

output voltage ripple.

VCC (Pin 18)

Provide a 12V bias supply for the chip to this pin.

OVP (Pin 19)

The OVP pin can be used to drive an external SCR in the

event of an overvoltage condition. Output rising 15% more

than the DAC-set voltage triggers a high output on this pin

and disables PWM gate drive circuitry.

PGOOD

(2V/DIV.)

0V

RT (Pin 20)

This pin provides oscillator switching frequency adjustment.

SOFT-START

(1V/DIV.)

By placing a resistor (R ) from this pin to GND, the nominal

T

200kHz switching frequency is increased according to the

following equation:

OUTPUT

VOLTAGE

(1V/DIV.)

6

5 x 10

0V

Fs ≈ 200kHz + --------------------

(R to GND)

T

R (kΩ)

T

0V

t

3

1

Conversely, connecting a pull-up resistor (R ) from this pin

2

T

to V

reduces the switching frequency according to the

TIME (5ms/DIV.)

CC

following equation:

FIGURE 3. SOFT START INTERVAL

7

4 x 10

Fs ≈ 200kHz – --------------------

(R to 12V)

Over-Current Protection

T

R (kΩ)

T

The over-current function protects the converter from a

shorted output by using the upper MOSFET’s on-resistance,

Functional Description

r

to monitor the current. This method enhances the

DS(ON)

Initialization

converter’s efficiency and reduces cost by eliminating a

current sensing resistor.

The HIP6004D automatically initializes upon receipt of power.

Special sequencing of the input supplies is not necessary. The

Power-On Reset (POR) function continually monitors the input

supply voltages. The POR monitors the bias voltage at the VCC

4V

2V

0V

pin and the input voltage (V ) on the OCSET pin. The level on

IN

OCSET is equal to V less a fixed voltage drop (see over-

IN

current protection). The POR function initiates soft start

operation after both input supply voltages exceed their POR

thresholds. For operation with a single +12V power source, V

15A

10A

IN

and V are equivalent and the +12V power source must

CC

exceed the rising VCC threshold before POR initiates operation.

5A

0A

Soft Start

The POR function initiates the soft start sequence. An internal

10µA current source charges an external capacitor (C ) on

SS

the SS pin to 4V. Soft start clamps the error amplifier output

(COMP pin) and reference input (+ terminal of error amp) to the

SS pin voltage. Figure 3 shows the soft start interval with

TIME (20ms/DIV.)

FIGURE 4. OVER-CURRENT OPERATION

C

= 0.1µF. Initially the clamp on the error amplifier (COMP

The over-current function cycles the soft-start function in a

SS

pin) controls the converter’s output voltage. At t in Figure 3, the

hiccup mode to provide fault protection. A resistor (R

)

1

OCSET

SS voltage reaches the valley of the oscillator’s triangle wave.

The oscillator’s triangular waveform is compared to the ramping

error amplifier voltage. This generates PHASE pulses of

programs the over-current trip level. An internal 200µA current

sink develops a voltage across R that is referenced to

OCSET

. When the voltage across the upper MOSFET (also

V

IN

5

HIP6004D

referenced to V ) exceeds the voltage across R

, the

over-current function initiates a soft-start sequence. The soft-

Output Voltage Program

IN OCSET

The output voltage of a HIP6004D converter is programmed

to discrete levels between 1.100V

start function discharges C with a 10µA current sink and

SS

and 1.850V . The

DC

inhibits PWM operation. The soft-start function recharges

voltage identification (VID) pins program an internal voltage

reference (DACOUT) with a TTL-compatible 5-bit digital-to-

analog converter (DAC). The level of DACOUT also sets the

PGOOD and OVP thresholds. Table 1 specifies the DACOUT

voltage for the 32 different combinations of connections on the

VID pins. The output voltage should not be adjusted while the

converter is delivering power. Remove input power before

changing the output voltage. Adjusting the output voltage

during operation could toggle the PGOOD signal and exercise

the overvoltage protection.

C

, and PWM operation resumes with the error amplifier

SS

clamped to the SS voltage. Should an overload occur while

recharging C , the soft start function inhibits PWM operation

SS

while fully charging C to 4V to complete its cycle. Figure 4

SS

shows this operation with an overload condition. Note that the

inductor current increases to over 15A during the C

charging interval and causes an over-current trip. The

converter dissipates very little power with this method. The

measured input power for the conditions of Figure 4 is 2.5W.

SS

The over-current function will trip at a peak inductor current

‘11111’ VID pin combination resulting in a 0V output setting

activates the Power-On Reset function and disables the gate

drives circuitry. For this specific VID combination, though,

PGOOD asserts a high level. This unusual behavior has been

implemented in order to allow for operation in dual-

(I

determined by:

PEAK)

I

x R

OCSET

I

= ----------------------------------------------------

PEAK

r

DS(ON)

microprocessor systems where AND-ing of the PGOOD

signals from two individual power converters is implemented.

where I

is the internal OCSET current source (200µA

OCSET

typical). The OC trip point varies mainly due to the

MOSFET’s r variations. To avoid over-current tripping

DS(ON)

Application Guidelines

in the normal operating load range, ﬁnd the R

resistor

OCSET

from the equation above with:

Layout Considerations

As in any high frequency switching converter, layout is very

important. Switching current from one power device to another

can generate voltage transients across the impedances of the

interconnecting bond wires and circuit traces. These

interconnecting impedances should be minimized by using

wide, short printed circuit traces. The critical components

should be located as close together as possible, using ground

plane construction or single point grounding.

1. The maximum r

2. The minimum I

at the highest junction temperature.

from the speciﬁcation table.

DS(ON)

OCSET

I

> I

+ (∆I) ⁄ 2

,

OUT(MAX)

3. Determine I

for

PEAK

where ∆I is the output inductor ripple current.

For an equation for the ripple current see the section under

component guidelines titled ‘Output Inductor Selection’.

A small ceramic capacitor should be placed in parallel with

R

to smooth the voltage across R in the

OCSET

presence of switching noise on the input voltage.

TABLE 1. OUTPUT VOLTAGE PROGRAM

PIN NAME

NOMINAL OUTPUT

VOLTAGE DACOUT

NOMINAL OUTPUT

VOLTAGE DACOUT

VID4

1

VID3

1

VID2

1

VID1

1

VID0

1

VID4

0

VID3

1

VID2

1

VID1

1

VID0

1

0

1.475

1.500

1.525

1.550

1.575

1.600

1.625

1.650

1.675

1.700

1.725

1.750

1.775

1.800

1.825

1.850

1

0

1.100

0

1

0

1

0

1

1.125

0

1

0

1

0

1.150

0

1

0

1

0

1

1.175

0

1

0

1

0

1

0

1.200

0

1

0

1

0

1

0

1

1.225

0

1

0

1

0

1.250

0

1

0

1

0

1

1.275

0

1

0

1

0

1.300

0

1

0

1

0

1

0

1

1.325

0

1

0

1

0

1

0

1.350

0

1

0

1

0

1

1.375

0

1

0

1

0

1.400

0

1

0

1

0

1

1.425

0

1

0

1.450

0

NOTE: 0 = connected to GND or V , 1 = connected to V

SS

through pull-up resistors.

DD

6

HIP6004D

V

IN

DRIVER

V

OSC

IN

PWM

L

O

COMPARATOR

V

OUT

HIP6004D

-

PHASE

+

∆V

C

O

OSC

UGATE

Q

1

L

O

V

OUT

PHASE

ESR

(PARASITIC)

Z

FB

C

IN

2

C

LGATE

PGND

O

V

E/A

D

2

Z

-

IN

+

REFERENCE

ERROR

AMP

RETURN

FIGURE 5. PRINTED CIRCUIT BOARD POWER AND

GROUND PLANES OR ISLANDS

DETAILED COMPENSATION COMPONENTS

Z

FB

V

OUT

C

2

Z

IN

Figure 5 shows the critical power components of the converter.

To minimize the voltage overshoot the interconnecting wires

indicated by heavy lines should be part of ground or power

plane in a printed circuit board. The components shown in

Figure 5 should be located as close together as possible.

C

R

3

1

3

2

R

1

COMP

FB

-

+

Please note that the capacitors C and C each represent

IN

O

numerous physical capacitors. Locate the HIP6004D within 3

HIP6004D

inches of the MOSFETs, Q and Q . The circuit traces for the

1

2

DACOUT

MOSFETs’ gate and source connections from the HIP6004D

must be sized to handle up to 1A peak current.

FIGURE 7. VOLTAGE-MODE BUCK CONVERTER

COMPENSATION DESIGN

Figure 6 shows the circuit traces that require additional

layout consideration. Use single point and ground plane

construction for the circuits shown. Minimize any leakage

The PWM wave is smoothed by the output filter (L and C ).

O

The modulator transfer function is the small-signal transfer

function of V /V . This function is dominated by a DC

current paths on the SS pin and locate the capacitor, C

SS

OUT E/A

Gain and the output ﬁlter (L and C ), with a double pole

close to the SS pin because the internal current source is

O

only 10µA. Provide local V

decoupling between VCC and

break frequency at F and a zero at F

. The DC Gain of

CC

LC

ESR

GND pins. Locate the capacitor, C

to the BOOT and PHASE pins.

as close as practical

the modulator is simply the input voltage (V ) divided by the

BOOT

IN

peak-to-peak oscillator voltage ∆V

OSC

.

Modulator Break Frequency Equations

+V

IN

BOOT

D

1

Q

1

L

O

C

F

= ------------------------------------------

F

= -------------------------------------------

BOOT

LC

ESR

2π x ESR x C

V

2π x

L

x C

OUT

O

PHASE

VCC

HIP6004D

The compensation network consists of the error ampliﬁer

(internal to the HIP6004D) and the impedance networks Z

C

O

+12V

SS

Q

2

IN

and Z . The goal of the compensation network is to provide

a closed loop transfer function with the highest 0dB crossing

FB

C

VCC

C

SS

GND

frequency (f

) and adequate phase margin. Phase margin

and

0dB

is the difference between the closed loop phase at f

0dB

180 degrees. The equations below relate the compensation

network’s poles, zeros and gain to the components (R , R ,

FIGURE 6. PRINTED CIRCUIT BOARD SMALL SIGNAL

LAYOUT GUIDELINES

1

2

R , C , C , and C ) in Figure 7. Use these guidelines for

3

1

2

3

locating the poles and zeros of the compensation network:

Feedback Compensation

1. Pick Gain (R /R ) for desired converter bandwidth.

2

1

Figure 7 highlights the voltage-mode control loop for a

synchronous-rectified buck converter. The output voltage

(V ) is regulated to the Reference voltage level. The

ST

2. Place 1 Zero Below Filter’s Double Pole (~75% F ).

LC

ND

ST

3. Place 2

Zero at Filter’s Double Pole.

OUT

4. Place 1 Pole at the ESR Zero.

ND

error amplifier (Error Amp) output (V ) is compared with

5. Place 2

Pole at Half the Switching Frequency.

E/A

the oscillator (OSC) triangular wave to provide a pulse-

6. Check Gain against Error Ampliﬁer’s Open-Loop Gain.

7. Estimate Phase Margin - Repeat if Necessary.

width modulated (PWM) wave with an amplitude of V at

IN

the PHASE node.

7

HIP6004D

Modern microprocessors produce transient load rates above

Compensation Break Frequency Equations

1A/ns. High frequency capacitors initially supply the transient

and slow the current load rate seen by the bulk capacitors.

The bulk filter capacitor values are generally determined by

the ESR (Effective Series Resistance) and voltage rating

requirements rather than actual capacitance requirements.

1

F

= ------------------------------------

2π x R x C

F

= --------------------------------------------------------

Z1

P1

C

x C

2

1

2

---------------------

x

2π x R

2

C

+ C

2

1

F

= ------------------------------------------------------

2π x (R + R ) x C

F

= ------------------------------------

2π x R x C

3

Z2

P2

1

3

High frequency decoupling capacitors should be placed as

close to the power pins of the load as physically possible. Be

careful not to add inductance in the circuit board wiring that

could cancel the usefulness of these low inductance

components. Consult with the manufacturer of the load on

speciﬁc decoupling requirements.

Figure 8 shows an asymptotic plot of the DC-DC converter’s

gain vs frequency. The actual Modulator Gain has a high gain

peak due to the high Q factor of the output filter and is not

shown in Figure 8. Using the above guidelines should give a

Compensation Gain similar to the curve plotted. The open

loop error amplifier gain bounds the compensation gain.

Use only specialized low-ESR capacitors intended for

switching-regulator applications for the bulk capacitors. The

bulk capacitor’s ESR will determine the output ripple voltage

and the initial voltage drop after a high slew-rate transient. An

aluminum electrolytic capacitor’s ESR value is related to the

case size with lower ESR available in larger case sizes.

However, the Equivalent Series Inductance (ESL) of these

capacitors increases with case size and can reduce the

usefulness of the capacitor to high slew-rate transient loading.

Unfortunately, ESL is not a specified parameter. Work with

your capacitor supplier and measure the capacitor’s

Check the compensation gain at F with the capabilities of

P2

the error amplifier. The Closed Loop Gain is constructed on

the log-log graph of Figure 8 by adding the Modulator Gain (in

dB) to the Compensation Gain (in dB). This is equivalent to

multiplying the modulator transfer function to the

compensation transfer function and plotting the gain.

The compensation gain uses external impedance networks

Z

and Z to provide a stable, high bandwidth (BW) overall

FB

IN

loop. A stable control loop has a gain crossing with

-20dB/decade slope and a phase margin greater than 45

degrees. Include worst case component variations when

determining phase margin.

impedance with frequency to select a suitable component. In

most cases, multiple electrolytic capacitors of small case size

perform better than a single large case capacitor.

Output Inductor Selection

The output inductor is selected to meet the output voltage

ripple requirements and minimize the converter’s response

time to the load transient. The inductor value determines the

converter’s ripple current and the ripple voltage is a function

of the ripple current. The ripple voltage and current are

approximated by the following equations:

100

F

P1

F

Z2

Z1

P2

80

60

40

20

0

OPEN LOOP

ERROR AMP GAIN

20LOG

(R /R )

2

1

20LOG

V

- V

OUT

V

OUT

IN

Fs x L

(V /∆V

)

IN OSC

∆I =

∆V = ∆I x ESR

OUT

x

V

MODULATOR

GAIN

IN

COMPENSATION

GAIN

-20

-40

-60

Increasing the value of inductance reduces the ripple current

and voltage. However, the large inductance values reduce

the converter’s response time to a load transient.

CLOSED LOOP

GAIN

F

LC

F

ESR

100K

FREQUENCY (Hz)

10

100

1K

10K

1M

10M

One of the parameters limiting the converter’s response to

a load transient is the time required to change the inductor

current. Given a sufficiently fast control loop design, the

HIP6004D will provide either 0% or 100% duty cycle in

response to a load transient. The response time is the time

required to slew the inductor current from an initial current

value to the transient current level. During this interval the

difference between the inductor current and the transient

current level must be supplied by the output capacitor.

Minimizing the response time can minimize the output

capacitance required.

FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN

Component Selection Guidelines

Output Capacitor Selection

An output capacitor is required to ﬁlter the output and supply

the load transient current. The ﬁltering requirements are a

function of the switching frequency and the ripple current.

The load transient requirements are a function of the slew

rate (di/dt) and the magnitude of the transient load current.

These requirements are generally met with a mix of

capacitors and careful layout.

The response time to a transient is different for the

application of load and the removal of load. The following

8

HIP6004D

equations give the approximate response time interval for

application and removal of a transient load:

voltage-current transitions and do not adequately model power

loss due the reverse-recovery of the lower MOSFET’s body

diode. The gate-charge losses are dissipated by the HIP6004D

and don't heat the MOSFETs. However, large gate-charge

L x I

TRAN

OUT

t

=

t

=

FALL

RISE

V

- V

V

OUT

IN

increases the switching interval, t

which increases the upper

SW

MOSFET switching losses. Ensure that both MOSFETs are

within their maximum junction temperature at high ambient

temperature by calculating the temperature rise according to

package thermal-resistance specifications. A separate heatsink

may be necessary depending upon MOSFET power, package

type, ambient temperature and air flow.

where: I

is the transient load current step, t

is the

TRAN

RISE

response time to the application of load, and t

FALL

response time to the removal of load. With a +5V input

source, the worst case response time can be either at the

application or removal of load and dependent upon the

DACOUT setting. Be sure to check both of these equations

at the minimum and maximum output levels for the worst

case response time. With a +12V input, and output voltage

1

2

Io x V x t

IN SW

x F

S

P

= Io x r

x D +

UPPER

LOWER

DS(ON)

2

P

= Io x r

x (1 - D)

level equal to DACOUT, t

FALL

is the longest response time.

Where: D is the duty cycle = V

OUT

/ V ,

IN

Input Capacitor Selection

t

is the switch ON time, and

SW

Use a mix of input bypass capacitors to control the voltage

overshoot across the MOSFETs. Use small ceramic

capacitors for high frequency decoupling and bulk capacitors

to supply the current needed each time Q turns on. Place the

small ceramic capacitors physically close to the MOSFETs

F

is the switching frequency.

S

Standard-gate MOSFETs are normally recommended for

use with the HIP6004D. However, logic-level gate MOSFETs

can be used under special circumstances. The input voltage,

upper gate drive level, and the MOSFET’s absolute gate-to-

source voltage rating determine whether logic-level

MOSFETs are appropriate.

1

and between the drain of Q and the source of Q .

1

2

The important parameters for the bulk input capacitor are the

voltage rating and the RMS current rating. For reliable

operation, select the bulk capacitor with voltage and current

ratings above the maximum input voltage and largest RMS

current required by the circuit. The capacitor voltage rating

should be at least 1.25 times greater than the maximum

input voltage and a voltage rating of 1.5 times is a

conservative guideline. The RMS current rating requirement

for the input capacitor of a buck regulator is approximately

1/2 the DC load current.

Figure 9 shows the upper gate drive (BOOT pin) supplied by a

bootstrap circuit from V . The boot capacitor, C

CC BOOT

develops a floating supply voltage referenced to the PHASE

pin. This supply is refreshed each cycle to a voltage of V

CC

less the boot diode drop (V ) when the lower MOSFET, Q

D

2

turns on. Logic-level MOSFETs can only be used if the

MOSFET’s absolute gate-to-source voltage rating exceeds

the maximum voltage applied to VCC.

For a through hole design, several electrolytic capacitors may

be needed. For surface mount designs, solid tantalum

capacitors can be used, but caution must be exercised with

regard to the capacitor surge current rating. These capacitors

must be capable of handling the surge-current at power-up.

Some capacitor series available from reputable manufacturers

are surge current tested.

+12V

D

BOOT

+5V OR +12V

+ V

-

D

VCC

BOOT

C

HIP6004D

BOOT

Q1

UGATE

PHASE

MOSFET Selection/Considerations

NOTE:

_G-S≈ V -V

The HIP6004D requires 2 N-Channel power MOSFETs. These

V

CC

D

should be selected based upon r

, gate supply

DS(ON)

Q2

requirements, and thermal management requirements.

D2

LGATE

PGND

-

+

In high-current applications, the MOSFET power dissipation,

package selection and heatsink are the dominant design

factors. The power dissipation includes two loss components;

conduction loss and switching loss. The conduction losses are

the largest component of power dissipation for both the upper

and the lower MOSFETs. These losses are distributed between

the two MOSFETs according to duty factor (see the equations

below). Only the upper MOSFET has switching losses, since

the Schottky rectifier clamps the switching node before the

synchronous rectifier turns on. These equations assume linear

NOTE:

V_G-S≈ V

CC

GND

FIGURE 9. UPPER GATE DRIVE - BOOTSTRAP OPTION

Figure 10 shows the upper gate drive supplied by a direct

connection to V . This option should only be used in

converter systems where the main input voltage is +5V

less. The peak upper gate-to-source voltage is approximately

less the input supply. For +5V main power and +12V

CC

or

DC

V

CC

DC

9

HIP6004D

for the bias, the gate-to-source voltage of Q is 7V. A logic-

Schottky Selection

1

level MOSFET is a good choice for Q and a logic-level

1

Rectifier D is a clamp that catches the negative inductor

2

MOSFET can be used for Q if its absolute gate-to-source

2

swing during the dead time between turning off the lower

MOSFET and turning on the upper MOSFET. The diode

must be a Schottky type to prevent the lossy parasitic

MOSFET body diode from conducting. It is acceptable to

omit the diode and let the body diode of the lower MOSFET

clamp the negative inductor swing, but efficiency will drop

one or two percent as a result. The diode’s rated reverse

breakdown voltage must be greater than the maximum

input voltage.

voltage rating exceeds the maximum voltage applied to V

.

CC

+12V

+5V OR LESS

VCC

BOOT

HIP6004D

Q

1

2

UGATE

PHASE

HIP6004D DC-DC Converter Application

Circuit

NOTE:

_G-S≈ V -5V

V

CC

Figure 11 shows an application circuit of a DC-DC Converter

for a microprocessor. Detailed information on the circuit,

including a complete Bill-of-Materials and circuit board

description, can be found in Application Note AN9672.

Although the Application Note details the HIP6004, the same

evaluation platform can be used to evaluate the HIP6004D.

Intersil AnswerFAX (321-724-7800) Doc. #99672.

D

2

LGATE

PGND

-

+

NOTE:

V_G-S≈ V

CC

GND

FIGURE 10. UPPER GATE DRIVE - DIRECT V

DRIVE OPTION

CC

+5V

V

=

OR

IN

L1 - 1µH

+12V

F

1

2 x 1µF

2N6394

C

IN

5x 1000µF

+12V

2K

D1

0.1µF

1000pF

VCC

18

OVP

19

1K

2

12

15

OCSET

PGOOD

BOOT

MONITOR

AND

PROTECTION

SS

VSEN

3

1

0.1µF

RT 20

OSC

14 UGATE

13 PHASE

Q1

Q2

L2

3µH

4

VID0

5

6

7

8

+V

OUT

VID1

VID2

VID3

VID4

HIP6004D

D/A

D

2

C

17 LGATE

16 PGND

-

OUT

+

-

9x 1000µF

FB 10

11

GND

9

COMP

2.2nF

20K

8.2nF

0.1µF

15

1.33K

Component Selection Notes:

C

- Each 1000µF 6.3W VDC, Sanyo MV-GX or Equivalent.

D

- 1N4148 or Equivalent.

- 3A, 40V Schottky, Motorola MBR340 or Equivalent.

OUT

- Each 330µF 25W VDC, Sanyo MV-GX or Equivalent.

1

2

IN

L - Core: Micrometals T50-52B; Winding: 10 Turns of 16AWG.

Q , Q - Intersil MOSFET; RFP70N03.

2

1 2

L

- Core: Micrometals T50-52; Winding: 5 Turns of 18AWG.

1

FIGURE 11. MICROPROCESSOR DC-DC CONVERTER

10

HIP6004D

Small Outline Plastic Packages (SOIC)

M20.3 (JEDEC MS-013-AC ISSUE C)

N

20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

INDEX

0.25(0.010)

M

B M

H

AREA

INCHES

MIN MAX

MILLIMETERS

E

SYMBOL

MIN

2.35

0.10

0.33

0.23

12.60

7.40

MAX

2.65

0.30

0.51

0.32

13.00

7.60

NOTES

-B-

A

A1

B

C

D

E

e

0.0926 0.1043

0.0040 0.0118

-

1

2

3

L

0.013

0.0200

9

SEATING PLANE

A

0.0091 0.0125

0.4961 0.5118

0.2914 0.2992

0.050 BSC

-

-A-

o

3

h x 45

D

4

-C-

1.27 BSC

-

α

H

h

0.394

0.010

0.016

0.419

0.029

0.050

10.00

0.25

0.40

10.65

0.75

1.27

-

e

A1

C

5

B

0.10(0.004)

L

6

0.25(0.010) M

C

A M B S

N

α

20

7

o

0

8

0

8

-

NOTES:

Rev. 0 12/93

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

4. Dimension“E”doesnotincludeinterleadflashorprotrusions. Interlead

flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact.

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-

out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site www.intersil.com

Sales Ofﬁce Headquarters

NORTH AMERICA

EUROPE

ASIA

Intersil Corporation

Intersil SA

Mercure Center

100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111

FAX: (32) 2.724.22.05

Intersil (Taiwan) Ltd.

7F-6, No. 101 Fu Hsing North Road

Taipei, Taiwan

Republic of China

TEL: (886) 2 2716 9310

FAX: (886) 2 2715 3029

P. O. Box 883, Mail Stop 53-204

Melbourne, FL 32902

TEL: (321) 724-7000

FAX: (321) 724-7240

11


型号：	HIP6004DCB
厂家：	Intersil
描述：	Buck and Synchronous-Rectifier PWM Controller and Output Voltage Monitor 降压和同步整流PWM控制器和输出电压监视器监视器开关光电二极管控制器
文件：	总11页 (文件大小：205K)
中文：	中文翻译
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