HIP6603CB [INTERSIL]

Synchronous-Rectified Buck MOSFET Drivers; 同步整流降压MOSFET驱动器


型号：	HIP6603CB
厂家：	Intersil
描述：	Synchronous-Rectified Buck MOSFET Drivers 同步整流降压MOSFET驱动器驱动器
文件：	总8页 (文件大小：87K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HIP6601, HIP6603

Data Sheet

January 2000

File Number 4819

Synchronous-Rectiﬁed Buck MOSFET

Drivers

Features

• Drives Two N-Channel MOSFETs

The HIP6601 and HIP6603 are high frequency, dual

MOSFET drivers speciﬁcally designed to drive two power

N-Channel MOSFETs in a synchronous-rectiﬁed buck

converter topology. These drivers combined with a HIP630x

Multi-Phase Buck PWM controller and Intersil UltraFETs™

form a complete core-voltage regulator solution for

advanced microprocessors.

• Adaptive Shoot-Through Protection

• Internal Bootstrap Device

• Supports High Switching Frequency

- Fast Output Rise Time

- Propagation Delay 30ns

• Small 8 Lead SOIC Package

The HIP6601 drives the lower gate in a synchronous-rectiﬁer

bridge to 12V, while the upper gate can be independently

driven over a range from 5V to 12V. The HIP6603 drives

both upper and lower gates over a range of 5V to 12V. This

drive-voltage ﬂexibility provides the advantage of optimizing

applications involving trade-offs between switching losses

and conduction losses.

• Dual Gate-Drive Voltages for Optimal Efﬁciency

• Three-State Input for Bridge Shutdown

• Supply Under Voltage Protection

Applications

• Core Voltage Supplies for Intel Pentium® III, AMD®

Athlon™ Microprocessors

The output drivers in the HIP6601 and HIP6603 have the

capacity to efﬁciently switch power MOSFETs at frequencies

up to 2MHz. Each driver is capable of driving a 3000pF load

with a 30ns propagation delay and 50ns transition time. Both

products implement bootstrapping on the upper gate with

only an external capacitor required. This reduces

implementation complexity and allows the use of higher

performance, cost effective, N-Channel MOSFETs. Adaptive

shoot-through protection is integrated to prevent both

MOSFETs from conducting simultaneously.

• High Frequency Low Proﬁle DC-DC Converters

• High Current Low Voltage DC-DC Converters

Pinout

HIP6601CB/HIP6603CB

(SOIC)

TOP VIEW

UGATE

BOOT

PWM

PHASE

PVCC

VCC

Ordering Information

TEMP. RANGE

PART NUMBER

HIP6601CB

( C)

PACKAGE

8 Ld SOIC

PKG. NO.

M8.15

GND

LGATE

0 to 85

HIP6603CB

M8.15

Block Diagram

PVCC

BOOT

UGATE

PHASE

VCC

+5V

10K

SHOOT-

THROUGH

PROTECTION

† VCC FOR HIP6601

PVCC FOR HIP6603

†

PWM

CONTROL

LOGIC

LGATE

GND

10K

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Pentium® is a registered trademark of Intel Corporation. AMD® is a registered trademark of Advanced Micro Devices, Inc.

HIP6601, HIP6603

Typical Application

+12V

+5V

BOOT

PVCC

UGATE

PHASE

VCC

DRIVE

HIP6601

PWM

LGATE

+12V

+5V

+VCORE

BOOT

VFB

COMP

PWM1

PVCC

UGATE

PHASE

VCC

VSEN

PWM

DRIVE

HIP6601

PWM2

PWM3

PGOOD

LGATE

MAIN

CONTROL

HIP6301

VID

ISEN1

ISEN2

ISEN3

+12V

GND

+5V

BOOT

PVCC

UGATE

PHASE

VCC

DRIVE

PWM HIP6601

LGATE

HIP6601, HIP6603

Absolute Maximum Ratings

Thermal Information

Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V

Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3V

Thermal Resistance

θ_JA( C/W)

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

113

BOOT Voltage (V

- V

). . . . . . . . . . . . . . . . . . . . . . . .15V

BOOT

PHASE

Maximum Junction Temperature (Plastic Package) . . . . . . . .150 C

Input Voltage (V

) . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 7V

PWM

Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C

UGATE. . . . . . . . . . . . . . . . . . . . . . V

LGATE . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to V

- 0.3V to V

+ 0.3V

PHASE

BOOT

PVCC

(SOIC - Lead Tips Only)

ESD Rating

Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . .3kV

Machine Model (Per EIAJ ED-4701 Method C-111). . . . . . . .200V

Operating Conditions

Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0 C to 85 C

Maximum Operating Junction Temperature . . . . . . . . . . . . . . 125 C

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V ±10%

Supply Voltage Range, PVCC . . . . . . . . . . . . . . . . . . . . . 5V to 12V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

Electrical Speciﬁcations Recommended Operating Conditions, Unless Otherwise Noted

PARAMETER

VCC SUPPLY CURRENT

Bias Supply Current

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

HIP6601, f

HIP6603, f

HIP6601, f

HIP6603, f

= 1MHz, V

= 12V

4.4

2.5

200

1.8

6.2

3.6

430

3.3

µA

VCC

PWM

PVCC

Power Supply Current

PVCC

POWER-ON RESET

VCC Rising Threshold

VCC Falling Threshold

PWM INPUT

9.7

9.0

9.9

9.1

10.0

9.2

Input Current

= 0 or 5V (See Block Diagram)

500

3.7

1.3

µA

PWM

PWM Rising Threshold

PWM Falling Threshold

UGATE Rise Time

3.6

1.4

UGATE

= V

= 12V, 3nF load

PVCC

VCC

LGATE Rise Time

LGATE

UGATE

UGATE Fall Time

LGATE Fall Time

LGATE

UGATE Turn-Off Propagation Delay

LGATE Turn-Off Propagation Delay

Shutdown Window

TPDL

= V

UGATE

LGATE

VCC

PVCC

TPDL

= V

PVCC

1.5

3.6

Shutdown Holdoff Time

OUTPUT

230

Upper Drive Source Impedance

= 12V, V

= 5V

= 12V

2.5

7.0

2.3

1.0

4.5

9.0

1.5

3.0

7.5

2.8

1.3

5.0

9.5

2.9

Ω

UGATE

VCC

PVCC

= V

PVCC

Upper Drive Sink Impedance

Lower Drive Source Impedance

Lower Drive Sink Impedance

= 12V, V

= 5V

UGATE

PVCC

= 12V

= 5V

LGATE

= 12V

= V

PVCC

= 12V

HIP6601, HIP6603

PVCC (Pin 7)

Functional Pin Description

For the HIP6601, this pin supplies the upper gate drive bias.

Connect this pin from +12V down to +5V.

UGATE (Pin 1)

Upper gate drive output. Connect to gate of high-side power

N-Channel MOSFET.

For the HIP6603, this pin supplies both the upper and lower

gate drive bias. Connect this pin to either +12V or +5V.

BOOT (Pin 2)

PHASE (Pin 8)

Floating bootstrap supply pin for the upper gate drive.

Connect the bootstrap capacitor between this pin and the

PHASE pin. The bootstrap capacitor provides the charge to

turn on the upper MOSFET. See the Internal Bootstrap

Device section under DESCRIPTION for guidance in

choosing the appropriate capacitor value.

Connect this pin to the source of the upper MOSFET and the

drain of the lower MOSFET. The PHASE voltage is

monitored for adaptive shoot-through protection. This pin

also provides a return path for the upper gate drive.

Description

PWM (Pin 3)

Operation

The PWM signal is the control input for the driver. The PWM

signal can enter three distinct states during operation, see the

three-state PWM Input section under DESCRIPTION for further

details. Connect this pin to the PWM output of the controller.

Designed for versatility and speed, the HIP6601 and HIP6603

dual MOSFET drivers control both high-side and low-side N-

Channel FETs from one externally provided PWM signal.

The upper and lower gates are held low until the driver is

initialized. Once the VCC voltage surpasses the VCC Rising

Threshold (See Electrical Speciﬁcations), the PWM signal

takes control of gate transitions. A rising edge on PWM

initiates the turn-off of the lower MOSFET (see Timing

GND (Pin 4)

Bias and reference ground. All signals are referenced to this

node.

LGATE (Pin 5)

Diagram). After a short propagation delay [TPDL

], the

LGATE

] are

Lower gate drive output. Connect to gate of the low-side

power N-Channel MOSFET.

lower gate begins to fall. Typical fall times [TF

LGATE

provided in the Electrical Speciﬁcations section. Adaptive

shoot-through circuitry monitors the LGATE voltage and

VCC (Pin 6)

Connect this pin to a +12V bias supply. Place a high quality

bypass capacitor from this pin to GND.

determines the upper gate delay time [TPDH ] based

UGATE

on how quickly the LGATE voltage drops below 1.0V. This

prevents both the lower and upper MOSFETs from

conducting simultaneously or shoot-through. Once this delay

period is complete the upper gate drive begins to rise

[TR

] and the upper MOSFET turns on.

UGATE

Timing Diagram

PWM

TPDH

UGATE

TPDL

UGATE

LGATE

TPDL

TPDH

LGATE

HIP6601, HIP6603

A falling transition on PWM indicates the turn-off of the upper

MOSFET and the turn-on of the lower MOSFET. A short

propagation delay [TPDL ] is encountered before the

The bootstrap capacitor must have a maximum voltage

rating above VCC + 5V. The bootstrap capacitor can be

chosen from the following equation:

UGATE

upper gate begins to fall [TF

]. Again, the adaptive

UGATE

shoot-through circuitry determines the lower gate delay time,

TPDH . The PHASE voltage is monitored and the lower

GATE

-----------------------

≥

BOOT

∆V

BOOT

LGATE

gate is allowed to rise after PHASE drops below 0.5V. The

Where Q

is the amount of gate charge required to fully

GATE

charge the gate of the upper MOSFET. The ∆V

deﬁned as the allowable droop in the rail of the upper drive.

lower gate then rises [TR ], turning on the lower

LGATE

term is

BOOT

MOSFET.

Three-State PWM Input

As an example, suppose a HUF76139 is chosen as the

A unique feature of the HIP660X drivers is the addition of a

shutdown window to the PWM input. If the PWM signal

enters and remains within the shutdown window for a set

holdoff time, the output drivers are disabled and both

MOSFET gates are pulled and held low. The shutdown state

is removed when the PWM signal moves outside the

shutdown window. Otherwise, the PWM rising and falling

thresholds outlined in the ELECTRICAL SPECIFICATIONS

determine when the lower and upper gates are enabled.

upper MOSFET. The gate charge, Q

GATE

, from the data

sheet is 65nC for a 10V upper gate drive. We will assume a

200mV droop in drive voltage over the PWM cycle. We ﬁnd

that a bootstrap capacitance of at least 0.325µF is required.

The next larger standard value capacitance is 0.33µF.

Gate Drive Voltage Versatility

The HIP6601 and HIP6603 provide the user total ﬂexibility in

choosing the gate drive voltage. The HIP6601 lower gate

drive is ﬁxed to VCC [+12V], but the upper drive rail can

range from 12V down to 5V depending on what voltage is

applied to PVCC. The HIP6603 ties the upper and lower

drive rails together. Simply applying a voltage from 5V up to

12V on PVCC will set both driver rail voltages.

Adaptive Shoot-Through Protection

Both drivers incorporate adaptive shoot-through protection

to prevent upper and lower MOSFETs from conducting

simultaneously and shorting the input supply. This is

accomplished by ensuring the falling gate has turned off one

MOSFET before the other is allowed to rise.

Power Dissipation

Package power dissipation is mainly a function of the

switching frequency and total gate charge of the selected

MOSFETs. Calculating the power dissipation in the driver for

a desired application is critical to ensuring safe operation.

Exceeding the maximum allowable power dissipation level

will push the IC beyond the maximum recommended

operating junction temperature of 125^oC. The maximum

allowable IC power dissipation for the SO8 package is

approximately 800mW. When designing the driver into an

application, it is recommended that the following calculation

be performed to ensure safe operation at the desired

frequency for the selected MOSFETs. The power dissipated

by the driver is approximated as:

During turn-off of the lower MOSFET, the LGATE voltage is

monitored until it reaches a 1.0V threshold, at which time the

UGATE is released to rise. Adaptive shoot-through circuitry

monitors the PHASE voltage during UGATE turn-off. Once

PHASE has dropped below a threshold of 0.5V, the LGATE

is allowed to rise. PHASE continues to be monitored during

the lower gate rise time. If the PHASE voltage exceeds the

0.5V threshold during this period and remains high for longer

than 2µs, the LGATE transitions low. Both upper and lower

gates are then held low until the next rising edge of the PWM

signal.

Power-On Reset (POR) Function

During initial startup, the VCC voltage rise is monitored and

gate drives are held low until a typical VCC rising threshold

of 9.9V is reached. Once the rising VCC threshold is

exceeded, the PWM input signal takes control of the gate

drives. If VCC drops below a typical VCC falling threshold of

9.1V during operation, then both gate drives are again held

low. This condition persists until the VCC voltage exceeds

the VCC rising threshold.

P = 1.05f

V Q + V Q + I

DDQ

where f is the switching frequency of the PWM signal. V

and V represent the upper and lower gate rail voltage. Q

and Q is the upper and lower gate charge determined by

MOSFET selection and any external capacitance added to

the gate pins. The I product is the quiescent power

DDQ CC

of the driver and is typically 30mW.

Internal Bootstrap Device

The power dissipation approximation is a result of power

transferred to and from the upper and lower gates. But, the

internal bootstrap device also dissipates power on-chip

during the refresh cycle. Expressing this power in terms of

the upper MOSFET total gate charge is explained below.

Both drivers feature an internal bootstrap device. Simply

adding an external capacitor across the BOOT and PHASE

pins completes the bootstrap circuit.

HIP6601, HIP6603

The bootstrap device conducts when the lower MOSFET or

it’s body diode conducts and pulls the PHASE node toward

GND. While the bootstrap device conducts, a current path is

formed that refreshes the bootstrap capacitor. Since the

upper gate is driving a MOSFET, the charge removed from

the bootstrap capacitor is equivalent to the total gate charge

of the MOSFET. Therefore, the refresh power required by the

bootstrap capacitor is equivalent to the power used to

charge the gate capacitance of the MOSFET.

1000

800

600

400

200

PVCC = VCC = 12V

= C = 3nF

= C = 1nF

Q V

REFRESH

= C = 2nF

LOSS

PVCC

= C = 4nF

= C = 5nF

where Q

is the total charge removed from the bootstrap

LOSS

capacitor and provided to the upper gate load.

500

1000

FREQUENCY (kHz)

1500

2000

The 1.05 factor is a correction factor derived from the

following characterization. The base circuit for characterizing

the drivers for different loading proﬁles and frequencies is

FIGURE 1. POWER DISSIPATION vs FREQUENCY

provided. C and C are the upper and lower gate load

capacitors. Decoupling capacitors [0.15µF] are added to the

PVCC and VCC pins. The bootstrap capacitor value is

0.01µF.

1000

PVCC = VCC = 12V

800

600

400

200

In Figure 1, C and C values are the same and frequency

= C = 3nF

is varied from 50kHz to 2MHz. PVCC and VCC are tied

together to a +12V supply. Curves do exceed the 800mW

cutoff, but continuous operation above this point is not

recommended.

= 3nF

Figure 2 shows the dissipation in the driver with 3nF loading

on both gates and each individually. Note the higher upper

gate power dissipation which is due to the bootstrap device

refresh cycle. Again PVCC and VCC are tied together and to

a +12V supply.

500

1000

1500

2000

FREQUENCY (kHz)

Test Circuit

FIGURE 2. 3nF LOADING PROFILE

+5V OR +12V

The impact of loading on power dissipation is shown in

Figure 3. Frequency is held constant while the gate

+12V

0.01µF

capacitors are varied from 1nF to 5nF. VCC and PVCC are

tied together and to a +12V supply. Figures 4 through 6

show the same characterization for the HIP6603 with a +5V

supply on PVCC and VCC tied to a +12V supply.

BOOT

PVCC

2N7002

0.15µF

UGATE

PHASE

VCC

Since both upper and lower gate capacitance can vary,

Figure 7 shows dissipation curves versus lower gate

capacitance with upper gate capacitance held constant at

three different values. These curves apply only to the

HIP6601 due to power supply conﬁguration.

0.15µF

LGATE

PWM

100kΩ

2N7002

GND

HIP6601, HIP6603

600

500

400

300

200

100

400

PVCC = VCC = 12V

FREQUENCY = 800kHz

PVCC = 5V VCC = 12V

320

240

160

= C = 5nF

= C = 4nF

= C = 3nF

FREQUENCY = 500kHz

= C = 2nF

= C = 1nF

FREQUENCY = 200kHz

4.0

500

1000

1500

2000

1.0

2.0

3.0

5.0

GATE CAPACITANCE (C = C ), (nF)

FREQUENCY (kHz)

FIGURE 3. POWER DISSIPATION vs LOADING

FIGURE 4. POWER DISSIPATION vs FREQUENCY (HIP6603)

250

300

240

180

120

PVCC = 5V VCC = 12V

200

= C = 3nF

FREQUENCY = 800kHz

150

= 3nF

100

FREQUENCY = 500kHz

= 1nF

FREQUENCY = 200kHz

1.0

2.0

3.0

4.0

5.0

500

1000

1500

2000

GATE CAPACITANCE (C = C ), (nF)

FREQUENCY (kHz)

FIGURE 5. 3nF LOADING PROFILE (HIP6603)

FIGURE 6. VARIABLE LOADING PROFILE (HIP6603)

400

= 5nF

= 3nF

PVCC = 5V VCC = 12V

350

300

200

150

100

= 1nF

1.0

2.0

3.0

4.0

5.0

FREQUENCY (kHz)

FIGURE 7. POWER DISSIPATION vs LOADING (HIP6601)

HIP6601, HIP6603

Small Outline Plastic Packages (SOIC)

M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC

PACKAGE

INDEX

AREA

0.25(0.010)

B M

INCHES

MILLIMETERS

-B-

SYMBOL

MIN

MAX

MIN

1.35

0.10

0.33

0.19

4.80

3.80

MAX

1.75

0.25

0.51

0.25

5.00

4.00

NOTES

0.0532

0.0040

0.013

0.0688

0.0098

0.020

SEATING PLANE

0.0075

0.1890

0.1497

0.0098

0.1968

0.1574

-A-

h x 45

-C-

0.050 BSC

1.27 BSC

0.2284

0.0099

0.016

0.2440

0.0196

0.050

5.80

0.25

0.40

6.20

0.50

1.27

0.10(0.004)

0.25(0.010) M

A M B S

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

Rev. 0 12/93

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact.

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-

out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site www.intersil.com

Sales Ofﬁce Headquarters

NORTH AMERICA

EUROPE

ASIA

Intersil Corporation

Intersil SA

Mercure Center

100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111

FAX: (32) 2.724.22.05

Intersil (Taiwan) Ltd.

7F-6, No. 101 Fu Hsing North Road

Taipei, Taiwan

Republic of China

TEL: (886) 2 2716 9310

FAX: (886) 2 2715 3029

P. O. Box 883, Mail Stop 53-204

Melbourne, FL 32902

TEL: (321) 724-7000

FAX: (321) 724-7240

HIP6603CB [INTERSIL]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E