HIP6604BCRZ [INTERSIL]

Synchronous Rectified Buck MOSFET Drivers; 同步整流降压MOSFET驱动器


型号：	HIP6604BCRZ
厂家：	Intersil
描述：	Synchronous Rectified Buck MOSFET Drivers 同步整流降压MOSFET驱动器驱动器接口集成电路
文件：	总12页 (文件大小：261K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HIP6601B, HIP6603B, HIP6604B

Data Sheet

May 1, 2012

FN9072.8

Synchronous Rectified Buck

MOSFET Drivers

Features

• Drives Two N-Channel MOSFETs

• Adaptive Shoot-Through Protection

• Internal Bootstrap Device

The HIP6601B, HIP6603B and HIP6604B are high-frequency,

dual MOSFET drivers specifically designed to drive two power

N-Channel MOSFETs in a synchronous rectified buck converter

topology. These drivers combined with a HIP63xx or the ISL65xx

series of Multi-Phase Buck PWM controllers and MOSFETs form

a complete core-voltage regulator solution for advanced

microprocessors.

• Supports High Switching Frequency

- Fast Output Rise Time

- Propagation Delay 30ns

• Small 8 Ld SOIC and EPSOIC and 16 Ld QFN Packages

• Dual Gate-Drive Voltages for Optimal Efficiency

• Three-State Input for Output Stage Shutdown

• Supply Undervoltage Protection

The HIP6601B drives the lower gate in a synchronous rectifier to

12V, while the upper gate can be independently driven over a range

from 5V to 12V. The HIP6603B drives both upper and lower gates

over a range of 5V to 12V. This drive-voltage flexibility provides

the advantage of optimizing applications involving trade-offs

between switching losses and conduction losses. The HIP6604B

can be configured as either a HIP6601B or a HIP6603B.

• QFN Package

- Compliant to JEDEC PUB95 MO-220 QFN—Quad Flat No

Leads—Product Outline.

The output drivers in the HIP6601B, HIP6603B and HIP6604B

have the capacity to efficiently switch power MOSFETs at

frequencies up to 2MHz. Each driver is capable of driving a

3000pF load with a 30ns propagation delay and 50ns transition

time. These products implement bootstrapping on the upper gate

with only an external capacitor required. This reduces

implementation complexity and allows the use of higher

performance, cost effective, N-Channel MOSFETs. Adaptive

shoot-through protection is integrated to prevent both MOSFETs

from conducting simultaneously.

- Near Chip-Scale Package Footprint; Improves PCB

Efficiency and Thinner in Profile.

• Pb-Free (RoHS Compliant)

Applications

• Core Voltage Supplies for Intel Pentium® III, AMD® Athlon™

Microprocessors

• High Frequency Low Profile DC/DC Converters

• High Current Low Voltage DC/DC Converters

Related Literature

• Technical Brief TB363, Guidelines for Handling and

Processing Moisture Sensitive Surface Mount Devices (SMDs)

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

HIP6601B, HIP6603B, HIP6604B

Pinouts

Ordering Information

HIP6601BCB, HIP6603BCB,

HIP6601BECB, HIP6603BECB,

(8 LD SOIC, EPSOIC)

TOP VIEW

TEMP.

RANGE

(°C)

PART NUMBER

(Notes 1, 2)

PART

MARKING

PACKAGE

(Pb-free)

PKG.

DWG. #

HIP6601BCBZ*

6601 BCBZ

0 to +85 8 Ld SOIC

M8.15

UGATE

BOOT

PWM

GND

PHASE

PVCC

VCC

HIP6601BCBZA* 6601 BCBZ

HIP6601BECBZ* 6601 BECBZ

HIP6601BECBZA* 6601 BECBZ

0 to +85 8 Ld EPSOIC M8.15B

LGATE

HIP6603BCBZ*

HIP6603BECBZ* 6603 BECBZ

HIP6604BCRZ* 66 04BCRZ

6603 BCBZ

0 to +85 8 Ld SOIC

0 to +85 8 Ld EPSOIC M8.15B

0 to +85 16 Ld QFN L16.4x4

M8.15

HIP6604B

(16 LD QFN)

TOP VIEW

*Add “-T” suffix for tape and reel. Please refer to TB347 for details on

reel specifications.

NOTES:

1. These Intersil Pb-free plastic packaged products employ special Pb-free

material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and

compatible with both SnPb and Pb-free soldering operations). Intersil Pb-

free products are MSL classified at Pb-free peak reflow temperatures that

meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

BOOT

PWM

GND

12 NC

11 PVCC

10 LVCC

2. For Moisture Sensitivity Level (MSL), please see device information

page for HIP6601B, HIP6603B, HIP6604B. For more information

on MSL, please see Technical Brief TB363.

VCC

Block Diagrams

HIP6601B AND HIP6603B

PVCC

VCC

BOOT

UGATE

PHASE

† VCC FOR HIP6601B

PVCC FOR HIP6603B

+5V

SHOOT-

THROUGH

PROTECTION

10k

PWM

CONTROL

LOGIC

†

LGATE

GND

10k

FOR HIP6601BECB AND HIP6603BECB DEVICES, THE PAD ON THE BOTTOM

SIDE OF THE PACKAGE MUST BE SOLDERED TO THE PC BOARD.

PAD

HIP6604B QFN PACKAGE

PVCC

VCC

BOOT

UGATE

+5V

PHASE

SHOOT-

THROUGH

10k

CONNECT LVCC TO VCC FOR HIP6601B CONFIGURATION

CONNECT LVCC TO PVCC FOR HIP6603B CONFIGURATION.

PROTECTION

PWM

GND

LVCC

CONTROL

LOGIC

LGATE

10k

PGND

PAD

PAD ON THE BOTTOM SIDE OF THE PACKAGE MUST BE SOLDERED TO THE PC BOARD

FN9072.8

May 1, 2012

HIP6601B, HIP6603B, HIP6604B

Typical Application: 3-Channel Converter Using HIP6301 and HIP6601B Gate Drivers

+12V

+5V

BOOT

PVCC

UGATE

PHASE

VCC

DRIVE

HIP6601B

PWM

LGATE

+12V

+5V

CORE

BOOT

VFB

COMP

PWM1

PVCC

UGATE

PHASE

VCC

VSEN

PWM

DRIVE

HIP6601B

PWM2

PWM3

PGOOD

LGATE

MAIN

CONTROL

HIP6301

VID

ISEN1

ISEN2

ISEN3

+12V

GND

+5V

BOOT

PVCC

UGATE

PHASE

VCC

DRIVE

HIP6601B

PWM

LGATE

FN9072.8

May 1, 2012

HIP6601B, HIP6603B, HIP6604B

Absolute Maximum Ratings

Thermal Information

Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V

Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3V

Thermal Resistance

(°C/W)

SOIC Package (Note 3). . . . . . . . . . . . . . . .

EPSOIC Package (Note 4) . . . . . . . . . . . . .

QFN Package (Notes 4, 5) . . . . . . . . . . . . .

Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . . . 150°C

Maximum Storage Temperature Range . . . . . . . . . . . . . . . .-65°C to 150°C

Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

N/A

BOOT Voltage (V

- V

). . . . . . . . . . . . . . . . . . . . . . . . . . . .15V

BOOT

PHASE

Input Voltage (V

UGATE . . . . . . . . . . V

) . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 7V

PWM

- 5V(<400ns pulse width) to V

+ 0.3V

PHASE

BOOT

PVCC

. . . . . . . . . . . . . . . V

LGATE . . . . . . . . . . . . . GND - 5V(<400ns pulse width) to V

. . . . . . . . . . . . . . . . . . GND -0.3V(>400ns pulse width) to V

-0.3V(>400ns pulse width) to V

PHASE . . . . . . . . . . . . . . . . . . . . . . GND -5V(<400ns pulse width) to 15V

. . . . . . . . . . . . . . . . . . . . . . . . . . .GND -0.3V(>400ns pulse width) to 15V

ESD Rating

Human Body Model (Per MIL-STD-883 Method 3015.7). . . . . . . . .3kV

Machine Model (Per EIAJ ED-4701 Method C-111). . . . . . . . . . . .200V

For Recommended soldering conditions see Tech Brief TB389.

Operating Conditions

Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C

Maximum Operating Junction Temperature. . . . . . . . . . . . . . . . . . . 125°C

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V ±10%

Supply Voltage Range, PVCC . . . . . . . . . . . . . . . . . . . . . . . . . . .5V to 12V

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTES:

3. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

4. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

Tech Brief TB379.

5. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.

Electrical Specifications

Recommended Operating Conditions, Unless Otherwise Noted. Boldface limits apply over the operating temperature

range, 0°C to +85°C

MIN

MAX

PARAMETER

VCC SUPPLY CURRENT

Bias Supply Current

SYMBOL

TEST CONDITIONS

(Note 6)

TYP

(Note 6) UNITS

HIP6601B, f

HIP6603B, f

HIP6601B, f

HIP6603B, f

= 1MHz, V

= 12V

4.4

2.5

200

1.8

6.2

3.6

430

3.3

μA

VCC

PWM

PVCC

Upper Gate Bias Current

PVCC

POWER-ON RESET

VCC Rising Threshold

VCC Falling Threshold

PWM INPUT

9.7

7.3

9.95

7.6

10.4

8.0

Input Current

= 0V or 5V (See “Block Diagrams” on

500

μA

PWM

page 2)

PWM Rising Threshold

PWM Falling Threshold

UGATE Rise Time

3.6

1.45

= 12V, 3nF Load

RUGATE

PVCC

LGATE Rise Time

RLGATE

FUGATE

UGATE Fall Time

LGATE Fall Time

FLGATE

UGATE Turn-Off Propagation Delay

LGATE Turn-Off Propagation Delay

Shutdown Window

PDLUGATE

PDLLGATE

1.4

3.6

Shutdown Holdoff Time

230

FN9072.8

May 1, 2012

HIP6601B, HIP6603B, HIP6604B

Electrical Specifications

Recommended Operating Conditions, Unless Otherwise Noted. Boldface limits apply over the operating temperature

range, 0°C to +85°C

MIN

MAX

PARAMETER

OUTPUT

SYMBOL

TEST CONDITIONS

(Note 6)

TYP

(Note 6) UNITS

Upper Drive Source Impedance

= 5V

1.7

3.0

2.3

1.1

580

730

3.0

5.0

4.0

2.0

UGATE

LGATE

PVCC

= 12V

= 5V

Upper Drive Sink Impedance

= 12V

= 5V

Lower Drive Source Current

400

500

= 12V

= 5V

Equivalent Drive Source Impedance

LGATE

Lower Drive Sink Impedance

NOTE:

= 5V or 12V

1.6

4.0

6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization

and are not production tested.

FN9072.8

May 1, 2012

HIP6601B, HIP6603B, HIP6604B

Lower gate driver supply voltage.

Functional Pin Description

PVCC (Pin 7), (Pin 11 QFN)

UGATE (Pin 1), (Pin 16 QFN)

For the HIP6601B and the HIP6604B, this pin supplies the upper gate

drive bias. Connect this pin from +12V down to +5V.

Upper gate drive output. Connect to gate of high-side power N-

Channel MOSFET.

For the HIP6603B, this pin supplies both the upper and lower gate

drive bias. Connect this pin to either +12V or +5V.

BOOT (Pin 2), (Pin 2 QFN)

Floating bootstrap supply pin for the upper gate drive. Connect a

bootstrap capacitor between this pin and the PHASE pin. The

bootstrap capacitor provides the charge to turn on the upper

MOSFET. A resistor in series with boot capacitor is required in

certain applications to reduce ringing on the BOOT pin. See

“Internal Bootstrap Device” on page 7 for guidance in choosing

the appropriate capacitor and resistor values.

PHASE (Pin 8), (Pin 14 QFN)

Connect this pin to the source of the upper MOSFET and the drain

of the lower MOSFET. The PHASE voltage is monitored for

adaptive shoot-through protection. This pin also provides a return

path for the upper gate drive.

Description

PWM (Pin 3), (Pin 3 QFN)

The PWM signal is the control input for the driver. The PWM signal

can enter three distinct states during operation, see the “Three-State

PWM Input” on page 7 for further details. Connect this pin to the

PWM output of the controller.

Operation

Designed for versatility and speed, the HIP6601B, HIP6603B and

HIP6604B dual MOSFET drivers control both high-side and low-

side N-Channel FETs from one externally provided PWM signal.

GND (Pin 4), (Pin 4 QFN)

The upper and lower gates are held low until the driver is

initialized. Once the VCC voltage surpasses the VCC Rising

Threshold (See “Electrical Specifications” on page 4), the PWM

signal takes control of gate transitions. A rising edge on PWM

initiates the turn-off of the lower MOSFET (see “Timing Diagram”

Bias and reference ground. All signals are referenced to this

node.

PGND (Pin 5 QFN Package Only)

This pin is the power ground return for the lower gate driver.

on page 6). After a short propagation delay [t

lower gate begins to fall. Typical fall times [t

], the

PDLLGATE

] are

FLGATE

LGATE (Pin 5), (Pin 7 QFN)

provided in the “Electrical Specifications” on page 4. Adaptive

shoot-through circuitry monitors the LGATE voltage and

Lower gate drive output. Connect to gate of the low-side power N-

Channel MOSFET.

determines the upper gate delay time [t

] based on how

PDHUGATE

quickly the LGATE voltage drops below 2.2V. This prevents both

the lower and upper MOSFETs from conducting simultaneously or

shoot-through. Once this delay period is complete the upper gate

VCC (Pin 6), (Pin 9 QFN)

Connect this pin to a +12V bias supply. Place a high quality bypass

capacitor from this pin to GND.

drive begins to rise [t

] and the upper MOSFET turns on.

RUGATE

LVCC (Pin 10 QFN Package Only)

Timing Diagram

PWM

PDHUGATE

PDLUGATE

RUGATE

FUGATE

UGATE

LGATE

RLGATE

FLGATE

PDHLGATE

PDLLGATE

FN9072.8

May 1, 2012

HIP6601B, HIP6603B, HIP6604B

A falling transition on PWM indicates the turn-off of the upper

MOSFET and the turn-on of the lower MOSFET. A short

The bootstrap capacitor must have a maximum voltage rating

above VCC + 5V. The bootstrap capacitor can be chosen from the

following equation:

propagation delay [t

] is encountered before the upper

PDLUGATE

gate begins to fall [t

circuitry determines the lower gate delay time, t

PHASE voltage is monitored and the lower gate is allowed to rise

after PHASE drops below 0.5V. The lower gate then rises

]. Again, the adaptive shoot-through

FUGATE

GATE

(EQ. 1)

. The

-----------------------

≥

PDHLGATE

BOOT

ΔV

BOOT

Where Q

GATE

charge the gate of the upper MOSFET. The ΔV

defined as the allowable droop in the rail of the upper drive.

is the amount of gate charge required to fully

term is

], turning on the lower MOSFET.

RLGATE

BOOT

Three-State PWM Input

A unique feature of the HIP660X drivers is the addition of a

shutdown window to the PWM input. If the PWM signal enters

and remains within the shutdown window for a set holdoff time,

the output drivers are disabled and both MOSFET gates are pulled

and held low. The shutdown state is removed when the PWM

signal moves outside the shutdown window. Otherwise, the PWM

rising and falling thresholds outlined in the Electrical

Specifications determine when the lower and upper gates are

enabled.

As an example, suppose a HUF76139 is chosen as the upper

MOSFET. The gate charge, Q

, from the data sheet is 65nC

GATE

for a 10V upper gate drive. We will assume a 200mV droop in

drive voltage over the PWM cycle. We find that a bootstrap

capacitance of at least 0.325μF is required. The next larger

standard value capacitance is 0.33μF.

In applications which require down conversion from +12V or

higher and PVCC is connected to a +12V source, a boot resistor in

series with the boot capacitor is required. The increased power

density of these designs tend to lead to increased ringing on the

BOOT and PHASE nodes, due to faster switching of larger

currents across given circuit parasitic elements. The addition of the

boot resistor allows for tuning of the circuit until the peak ringing

on BOOT is below 29V from BOOT to GND and 17V from BOOT

to VCC. A boot resistor value of 5Ω typically meets this criteria.

Adaptive Shoot-Through Protection

Both drivers incorporate adaptive shoot-through protection to

prevent upper and lower MOSFETs from conducting

simultaneously and shorting the input supply. This is accomplished

by ensuring the falling gate has turned off one MOSFET before the

other is allowed to rise.

During turn-off of the lower MOSFET, the LGATE voltage is

monitored until it reaches a 2.2V threshold, at which time the

UGATE is released to rise. Adaptive shoot-through circuitry

monitors the PHASE voltage during UGATE turn-off. Once

PHASE has dropped below a threshold of 0.5V, the LGATE is

allowed to rise. PHASE continues to be monitored during the

lower gate rise time. If PHASE has not dropped below 0.5V within

250ns, LGATE is taken high to keep the bootstrap capacitor

charged. If the PHASE voltage exceeds the 0.5V threshold during

this period and remains high for longer than 2μs, the LGATE

transitions low. Both upper and lower gates are then held low until

the next rising edge of the PWM signal.

In some applications, a well tuned boot resistor reduces the ringing

on the BOOT pin, but the PHASE to GND peak ringing exceeds

17V. A gate resistor placed in the UGATE trace between the

controller and upper MOSFET gate is recommended to reduce the

ringing on the PHASE node by slowing down the upper MOSFET

turn-on. A gate resistor value between 2Ω to 10Ω typically reduces

the PHASE to GND peak ringing below 17V.

Gate Drive Voltage Versatility

The HIP6601B and HIP6603B provide the user total flexibility in

choosing the gate drive voltage. The HIP6601B lower gate drive is

fixed to VCC [+12V], but the upper drive rail can range from 12V

down to 5V depending on what voltage is applied to PVCC. The

HIP6603B ties the upper and lower drive rails together. Simply

applying a voltage from 5V up to 12V on PVCC will set both

driver rail voltages.

Power-On Reset (POR) Function

During initial start-up, the VCC voltage rise is monitored and gate

drives are held low until a typical VCC rising threshold of 9.95V is

reached. Once the rising VCC threshold is exceeded, the PWM

input signal takes control of the gate drives. If VCC drops below a

typical VCC falling threshold of 7.6V during operation, then both

gate drives are again held low. This condition persists until the

VCC voltage exceeds the VCC rising threshold.

Power Dissipation

Package power dissipation is mainly a function of the switching

frequency and total gate charge of the selected MOSFETs.

Calculating the power dissipation in the driver for a desired

application is critical to ensuring safe operation. Exceeding the

maximum allowable power dissipation level will push the IC

beyond the maximum recommended operating junction

temperature of +125°C. The maximum allowable IC power

dissipation for the SO8 package is approximately 800mW. When

designing the driver into an application, it is recommended that the

following calculation be performed to ensure safe operation at the

Internal Bootstrap Device

The HIP6601B, HIP6603B, and HIP6604B drivers all feature an

internal bootstrap device. Simply adding an external capacitor

across the BOOT and PHASE pins completes the bootstrap circuit.

FN9072.8

May 1, 2012

HIP6601B, HIP6603B, HIP6604B

desired frequency for the selected MOSFETs. The power

dissipated by the driver is approximated as:

Test Circuit

+5V OR +12V

0.01μF

⎛

⎝

⎞

+12V

(EQ. 2)

P = 1.05f

+ V Q + I

VCC

DDQ

⎠

BOOT

PVCC

2N7002

where f is the switching frequency of the PWM signal. V and

0.15μF

UGATE

represent the upper and lower gate rail voltage. Q and Q is

U L

PHASE

VCC

the upper and lower gate charge determined by MOSFET selection

and any external capacitance added to the gate pins. The I

DDQ

product is the quiescent power of the driver and is typically

LGATE

0.15μF

PWM

100kΩ

2N7002

30mW.

GND

The power dissipation approximation is a result of power

transferred to and from the upper and lower gates. But, the internal

bootstrap device also dissipates power on-chip during the refresh

cycle. Expressing this power in terms of the upper MOSFET total

gate charge is explained below.

1000

= C = 3nF

800

600

400

200

The bootstrap device conducts when the lower MOSFET or its

body diode conducts and pulls the PHASE node toward GND.

While the bootstrap device conducts, a current path is formed that

refreshes the bootstrap capacitor. Since the upper gate is driving a

MOSFET, the charge removed from the bootstrap capacitor is

equivalent to the total gate charge of the MOSFET. Therefore, the

refresh power required by the bootstrap capacitor is equivalent to

the power used to charge the gate capacitance of the MOSFET.

= C = 2nF

= C = 1nF

= C = 4nF

= C = 5nF

VCC = PVCC = 12V

500

1000

1500 2000

(EQ. 3)

Q V

REFRESH

LOSS

PVCC

FREQUENCY (kHz)

FIGURE 1. POWER DISSIPATION vs FREQUENCY

where Q

is the total charge removed from the bootstrap

LOSS

capacitor and provided to the upper gate load.

1000

VCC = PVCC = 12V

= 3nF

= 0nF

The 1.05 factor is a correction factor derived from the following

characterization. The base circuit for characterizing the drivers for

different loading profiles and frequencies is provided. C and C

are the upper and lower gate load capacitors. Decoupling capacitors

[0.15μF] are added to the PVCC and VCC pins. The bootstrap

capacitor value is 0.01μF.

800

600

400

200

= C = 3nF

= 0nF

= 3nF

In Figure 1, C and C values are the same and frequency is

varied from 50kHz to 2MHz. PVCC and VCC are tied together to

a +12V supply. Curves do exceed the 800mW cutoff, but

continuous operation above this point is not recommended.

500

1000

FREQUENCY (kHz)

1500

2000

Figure 2 shows the dissipation in the driver with 3nF loading on

both gates and each individually. Note the higher upper gate power

dissipation which is due to the bootstrap device refresh cycle.

Again PVCC and VCC are tied together and to a +12V supply.

FIGURE 2. 3nF LOADING PROFILE

The impact of loading on power dissipation is shown in

Figure 3. Frequency is held constant while the gate capacitors are

varied from 1nF to 5nF. VCC and PVCC are tied together and to a

+12V supply. Figures 4, 5 and 6 show the same characterization for

the HIP6603B with a +5V supply on PVCC and VCC tied to a +12V

supply.

Since both upper and lower gate capacitance can vary,

Figure 8 shows dissipation curves versus lower gate capacitance with

upper gate capacitance held constant at three different values. These

curves apply only to the HIP6601B due to power supply

configuration.

FN9072.8

May 1, 2012

HIP6601B, HIP6603B, HIP6604B

Typical Performance Curves

400

1000

VCC = PVCC = 12V

VCC = 12V, PVCC = 5V

FREQUENCY

= 1MHz

800

600

400

200

300

200

100

= C = 5nF

FREQUENCY = 500kHz

FREQUENCY = 200kHz

= C = 4nF

= C = 3nF

= C = 2nF

= C = 1nF

1.0

2.0

3.0

4.0

5.0

500

1000

1500

2000

GATE CAPACITANCE (C = C ) (nF)

FREQUENCY (kHz)

FIGURE 4. POWER DISSIPATION vs FREQUENCY (HIP6603B)

FIGURE 3. POWER DISSIPATION vs LOADING

400

VCC = 12V, PVCC = 5V

300

200

100

= C = 3nF

FREQUENCY = 1MHz

200

= 3nF

= 0nF

FREQUENCY = 500kHz

100

= 0nF

= 3nF

FREQUENCY = 200kHz

1.0

2.0

3.0

4.0

5.0

500

1000

FREQUENCY (kHz)

1500

2000

GATE CAPACITANCE = (C = C ) (nF)

FIGURE 5. 3nF LOADING PROFILE (HIP6603B)

FIGURE 6. VARIABLE LOADING PROFILE (HIP6603B)

1000

500

VCC = 12V, PVCC = 5V

FREQUENCY = 1MHz

= 5nF

= 3nF

FREQUENCY = 500kHz

400

300

200

100

800

600

400

200

FREQUENCY = 500kHz

= 1nF

FREQUENCY = 200kHz

1.0

2.0

3.0

4.0

5.0

1.0

2.0

3.0

4.0

5.0

LOWER GATE CAPACITANCE (C ) (nF)

GATE CAPACITANCE (C = C ) (nF)

FIGURE 8. POWER DISSIPATION vs LOWER GATE

FIGURE 7. POWER DISSIPATION vs FREQUENCY (HIP6601B)

CAPACITANCE FOR FIXED VALUES OF UPPER

GATE CAPACITANCE

FN9072.8

May 1, 2012

HIP6601B, HIP6603B, HIP6604B

Small Outline Exposed Pad Plastic Packages (EPSOIC)

M8.15B

8 LEAD NARROW BODY SMALL OUTLINE EXPOSED PAD

PLASTIC PACKAGE

INDEX

AREA

0.25(0.010)

B M

INCHES

MILLIMETERS

-B-

SYMBOL

MIN

MAX

MIN

1.43

0.03

0.35

0.19

4.80

3.81

MAX

1.68

0.13

0.49

0.25

4.98

3.99

NOTES

0.056

0.001

0.0138

0.0075

0.189

0.150

0.066

0.005

0.0192

0.0098

0.196

0.157

TOP VIEW

SEATING PLANE

-A-

0.050 BSC

1.27 BSC

h x 45

0.230

0.010

0.016

0.244

0.016

0.035

5.84

0.25

0.41

6.20

0.41

0.89

-C-

0.10(0.004)

0°

8°

0°

8°

0.25(0.010) M

SIDE VIEW

C A M B S

0.094

2.387

Rev. 5 8/10

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section

2.2 of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs. Mold flash, protrusion and gate burrs shall not exceed

0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions.

Interlead flash and protrusions shall not exceed 0.25mm (0.010

inch) per side.

BOTTOM VIEW

5. The chamfer on the body is optional. If it is not present, a visual

index feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: INCH. Converted millimeter dimensions

are not necessarily exact.

11. Dimensions “P” and “P1” are thermal and/or electrical enhanced

variations. Values shown are maximum size of exposed pad

within lead count and body size.

FN9072.8

May 1, 2012

HIP6601B, HIP6603B, HIP6604B

Package Outline Drawing

L16.4x4

16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 6, 02/08

4X 1.95

0.65

12X

4.00

PIN #1 INDEX AREA

PIN 1

INDEX AREA

2 . 10 ± 0 . 15

0.15

(4X)

0.10 M C A B

0.28 +0.07 / -0.05

TOP VIEW

+0.15

-0.10

16X 0 . 60

BOTTOM VIEW

SEE DETAIL "X"

0.10

1.00 MAX

BASE PLANE

( 3 . 6 TYP )

SEATING PLANE

0.08

SIDE VIEW

(

2 . 10 )

( 12X 0 . 65 )

( 16X 0 . 28 )

( 16 X 0 . 8 )

0 . 2 REF

0 . 00 MIN.

0 . 05 MAX.

DETAIL "X"

TYPICAL RECOMMENDED LAND PATTERN

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.

2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

Unless otherwise specified, tolerance : Decimal ± 0.05

4. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

Tiebar shown (if present) is a non-functional feature.

The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

FN9072.8

May 1, 2012

HIP6601B, HIP6603B, HIP6604B

Small Outline Plastic Packages (SOIC)

M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

INDEX

0.25(0.010)

B M

AREA

INCHES MILLIMETERS

SYMBOL

MIN

MAX

MIN

1.35

0.10

0.33

0.19

4.80

3.80

MAX

1.75

0.25

0.51

0.25

5.00

4.00

NOTES

-B-

0.0532

0.0040

0.013

0.0688

0.0098

0.020

SEATING PLANE

0.0075

0.1890

0.1497

0.0098

0.1968

0.1574

-A-

h x 45°

-C-

0.050 BSC

1.27 BSC

0.2284

0.0099

0.016

0.2440

0.0196

0.050

5.80

0.25

0.40

6.20

0.50

1.27

0.10(0.004)

0.25(0.010) M

A M B S

NOTES:

0°

8°

0°

8°

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

Rev. 1 6/05

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact.

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN9072.8

May 1, 2012

HIP6604BCRZ [INTERSIL]

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