HIP6604 [INTERSIL]

Synchronous Rectified Buck MOSFET Drivers; 同步整流降压MOSFET驱动器


型号：	HIP6604
厂家：	Intersil
描述：	Synchronous Rectified Buck MOSFET Drivers 同步整流降压MOSFET驱动器驱动器
文件：	总11页 (文件大小：481K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HIP6601A, HIP6603A, HIP6604

Data Sheet

Augus t 2004

FN4884.5

Synchronous Rectified Buck MOSFET

Drivers

Features

• Drives Two N-Channel MOSFETs

• Adaptive Shoot-Through Protection

• Internal Bootstrap Device

The HIP6601A, HIP6603A and HIP6604 are high frequency,

dual MOSFET drivers specifically designed to drive two

power N-Channel MOSFETs in a synchronous rectified buck

converter topology. These drivers combined with a HIP63xx

or an ISL65xx Multi-Phase Buck PWM controller form a

complete core-voltage regulator solution for advanced

microprocessors.

• Supports High Switching Frequency

- Fast Output Rise Time

- Propagation Delay 30ns

• Small 8 Lead SOIC and EPSOIC and 16 Lead QFN

Packages

The HIP6601A drives the lower gate in a synchronous

rectifier to 12V, while the upper gate can be independently

driven over a range from 5V to 12V. The HIP6603A drives

both upper and lower gates over a range of 5V to 12V. This

drive-voltage flexibility provides the advantage of optimizing

applications involving trade-offs between switching losses

and conduction losses. The HIP6604 can be configured as

either a HIP6601A or a HIP6603A.

• Dual Gate-Drive Voltages for Optimal Efficiency

• Three-State Input for Output Stage Shutdown

• Supply Under Voltage Protection

Applications

• Core Voltage Supplies for Intel Pentium® III, AMD®

Athlon™ Microprocessors

• High Frequency Low Profile DC-DC Converters

• High Current Low Voltage DC-DC Converters

The output drivers in the HIP6601A, HIP6603A and HIP6604

have the capacity to efficiently switch power MOSFETs at

frequencies up to 2MHz. Each driver is capable of driving a

3000pF load with a 30ns propagation delay and 50ns

transition time. These products implement bootstrapping on

the upper gate with only an external capacitor required. This

reduces implementation complexity and allows the use of

higher performance, cost effective, N-Channel MOSFETs.

Adaptive shoot-through protection is integrated to prevent

both MOSFETs from conducting simultaneously.

Related Literature

• Technical Brief TB363 “Guidelines for Handling and

Processing Moisture Sensitive Surface Mount Devices

(SMDs)”

Pinouts

HIP6601ACB, HIP6603ACB (SOIC)

HIP6601ECB, HIP6603ECB (EPSOIC)

TOP VIEW

Ordering Information

UGATE

BOOT

PWM

PHASE

PVCC

VCC

TEMP. RANGE

PKG.

DWG. #

PART NUMBER

HIP6601ACB

HIP6603ACB

HIP6601ACB-T

HIP6603ACB-T

HIP6601ECB

HIP6603ECB

HIP6601ECB-T

HIP6603ECB-T

HIP6604CR

( C)

PACKAGE

8 Ld SOIC

0 to 85

M8.15

GND

LGATE

8 Ld SOIC Tape and Reel

HIP6604 (QFN)

TOP VIEW

0 to 85

8 Ld EPSOIC M8.15B

8 Ld EPSOIC Tape and Reel

16 15 14 13

BOOT

PWM

GND

12 NC

0 to 85

16 Ld 4x4 QFN L16.4x4

11 PVCC

10 LVCC

HIP6604CR-T

16 Ld 4x4 QFN Tape and Reel

VCC

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

HIP6601A, HIP6603A, HIP6604

Block Diagrams

HIP6601A AND HIP6603A

PVCC

VCC

BOOT

UGATE

† VCC FOR HIP6601A

PVCC FOR HIP6603A

+5V

PHASE

SHOOT-

THROUGH

PROTECTION

10K

PWM

CONTROL

LOGIC

†

LGATE

GND

FOR HIP6601ECB AND HIP6603ECB DEVICES, THE PAD ON THE BOTTOM

SIDE OF THE PACKAGE MUST BE SOLDERED TO THE PC BOARD.

PAD

HIP6604 QFN PACKAGE

PVCC

VCC

BOOT

UGATE

+5V

PHASE

SHOOT-

THROUGH

10K

CONNECT LVCC TO VCC FOR HIP6601A CONFIGURATION

CONNECT LVCC TO PVCC FOR HIP6603A CONFIGURATION.

PROTECTION

PWM

GND

LVCC

CONTROL

LOGIC

LGATE

10K

PGND

PAD

PAD ON THE BOTTOM SIDE OF THE PACKAGE MUST BE SOLDERED TO THE PC BOARD

HIP6601A, HIP6603A, HIP6604

Typical Application - 3 Channel Converter Using HIP6301 and HIP6601A Gate Drivers

+12V

+5V

BOOT

PVCC

UGATE

PHASE

VCC

DRIVE

HIP6601A

PWM

LGATE

+12V

+5V

CORE

BOOT

VFB

COMP

PWM1

PVCC

UGATE

PHASE

VCC

VSEN

PWM

DRIVE

HIP6601A

PWM2

PWM3

PGOOD

LGATE

MAIN

CONTROL

HIP6301

VID

ISEN1

ISEN2

ISEN3

+12V

GND

+5V

BOOT

PVCC

UGATE

PHASE

VCC

DRIVE

HIP6601A

PWM

LGATE

HIP6601A, HIP6603A, HIP6604

Absolute Maximum Ratings

Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V

Thermal Information

Thermal Resistance

( C/W)

Supply Voltage (PVCC) . . . . . . . . . . . . . . . . . . . . . . . . . VCC + 0.3V

SOIC Package (Note 1)

N/A

BOOT Voltage (V

- V

) . . . . . . . . . . . . . . . . . . . . . . .15V

PHASE

BOOT

) . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 7V

EPSOIC Package (Note 2). . . . . . . . . .

QFN Package (Note 2). . . . . . . . . . . . .

Maximum Junction Temperature (Plastic Package) . . . . . . . .150 C

Maximum Storage Temperature Range . . . . . . . . . -65 C to 150 C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C

N/A

Input Voltage (V

PWM

UGATE. . . . . . .V

. . . . . . . . . . . V

LGATE . . . . . . . . . GND - 5V(<400ns pulse width) to V

- 5V(<400ns pulse width) to V

- 3.0V(>400ns pulse width) to V

+ 0.3V

PHASE

BOOT

PVCC

PHASE

. . . . . . . . . . . . . . GND - 3.0V(>400ns pulse width) to V

(SOIC - Lead Tips Only)

For Recommended soldering conditions see Tech Brief TB389.

PHASE. . . . . . . . . . . . . . . . . .GND - 5V(<400ns pulse width) to 15V

. . . . . . . . . . . . . . . . . . . . . . GND - 0.3V(>400ns pulse width) to 15V

ESD Rating

Human Body Model (Per MIL-STD-883 Method 3015.7) . . . . .3kV

Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . .200V

Operating Conditions

Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . 0 C to 85 C

Maximum Operating Junction Temperature . . . . . . . . . . . . . 125 C

Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V ±10%

Supply Voltage Range, PVCC . . . . . . . . . . . . . . . . . . . . . 5V to 12V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

2. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. θ

the

JC,

“case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379.

Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted

PARAMETER

VCC SUPPLY CURRENT

Bias Supply Current

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

HIP6601A, f

HIP6603A, f

HIP6601A, f

HIP6603A, f

= 1MHz, V

= 12V

4.4

2.5

200

1.8

6.2

3.6

430

3.3

µA

VCC

PWM

PVCC

Upper Gate Bias Current

PVCC

POWER-ON RESET

VCC Rising Threshold

VCC Falling Threshold

PWM INPUT

9.7

9.0

9.95

9.2

10.4

9.5

Input Current

= 0 or 5V (See Block Diagram)

500

3.6

1.45

µA

PWM

PWM Rising Threshold

PWM Falling Threshold

UGATE Rise Time

3.45

1.55

= 12V, 3nF Load

RUGATE

PVCC

LGATE Rise Time

RLGATE

UGATE Fall Time

FUGATE

LGATE Fall Time

FLGATE

UGATE Turn-Off Propagation Delay

LGATE Turn-Off Propagation Delay

Shutdown Window

PDLUGATE

PDLLGATE

1.4

3.6

Shutdown Holdoff Time

OUTPUT

230

Upper Drive Source Impedance

= 5V

1.7

3.0

2.3

1.1

580

730

1.6

3.0

5.0

4.0

2.0

Ω

UGATE

LGATE

PVCC

= 12V

Upper Drive Sink Impedance

Lower Drive Source Current

= 5V

Ω

= 12V

Ω

= 5V, HIP6603A

= 12V, HIP6603A

= 5V or 12V, HIP6601A

= 5V or 12V

400

500

Ω

Lower Drive Sink Impedance

4.0

LGATE

HIP6601A, HIP6603A, HIP6604

PVCC (Pin 7), (Pin 11 QFN)

Functional Pin Des cription

For the HIP6601A and the HIP6604, this pin supplies the

upper gate drive bias. Connect this pin from +12V down to

+5V.

UGATE (Pin 1), (Pin 16 QFN)

Upper gate drive output. Connect to gate of high-side power

N-Channel MOSFET.

For the HIP6603A, this pin supplies both the upper and

lower gate drive bias. Connect this pin to either +12V or +5V.

BOOT (Pin 2), (Pin 2 QFN)

Floating bootstrap supply pin for the upper gate drive.

Connect the bootstrap capacitor between this pin and the

PHASE pin. The bootstrap capacitor provides the charge to

turn on the upper MOSFET. A resistor in series with boot

capacitor is required in certain applications to reduce ringing

on the BOOT pin. See the Internal Bootstrap Device section

under DESCRIPTION for guidance in choosing the

appropriate capacitor and resistor values.

PHASE (Pin 8), (Pin 14 QFN)

Connect this pin to the source of the upper MOSFET and the

drain of the lower MOSFET. The PHASE voltage is

monitored for adaptive shoot-through protection. This pin

also provides a return path for the upper gate drive.

Des cription

Operation

PWM (Pin 3), (Pin 3 QFN)

Designed for versatility and speed, the HIP6601A, HIP6603A

and HIP6604 dual MOSFET drivers control both high-side and

low-side N-Channel FETs from one externally provided PWM

signal.

The PWM signal is the control input for the driver. The PWM

signal can enter three distinct states during operation, see the

three-state PWM Input section under DESCRIPTION for further

details. Connect this pin to the PWM output of the controller.

The upper and lower gates are held low until the driver is

initialized. Once the VCC voltage surpasses the VCC Rising

Threshold (See Electrical Specifications), the PWM signal

takes control of gate transitions. A rising edge on PWM

initiates the turn-off of the lower MOSFET (see Timing

GND (Pin 4), (Pin 4 QFN)

Bias and reference ground. All signals are referenced to this

node.

PGND (Pin 5 QFN Package Only)

Diagram). After a short propagation delay [t

lower gate begins to fall. Typical fall times [t

provided in the Electrical Specifications section. Adaptive

shoot-through circuitry monitors the LGATE voltage and

], the

] are

PDLLGATE

This pin is the power ground return for the lower gate driver.

FLGATE

LGATE (Pin 5), (Pin 7 QFN)

Lower gate drive output. Connect to gate of the low-side

power N-Channel MOSFET.

determines the upper gate delay time [t

] based

PDHUGATE

on how quickly the LGATE voltage drops below 2.2V. This

prevents both the lower and upper MOSFETs from

conducting simultaneously or shoot-through. Once this delay

period is complete the upper gate drive begins to rise

VCC (Pin 6), (Pin 9 QFN)

Connect this pin to a +12V bias supply. Place a high quality

bypass capacitor from this pin to GND.

] and the upper MOSFET turns on.

RUGATE

LVCC (Pin 10 QFN Package Only)

Lower gate driver supply voltage.

Timing Diagram

PWM

PDHUGATE

PDLUGATE

RUGATE

FUGATE

UGATE

LGATE

RLGATE

FLGATE

PDHLGATE

PDLLGATE

HIP6601A, HIP6603A, HIP6604

A falling transition on PWM indicates the turn-off of the upper

MOSFET and the turn-on of the lower MOSFET. A short

propagation delay [t ] is encountered before the

The bootstrap capacitor must have a maximum voltage

rating above VCC + 5V. The bootstrap capacitor can be

chosen from the following equation:

PDLUGATE

upper gate begins to fall [t

]. Again, the adaptive

FUGATE

shoot-through circuitry determines the lower gate delay time,

. The PHASE voltage is monitored and the lower

GATE

-----------------------

≥

BOOT

∆V

BOOT

PDHLGATE

gate is allowed to rise after PHASE drops below 0.5V. The

Where Q

GATE

charge the gate of the upper MOSFET. The ∆V

defined as the allowable droop in the rail of the upper drive.

is the amount of gate charge required to fully

term is

lower gate then rises [t ], turning on the lower

RLGATE

BOOT

MOSFET.

Three-State PWM Input

As an example, suppose a HUF76139 is chosen as the

A unique feature of the HIP660X drivers is the addition of a

shutdown window to the PWM input. If the PWM signal

enters and remains within the shutdown window for a set

holdoff time, the output drivers are disabled and both

MOSFET gates are pulled and held low. The shutdown state

is removed when the PWM signal moves outside the

shutdown window. Otherwise, the PWM rising and falling

thresholds outlined in the ELECTRICAL SPECIFICATIONS

determine when the lower and upper gates are enabled.

upper MOSFET. The gate charge, Q

GATE

, from the data

sheet is 65nC for a 10V upper gate drive. We will assume a

200mV droop in drive voltage over the PWM cycle. We find

that a bootstrap capacitance of at least 0.325µF is required.

The next larger standard value capacitance is 0.33µF.

In applications which require down conversion from +12V or

higher and PVCC is connected to a +12V source, a boot

resistor in series with the boot capacitor is required. The

increased power density of these designs tend to lead to

increased ringing on the BOOT and PHASE nodes, due to

faster switching of larger currents across given circuit

parasitic elements. The addition of the boot resistor allows

for tuning of the circuit until the peak ringing on BOOT is

below 29V from BOOT to GND and 17V from BOOT to VCC.

A boot resistor value of 5Ω typically meets this criteria.

Adaptive Shoot-Through Protection

Both drivers incorporate adaptive shoot-through protection

to prevent upper and lower MOSFETs from conducting

simultaneously and shorting the input supply. This is

accomplished by ensuring the falling gate has turned off one

MOSFET before the other is allowed to rise.

During turn-off of the lower MOSFET, the LGATE voltage is

monitored until it reaches a 2.2V threshold, at which time the

UGATE is released to rise. Adaptive shoot-through circuitry

monitors the PHASE voltage during UGATE turn-off. Once

PHASE has dropped below a threshold of 0.5V, the LGATE

is allowed to rise. PHASE continues to be monitored during

the lower gate rise time. If PHASE has not dropped below

0.5V within 250ns, LGATE is taken high to keep the

bootstrap capacitor charged. If the PHASE voltage exceeds

the 0.5V threshold during this period and remains high for

longer than 2µs, the LGATE transitions low. Both upper and

lower gates are then held low until the next rising edge of the

PWM signal.

In some applications, a well tuned boot resistor reduces the

ringing on the BOOT pin, but the PHASE to GND peak

ringing exceeds 17V. A gate resistor placed in the UGATE

trace between the controller and upper MOSGET gate is

recommended to reduce the ringing on the PHASE node by

slowing down the upper MOSFET turn-on. A gate resistor

value between 2Ω to 10Ω typically reduces the PHASE to

GND peak ringing below 17V.

Gate Drive Voltage Vers atility

The HIP6601A and HIP6603A provide the user total

flexibility in choosing the gate drive voltage. The HIP6601A

lower gate drive is fixed to VCC [+12V], but the upper drive

rail can range from 12V down to 5V depending on what

voltage is applied to PVCC. The HIP6603A ties the upper

and lower drive rails together. Simply applying a voltage

from 5V up to 12V on PVCC will set both driver rail voltages.

Power-On Res et (POR) Function

During initial startup, the VCC voltage rise is monitored and

gate drives are held low until a typical VCC rising threshold

of 9.95V is reached. Once the rising VCC threshold is

exceeded, the PWM input signal takes control of the gate

drives. If VCC drops below a typical VCC falling threshold of

9.2V during operation, then both gate drives are again held

low. This condition persists until the VCC voltage exceeds

the VCC rising threshold.

Power Dis s ipation

Package power dissipation is mainly a function of the

switching frequency and total gate charge of the selected

MOSFETs. Calculating the power dissipation in the driver for

a desired application is critical to ensuring safe operation.

Exceeding the maximum allowable power dissipation level

will push the IC beyond the maximum recommended

operating junction temperature of 125^oC. The maximum

allowable IC power dissipation for the SO8 package is

approximately 800mW. When designing the driver into an

application, it is recommended that the following calculation

Internal Boots trap Device

The HIP6601A, HIP6603A, and HIP6604 drivers all feature

an internal bootstrap device. Simply adding an external

capacitor across the BOOT and PHASE pins completes the

bootstrap circuit.

HIP6601A, HIP6603A, HIP6604

be performed to ensure safe operation at the desired

frequency for the selected MOSFETs. The power dissipated

by the driver is approximated as:

Tes t Circuit

+5V OR +12V







+12V

P = 1.05f

V Q + V Q + I

DDQ

0.01µF



BOOT

PVCC

where f is the switching frequency of the PWM signal. V

2N7002

and V represent the upper and lower gate rail voltage. Q

0.15µF

UGATE

PHASE

and Q is the upper and lower gate charge determined by

VCC

MOSFET selection and any external capacitance added to

the gate pins. The I product is the quiescent power

DDQ CC

LGATE

0.15µF

PWM

of the driver and is typically 30mW.

100kΩ

2N7002

GND

The power dissipation approximation is a result of power

transferred to and from the upper and lower gates. But, the

internal bootstrap device also dissipates power on-chip

during the refresh cycle. Expressing this power in terms of

the upper MOSFET total gate charge is explained below.

1000

= C = 3nF

The bootstrap device conducts when the lower MOSFET or

its body diode conducts and pulls the PHASE node toward

GND. While the bootstrap device conducts, a current path is

formed that refreshes the bootstrap capacitor. Since the

upper gate is driving a MOSFET, the charge removed from

the bootstrap capacitor is equivalent to the total gate charge

of the MOSFET. Therefore, the refresh power required by

the bootstrap capacitor is equivalent to the power used to

charge the gate capacitance of the MOSFET.

800

600

400

200

= C = 2nF

= C = 1nF

= C = 4nF

VCC = PVCC = 12V

= C = 5nF

Q V

REFRESH

LOSS

PVCC

500

1000

1500 2000

FREQUENCY (kHz)

where Q

is the total charge removed from the bootstrap

LOSS

FIGURE 1. POWER DISSIPATION vs FREQUENCY

capacitor and provided to the upper gate load.

The 1.05 factor is a correction factor derived from the

following characterization. The base circuit for characterizing

the drivers for different loading profiles and frequencies is

1000

VCC = PVCC = 12V

= 3nF

= 0nF

800

600

400

200

provided. C and C are the upper and lower gate load

= C = 3nF

capacitors. Decoupling capacitors [0.15µF] are added to the

PVCC and VCC pins. The bootstrap capacitor value is

0.01µF.

= 0nF

= 3nF

In Figure 1, C and C values are the same and frequency

is varied from 50kHz to 2MHz. PVCC and VCC are tied

together to a +12V supply. Curves do exceed the 800mW

cutoff, but continuous operation above this point is not

recommended.

500

1000

FREQUENCY (kHz)

1500

2000

Figure 2 shows the dissipation in the driver with 3nF loading

on both gates and each individually. Note the higher upper

gate power dissipation which is due to the bootstrap device

refresh cycle. Again PVCC and VCC are tied together and to

a +12V supply.

FIGURE 2. 3nF LOADING PROFILE

The impact of loading on power dissipation is shown in

Figure 3. Frequency is held constant while the gate

capacitors are varied from 1nF to 5nF. VCC and PVCC are

tied together and to a +12V supply. Figures 4 through 6

show the same characterization for the HIP6603A with a

+5V supply on PVCC and VCC tied to a +12V supply.

HIP6601A, HIP6603A, HIP6604

Since both upper and lower gate capacitance can vary, Figure 8 shows dissipation curves versus lower gate capacitance with

upper gate capacitance held constant at three different values. These curves apply only to the HIP6601A due to power supply

configuration.

Typical Performance Curves

400

300

200

100

1000

800

600

400

200

VCC = PVCC = 12V

VCC = 12V, PVCC = 5V

FREQUENCY

= 1MHz

= C = 5nF

FREQUENCY = 500kHz

= C = 4nF

= C = 3nF

FREQUENCY = 200kHz

= C = 2nF

= C = 1nF

1.0

2.0

3.0

4.0

5.0

500

1000

1500

2000

GATE CAPACITANCE (C = C ) (nF)

FREQUENCY (kHz)

FIGURE 3. POWER DISSIPATION vs LOADING

VCC = 12V, PVCC = 5V

FIGURE 4. POWER DISSIPATION vs FREQUENCY (HIP6603A)

400

300

200

100

VCC = 12V, PVCC = 5V

300

= C = 3nF

FREQUENCY = 1MHz

200

= 3nF

= 0nF

FREQUENCY = 500kHz

100

= 0nF

= 3nF

FREQUENCY = 200kHz

1.0

2.0

3.0

4.0

5.0

500

1000

FREQUENCY (kHz)

1500

2000

GATE CAPACITANCE = (C = C ) (nF)

FIGURE 5. 3nF LOADING PROFILE (HIP6603A)

FIGURE 6. VARIABLE LOADING PROFILE (HIP6603A)

500

1000

800

600

400

200

VCC = 12V, PVCC = 5V

FREQUENCY = 1MHz

= 5nF

= 3nF

FREQUENCY = 500kHz

400

300

200

100

FREQUENCY = 500kHz

= 1nF

FREQUENCY = 200kHz

1.0

2.0

3.0

4.0

5.0

GATE CAPACITANCE (C = C ) (nF)

1.0

2.0

3.0

4.0

5.0

LOWER GATE CAPACITANCE (C ) (nF)

FIGURE 7. POWER DISSIPATION vs FREQUENCY (HIP6601A)

FIGURE 8. POWER DISSIPATION vs LOWER GATE

CAPACITANCE FOR FIXED VALUES OF UPPER

GATE CAPACITANCE

HIP6601A, HIP6603A, HIP6604

Small Outline Expos ed Pad Plas tic Packages (EPSOIC)

M8.15B

8 LEAD NARROW BODY SMALL OUTLINE EXPOSED PAD

PLASTIC PACKAGE

INDEX

AREA

0.25(0.010)

B M

INCHES

MILLIMETERS

-B-

SYMBOL

MIN

MAX

MIN

1.43

0.03

0.35

0.19

4.80

3.31

MAX

1.68

0.13

0.49

0.25

4.98

3.39

NOTES

0.056

0.001

0.0138

0.0075

0.189

0.150

0.066

0.005

0.0192

0.0098

0.196

0.157

TOP VIEW

SEATING PLANE

-A-

0.050 BSC

1.27 BSC

h x 45

0.230

0.010

0.016

0.244

0.016

0.035

5.84

0.25

0.41

6.20

0.41

0.64

-C-

0.10(0.004)

0.25(0.010) M

SIDE VIEW

C A M B S

0.090

2.286

Rev. 0 6/00

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in

Section 2.2 of Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or

gate burrs. Mold flash, protrusion and gate burrs shall not

exceed 0.15mm (0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions.

Interlead flash and protrusions shall not exceed 0.25mm

(0.010 inch) per side.

BOTTOM VIEW

5. The chamfer on the body is optional. If it is not present, a

visual index feature must be located within the crosshatched

area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or

greater above the seating plane, shall not exceed a

maximum value of 0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch

dimensions are not necessarily exact.

11. Dimensions “P” and “P1” are thermal and/or electrical

enhanced variations. Values shown are maximum size of

exposed pad within lead count and body size.

HIP6601A, HIP6603A, HIP6604

Quad Flat No-Lead Plas tic Package (QFN)

L16.4x4

16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

(COMPLIANT TO JEDEC MO-220-VGGC ISSUE C)

Micro Lead Frame Plas tic Package (MLFP)

MILLIMETERS

SYMBOL

MIN

NOMINAL

MAX

1.00

0.05

1.00

NOTES

0.80

0.90

0.20 REF

0.23

1.95

0.28

0.38

2.25

5, 8

4.00 BSC

3.75 BSC

2.10

7, 8

4.00 BSC

3.75 BSC

2.10

7, 8

0.65 BSC

0.25

0.35

0.60

0.75

0.15

0.60

Rev. 4 10/02

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

3. Nd and Ne refer to the number of terminals on each D and E.

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

7. Dimensions D2 and E2 are for the exposed pads which provide

improved electrical and thermal performance.

8. Nominal dimensionsare providedtoassistwith PCBLandPattern

Design efforts, see Intersil Technical Brief TB389.

9. Features and dimensions A2, A3, D1, E1, P & θ are present when

Anvil singulation method is used and not present for saw

singulation.

10. Depending on the method of lead termination at the edge of the

package, a maximum 0.15mm pull back (L1) maybe present. L

minus L1 to be equal to or greater than 0.3mm.

HIP6601A, HIP6603A, HIP6604

Small Outline Plas tic Packages (SOIC)

M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC

PACKAGE

INDEX

0.25(0.010)

B M

AREA

INCHES

MILLIMETERS

-B-

SYMBOL

MIN

MAX

MIN

1.35

0.10

0.33

0.19

4.80

3.80

MAX

1.75

0.25

0.51

0.25

5.00

4.00

NOTES

0.0532

0.0040

0.013

0.0688

0.0098

0.020

SEATING PLANE

0.0075

0.1890

0.1497

0.0098

0.1968

0.1574

-A-

h x 45

-C-

0.050 BSC

1.27 BSC

0.2284

0.0099

0.016

0.2440

0.0196

0.050

5.80

0.25

0.40

6.20

0.50

1.27

0.10(0.004)

0.25(0.010) M

C A M B S

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

Rev. 0 12/93

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006

inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact.

All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.

Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. How-

ever, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use.

No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site www.intersil.com

HIP6604 [INTERSIL]

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