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HS-1135RH_09 [INTERSIL]

Radiation Hardened, High Speed, Low Power Current Feedback Amplifier; 抗辐射，高速，低功耗电流反馈放大器
HS-1135RH_09
型号： HS-1135RH_09
厂家： Intersil    Intersil
描述：

Radiation Hardened, High Speed, Low Power Current Feedback Amplifier
抗辐射，高速，低功耗电流反馈放大器

放大器
文件： 总9页 (文件大小：253K)
中文：  中文翻译
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HS-1135RH  
®
Data Sheet  
April 6, 2009  
FN4099.3  
Radiation Hardened, High Speed, Low  
Power Current Feedback Amplifier with  
Programmable Output Limiting  
Features  
• Electrically Screened to SMD # 5962-96767  
• QML Qualified per MIL-PRF-38535 Requirements  
• User Programmable Output Voltage Limiting  
The HS-1135RH is a radiation hardened, high speed, low  
power current feedback amplifier built with Intersil’s  
proprietary complementary bipolar UHF-1 (DI bonded wafer)  
process. They are QML approved and processed in full  
compliance with MIL-PRF-38535. This amplifier features  
• Fast Overdrive Recovery . . . . . . . . . . . . . . . . . <1ns (Typ)  
• Low Supply Current . . . . . . . . . . . . . . . . . . . . 6.9mA (Typ)  
• Wide -3dB Bandwidth. . . . . . . . . . . . . . . . . .360MHz (Typ)  
• High Slew Rate . . . . . . . . . . . . . . . . . . . . .1200V/µs (Typ)  
• High Input Impedance . . . . . . . . . . . . . . . . . . . 2MΩ (Typ)  
• Excellent Gain Flatness (to 50MHz). . . . . . ±0.07dB (Typ)  
• Total Gamma Dose . . . . . . . . . . . . . . . . . . . 300kRAD(Si)  
• Latch Up. . . . . . . . . . . . . . . . . . . . . None (DI Technology)  
user programmable output limiting, via the V and V pins.  
H
L
The HS-1135RH is the ideal choice for high speed, low  
power applications requiring output limiting (e.g., flash A/D  
drivers), especially those requiring fast overdrive recovery  
times. The limiting function allows the designer to set the  
maximum and minimum output levels to protect downstream  
stages from damage or input saturation. The  
sub-nanosecond overdrive recovery time ensures a quick  
return to linear operation following an overdrive condition.  
Applications  
Component and composite video systems also benefit from  
this op amp’s performance, as indicated by the gain flatness,  
and differential gain and phase specifications.  
• Flash A/D Driver  
• Video Switching and Routing  
• Pulse and Video Amplifiers  
• Wideband Amplifiers  
• RF/IF Signal Processing  
• Imaging Systems  
Specifications for Rad Hard QML devices are controlled  
by the Defense Supply Center in Columbus (DSCC). The  
SMD numbers listed here must be used when ordering.  
Detailed Electrical Specifications for these devices are  
contained in SMD 5962-96767. A “hot-link” is provided  
on our website for downloading.  
Pinouts  
HS-1135RH  
GDIP1-T8 (CERDIP)  
OR CDIP2-TI (SBDIP)  
TOP VIEW  
HS-1135RH  
CDFP3-F14 (FLATPACK)  
TOP VIEW  
NC  
NC  
-IN  
+IN  
NC  
NC  
V-  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
NC  
V
H
NC  
-IN  
+IN  
V-  
1
2
3
4
8
7
6
5
V
H
V+  
V+  
-
+
OUT  
OUT  
V
L
V
L
NC  
NC  
8
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
Copyright Intersil Americas Inc. 1999, 2009. All Rights Reserved  
1
All other trademarks mentioned are the property of their respective owners.  
HS-1135RH  
Ordering Information  
ORDERING NUMBER  
(Note)  
INTERNAL  
MKT. NUMBER  
TEMP. RANGE  
(°C)  
PART MARKING  
Q5962F96 76701VPC  
Q5962F96 76701VXC  
HS7B- 1135RH /PROTO  
HS9- 1135RH /PROTO  
PACKAGE  
PKG DWG #  
5962F9676701VPC  
5962F9676701VXC  
HS7B-1135RH/PROTO  
HS9-1135RH/PROTO  
HS7B-1135RH-Q  
-55 to +125  
-55 to +125  
-55 to +125  
-55 to +125  
8 Ld SBDIP  
D8.3  
HS9-1135RH-Q  
8 Ld Flatpack K14.A  
8 Ld SBDIP D8.3  
8 Ld Flatpack K14.A  
HS7B-1135RH/PROTO  
HS9-1135RH/PROTO  
NOTE: These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible  
with both SnPb and Pb-free soldering operations.  
FN4099.3  
April 6, 2009  
2
HS-1135RH  
the clamp inputs floating. A similar description applies to the  
symmetrical low clamp circuitry controlled by V .  
L
Clamp Operation  
General  
When the output is clamped, the negative input continues to  
The HS-1135RH features user programmable output clamps  
to limit output voltage excursions. Clamping action is obtained  
by applying voltages to the V and V terminals (pins 8 and 5)  
source a slewing current (I  
) in an attempt to force the  
CLAMP  
output to the quiescent voltage defined by the input. Q must  
P5  
H
L
sink this current while clamping, because the -IN current is  
always mirrored onto the high impedance node. The clamping  
of the amplifier. V sets the upper output limit, while V sets  
H
L
the lower clamp level. If the amplifier tries to drive the output  
above V , or below V , the clamp circuitry limits the output  
current is calculated as (V - V  
)/R . As an example, a  
-IN OUT  
F
H
L
unity gain circuit with V = 2V, V = 1V, and R = 510Ω  
IN  
H
F
voltage at V or V (± the clamp accuracy), respectively. The  
H
L
would have I  
increase by I  
= (2-1)/510Ω = 1.96mA. Note that I  
when the output is clamp limited.  
will  
CLAMP  
CLAMP  
CC  
low input bias currents of the clamp pins allow them to be  
driven by simple resistive divider circuits, or active elements  
such as amplifiers or DACs.  
Clamp Accuracy  
The clamped output voltage will not be exactly equal to the  
voltage applied to V or V . Offset errors, mostly due to V  
BE  
Clamp Circuitry  
H
L
Figure 1 shows a simplified schematic of the HS-1135RH  
input stage, and the high clamp (V ) circuitry. As with all  
current feedback amplifiers, there is a unity gain buffer  
mismatches, necessitate a clamp accuracy parameter which is  
found in the device specifications. Clamp accuracy is a function  
of the clamping conditions. Referring again to Figure 1, it can  
H
(Q - Q ) between the positive and negative inputs. This  
X1 X2  
be seen that one component of clamp accuracy is the V  
BE  
buffer forces -IN to track +IN, and sets up a slewing current  
of (V - V )/R . This current is mirrored onto the high  
mismatch between the Q transistors, and the Q transistors.  
X6 X5  
If the transistors always ran at the same current level, there  
-IN OUT  
F
impedance node (Z) by Q -Q , where it is converted to a  
voltage and fed to the output via another unity gain buffer. If  
no clamping is utilized, the high impedance node may swing  
within the limits defined by Q and Q . Note that when the  
output reaches it’s quiescent value, the current flowing  
X3 X4  
would be no V mismatch, and no contribution to the  
BE  
inaccuracy. The Q transistors are biased at a constant  
X6  
current, but as described earlier, the current through Q is  
X5  
increases,  
P4 N4  
equivalent to I  
. V increases as I  
CLAMP BE  
CLAMP  
causing the clamped output voltage to increase as well. I  
CLAMP  
through -IN is reduced to only that small current (-I  
required to keep the output at the final voltage.  
)
BIAS  
is a function of the overdrive level (V -V  
) and  
-IN OUTCLAMPED  
R ,so clamp accuracy degrades as the overdrive increases, or  
F
V+  
as R decreases. As an example, the specified accuracy of  
F
±60mV for a 2X overdrive with R = 510Ω degrades to ±220mV  
F
Q
Q
P3  
P4  
for R = 240Ω at the same overdrive, or to ±250mV for a 3X  
F
overdrive with R = 510Ω.  
F
50k  
(30k  
Q
N2  
R
1
Consideration must also be given to the fact that the clamp  
voltages have an effect on amplifier linearity.  
FOR V )  
L
Q
P1  
V-  
V+  
Z
I
CLAMP  
+IN  
+1  
Clamp Range  
V
H
Unlike some competitor devices, both V and V have usable  
Q
H
L
N1  
Q
N6  
ranges that cross 0V. While V must be more positive than V ,  
Q
H
L
N5  
200Ω  
Q
both may be positive or negative, within the range restrictions  
P2  
Q
P6  
indicated in the specifications. For example, the HS-1135RH  
Q
P5  
could be limited to ECL output levels by setting V = -0.8V and  
H
Q
Q
N3  
N4  
V = -1.8V. V and V may be connected to the same voltage  
L
H
L
(GND for instance) but the result won’t be in a DC output  
voltage from an AC input signal. A 150 - 200mV AC signal will  
still be present at the output.  
V-  
R
F
-IN  
(EXTERNAL)  
V
OUT  
Recovery from Overdrive  
FIGURE 1. HS-1135RH SIMPLIFIED V CLAMP CIRCUITRY  
H
The output voltage remains at the clamp level as long as the  
overdrive condition remains. When the input voltage drops  
Tracing the path from V to Z illustrates the effect of the  
H
below the overdrive level (V  
/A ) the amplifier will  
CLAMP VCL  
clamp voltage on the high impedance node. V decreases  
H
return to linear operation. A time delay, known as the  
Overdrive Recovery Time, is required for this resumption of  
linear operation. The plots of “Unclamped Performance” and  
“Clamped Performance” highlight the HS-1135RH’s sub  
nanosecond recovery time. The difference between the  
unclamped and clamped propagation delays is the overdrive  
by 2V (QN6 and QP6) to set up the base voltage on QP5.  
QP5 begins to conduct whenever the high impedance node  
BE  
reaches a voltage equal to QP5’s base + 2V (QP5 and  
BE  
QN5). Thus, QP5 clamps node Z whenever Z reaches V .  
H
R1 provides a pull-up network to ensure functionality with  
FN4099.3  
April 6, 2009  
3
HS-1135RH  
recovery time. The appropriate propagation delays are 4.0ns  
The layout and schematic of the board are shown in the  
following:  
for the unclamped pulse, and 4.8ns for the clamped (2X  
overdrive) pulse yielding an overdrive recovery time of  
800ps. The measurement uses the 90% point of the output  
transition to ensure that linear operation has resumed. Note:  
The propagation delay illustrated is dominated by the  
fixturing. The delta shown is accurate, but the true  
HS-1135RH propagation delay is 500ps.  
V
H
1
+IN  
OUT  
V-  
V+  
Use of Die in Hybrid Applications  
V
L
This amplifier is designed with compensation to negate the  
package parasitics that typically lead to instabilities. As a  
result, the use of die in hybrid applications results in  
overcompensated performance due to lower parasitic  
GND  
FIGURE 2A. TOP LAYOUT  
capacitances. Reducing R below the recommended values  
F
for packaged units will solve the problem. For A = +2 the  
V
recommended starting point is 300Ω, while unity gain  
applications should try 400Ω.  
PC Board Layout  
The frequency performance of this amplifier depends a great  
deal on the amount of care taken in designing the PC board.  
The use of low inductance components such as chip  
resistors and chip capacitors is strongly recommended,  
while a solid ground plane is a must!  
Attention should be given to decoupling the power supplies.  
A large value (10µF) tantalum in parallel with a small value  
chip (0.1µF) capacitor works well in most cases.  
FIGURE 2B. BOTTOM LAYOUT  
Terminated microstrip signal lines are recommended at the  
input and output of the device. Output capacitance, such as  
that resulting from an improperly terminated transmission  
line will degrade the frequency response of the amplifier and  
may cause oscillations. In most cases, the oscillation can be  
avoided by placing a resistor in series with the output.  
500Ω  
500Ω  
50Ω  
V
H
1
2
3
4
8
7
6
5
0.1µF  
50Ω  
10µF  
+5V  
Care must also be taken to minimize the capacitance to  
ground seen by the amplifier’s inverting input. The larger this  
capacitance, the worse the gain peaking, resulting in pulse  
overshoot and possible instability. To this end, it is  
recommended that the ground plane be removed under  
traces connected to pin 2, and connections to pin 2 should  
be kept as short as possible.  
IN  
OUT  
V
L
10µF  
0.1µF  
GND  
GND  
-5V  
FIGURE 2C. SCHEMATIC  
FIGURE 2. EVALUATION BOARD SCHEMATIC AND LAYOUT  
An example of a good high frequency layout is the  
Evaluation Board shown in Figure 2.  
Evaluation Board  
An evaluation board is available for the HS-1135RH,  
(HFA11XXEVAL). Please contact your local sales office for  
information.  
FN4099.3  
April 6, 2009  
4
HS-1135RH  
Burn-In Circuit  
HS-1135RH CERDIP  
R
2
1
2
3
4
8
7
6
5
D
2
R
1
V+  
-
R
1
+
C
D
1
1
D
2
V-  
D
C
1
1
NOTES:  
1. R = 1kΩ, ±5% (Per Socket)  
1
2. R = 10kΩ, ±5% (Per Socket)  
2
3. C = 0.01µF (Per Socket) or 0.1µF (Per Row) Minimum  
1
4. D = 1N4002 or Equivalent (Per Board)  
1
5. D = 1N4002 or Equivalent (Per Socket)  
2
6. V+ = +5.5V ±0.5V  
7. V- = -5.5V ±0.5V  
Irradiation Circuit  
HS-1135RH CERDIP  
R
2
1
2
3
4
8
7
6
5
R
1
V+  
-
R
1
+
C
1
V-  
C
2
NOTES:  
8. R = 1kΩ, ±5%  
1
9. R = 10kΩ, ±5%  
2
10. C = C = 0.01µF  
1
2
11. V+ = +5.0V ±0.5V  
12. V- = -5.0V ±0.5V  
FN4099.3  
April 6, 2009  
5
HS-1135RH  
Die Characteristics  
DIE DIMENSIONS:  
Substrate:  
UHF-1, Bonded Wafer, DI  
59 mils x 58.2 mils x 19 mils ±1 mil  
1500µm x 1480µm x 483µm ±25.4µm  
ASSEMBLY RELATED INFORMATION:  
INTERFACE MATERIALS:  
Glassivation:  
Substrate Potential:  
Floating  
Type: Nitride  
Thickness: 4kÅ ±0.5kÅ  
ADDITIONAL INFORMATION:  
Worst Case Current Density:  
Top Metallization:  
5
2
< 2 x 10 A/cm  
Type: Metal 1: AICu(2%)/TiW  
Thickness: Metal 1: 8kÅ ±0.4kÅ  
Type: Metal 2: AICu(2%)  
Transistor Count:  
89  
Thickness: Metal 2: 16kÅ ±0.8kÅ  
Metallization Mask Layout  
HS-1135RH  
-IN  
V
H
V+  
OUT  
+IN  
V-  
V
L
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.  
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality  
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without  
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and  
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result  
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see www.intersil.com  
FN4099.3  
April 6, 2009  
6
HS-1135RH  
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)  
c1 LEAD FINISH  
F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A)  
8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE  
-D-  
E
-A-  
INCHES MILLIMETERS  
MIN  
BASE  
(c)  
METAL  
SYMBOL  
MAX  
0.200  
0.026  
0.023  
0.065  
0.045  
0.018  
0.015  
0.405  
0.310  
MIN  
-
MAX  
5.08  
0.66  
0.58  
1.65  
1.14  
0.46  
0.38  
10.29  
7.87  
NOTES  
b1  
A
b
-
-
M
M
(b)  
0.014  
0.014  
0.045  
0.023  
0.008  
0.008  
-
0.36  
0.36  
1.14  
0.58  
0.20  
0.20  
-
2
-B-  
b1  
b2  
b3  
c
3
SECTION A-A  
bbb  
C A - B  
D
D
S
S
S
-
4
BASE  
PLANE  
Q
A
2
-C-  
SEATING  
PLANE  
c1  
D
3
L
α
5
S1  
b2  
eA  
A A  
e
E
0.220  
5.59  
5
b
C A - B  
eA/2  
C A - B  
c
e
0.100 BSC  
2.54 BSC  
-
eA  
eA/2  
L
0.300 BSC  
0.150 BSC  
7.62 BSC  
3.81 BSC  
-
ccc  
D
aaa  
D
S
M
S
S
M
S
-
NOTES:  
0.125  
0.200  
0.060  
-
3.18  
5.08  
1.52  
-
-
1. Index area: A notch or a pin one identification mark shall be locat-  
ed adjacent to pin one and shall be located within the shaded  
area shown. The manufacturer’s identification shall not be used  
as a pin one identification mark.  
Q
0.015  
0.005  
0.38  
0.13  
6
S1  
7
o
o
o
o
90  
105  
90  
105  
-
α
aaa  
bbb  
ccc  
M
2. The maximum limits of lead dimensions b and c or M shall be  
measured at the centroid of the finished lead surfaces, when  
solder dip or tin plate lead finish is applied.  
-
-
-
-
0.015  
0.030  
0.010  
0.0015  
-
-
-
-
0.38  
0.76  
0.25  
0.038  
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension  
M applies to lead plating and finish thickness.  
-
2, 3  
8
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a  
partial lead paddle. For this configuration dimension b3 replaces  
dimension b2.  
N
8
8
Rev. 0 4/94  
5. This dimension allows for off-center lid, meniscus, and glass  
overrun.  
6. Dimension Q shall be measured from the seating plane to the  
base plane.  
7. Measure dimension S1 at all four corners.  
8. N is the maximum number of terminal positions.  
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.  
10. Controlling dimension: INCH  
FN4099.3  
April 6, 2009  
7
HS-1135RH  
Ceramic Dual-In-Line Metal Seal Packages (SBDIP)  
c1 LEAD FINISH  
D8.3 MIL-STD-1835 CDIP2-T8 (D-4, CONFIGURATION C)  
8 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE  
-A-  
-D-  
E
INCHES MILLIMETERS  
MIN  
BASE  
METAL  
(c)  
SYMBOL  
MAX  
0.200  
0.026  
0.023  
0.065  
0.045  
0.018  
0.015  
0.405  
0.310  
MIN  
-
MAX  
5.08  
0.66  
0.58  
1.65  
1.14  
0.46  
0.38  
10.29  
7.87  
NOTES  
b1  
A
b
-
-
M
A
M
(b)  
0.014  
0.014  
0.045  
0.023  
0.008  
0.008  
-
0.36  
0.36  
1.14  
0.58  
0.20  
0.20  
-
2
-B-  
b1  
b2  
b3  
c
3
SECTION A-A  
S
S
S
D
bbb  
C
A - B  
-
D
4
BASE  
PLANE  
S2  
Q
2
-C-  
SEATING  
PLANE  
c1  
D
3
L
-
S1  
b2  
eA  
A A  
E
0.220  
5.59  
-
e
eA/2  
aaa M C A - B S D S  
b
c
e
0.100 BSC  
2.54 BSC  
-
eA  
eA/2  
L
0.300 BSC  
0.150 BSC  
7.62 BSC  
3.81 BSC  
-
ccc  
M
C A - B S D S  
-
NOTES:  
0.125  
0.200  
3.18  
5.08  
-
1. Index area: A notch or a pin one identification mark shall be locat-  
ed adjacent to pin one and shall be located within the shaded  
area shown. The manufacturer’s identification shall not be used  
as a pin one identification mark.  
Q
0.015  
0.005  
0.005  
0.060  
0.38  
0.13  
0.13  
1.52  
5
S1  
S2  
α
-
-
-
-
6
7
2. The maximum limits of lead dimensions b and c or M shall be  
measured at the centroid of the finished lead surfaces, when  
solder dip or tin plate lead finish is applied.  
o
o
o
o
90  
105  
90  
105  
-
aaa  
bbb  
ccc  
M
-
-
-
-
0.015  
0.030  
0.010  
0.0015  
-
-
-
-
0.38  
0.76  
0.25  
0.038  
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension  
M applies to lead plating and finish thickness.  
-
-
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a  
partial lead paddle. For this configuration dimension b3 replaces  
dimension b2.  
2
8
N
8
8
5. Dimension Q shall be measured from the seating plane to the  
base plane.  
Rev. 0 4/94  
6. Measure dimension S1 at all four corners.  
7. Measure dimension S2 from the top of the ceramic body to the  
nearest metallization or lead.  
8. N is the maximum number of terminal positions.  
9. Braze fillets shall be concave.  
10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.  
11. Controlling dimension: INCH.  
FN4099.3  
April 6, 2009  
8
HS-1135RH  
Ceramic Metal Seal Flatpack Packages (Flatpack)  
K14.A MIL-STD-1835 CDFP3-F14 (F-2A, CONFIGURATION B)  
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE  
A
A
e
INCHES MILLIMETERS  
MIN  
PIN NO. 1  
ID AREA  
SYMBOL  
MAX  
0.115  
0.022  
0.019  
0.009  
0.006  
0.390  
0.260  
0.290  
-
MIN  
1.14  
0.38  
0.38  
0.10  
0.10  
-
MAX  
2.92  
0.56  
0.48  
0.23  
0.15  
9.91  
6.60  
7.11  
-
NOTES  
D
A
b
0.045  
0.015  
0.015  
0.004  
0.004  
-
-
-
-A-  
-B-  
S1  
b1  
c
-
-
b
c1  
D
-
E1  
3
-
0.004  
Q
H
A - B  
D
0.036  
H
A - B  
D
S
M
S
S
M
S
C
E
0.235  
-
5.97  
-
E
E1  
E2  
E3  
e
3
-
-D-  
A
0.125  
0.030  
3.18  
0.76  
-H-  
-C-  
-
-
7
-
L
E2  
L
E3  
E3  
0.050 BSC  
1.27 BSC  
SEATING AND  
BASE PLANE  
c1  
LEAD FINISH  
k
0.008  
0.270  
0.026  
0.005  
-
0.015  
0.370  
0.045  
-
0.20  
6.86  
0.66  
0.13  
-
0.38  
9.40  
1.14  
-
2
-
L
BASE  
METAL  
Q
S1  
M
N
8
6
-
(c)  
b1  
0.0015  
0.04  
M
M
(b)  
14  
14  
-
SECTION A-A  
Rev. 0 5/18/94  
NOTES:  
1. Index area: A notch or a pin one identification mark shall be locat-  
ed adjacent to pin one and shall be located within the shaded  
area shown. The manufacturer’s identification shall not be used  
as a pin one identification mark. Alternately, a tab (dimension k)  
may be used to identify pin one.  
2. If a pin one identification mark is used in addition to a tab, the lim-  
its of dimension k do not apply.  
3. This dimension allows for off-center lid, meniscus, and glass  
overrun.  
4. Dimensions b1 and c1 apply to lead base metal only. Dimension  
M applies to lead plating and finish thickness. The maximum lim-  
its of lead dimensions b and c or M shall be measured at the cen-  
troid of the finished lead surfaces, when solder dip or tin plate  
lead finish is applied.  
5. N is the maximum number of terminal positions.  
6. Measure dimension S1 at all four corners.  
7. For bottom-brazed lead packages, no organic or polymeric mate-  
rials shall be molded to the bottom of the package to cover the  
leads.  
8. Dimension Q shall be measured at the point of exit (beyond the  
meniscus) of the lead from the body. Dimension Q minimum  
shall be reduced by 0.0015 inch (0.038mm) maximum when sol-  
der dip lead finish is applied.  
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.  
10. Controlling dimension: INCH.  
FN4099.3  
April 6, 2009  
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