HS-2510RH [INTERSIL]
Radiation Hardened High Slew Rate Operational Amplifier; 抗辐射高转换率运算放大器
| 型号： | HS-2510RH |
| 厂家： | 
Intersil |
| 描述： | Radiation Hardened High Slew Rate Operational Amplifier |
| 文件： | 总7页 (文件大小：90K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HS-2510RH
Data Sheet
August 1999
File Number 3592.2
Radiation Hardened High Slew Rate
Operational Amplifier
Features
• Electrically Screened to SMD # 5962-95686
The HS-2510RH is a radiation hardened high performance
operational amplifier which set the standard for maximum
slew rate and wide bandwidth operation in moderately
powered, internally compensated, monolithic devices. In
addition to excellent dynamic characteristics, this
dielectrically isolated amplifier also offers low offset current
and high input impedance.
• QML Qualified per MIL-PRF-38535 Requirements
• High Slew Rate. . . . . . . . . . . . 50V/µs (Min), 65V/µs (Typ)
• Wide Power Bandwidth . . . . . . . . . . . . . . . . 750kHz (Min)
• Low Offset Current . . . . . . . . . . . . 25nA (Min), 10nA (Typ)
• High Input Impedance . . . . . . . 50MΩ (Min), 100MΩ (Typ)
• Wide Small Signal Bandwidth . . . . . . . . . . . .12MHz (Typ)
• Fast Settling Time (0.1% of 10V Step) . . . . . . 250ns (Typ)
• Low Quiescent Supply Current. . . . . . . . . . . . . 6mA (Max)
• Internally Compensated For Unity Gain Stability
The ±50V/ms minimum slew rate and fast settling time of the
HS-2510RH are ideally suited for high speed D/A, A/D, and
pulse amplification designs. The HS-2510RH superior
bandwidth and 750kHz minimum full power bandwidth are
extremely useful in RF and video applications. To insure
compliance with slew rate and transient response
• Total Gamma Dose. . . . . . . . . . . . . . . . . . . . . 10kRAD(Si)
specifications, all devices are 100% tested for AC
performance characteristics over full temperature limits. To
improve signal conditioning accuracy, the HS-2510RH
provides a maximum offset current of 25nA and a minimum
input impedance of 50MΩ, both at 25 C, as well as offset
voltage trim capability.
Applications
• Data Acquisition Systems
• RF Amplifiers
o
• Video Amplifiers
• Signal Generators
• Pulse Amplification
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-95686. A “hot-link” is provided
on our homepage for downloading.
Ordering Information
INTERNAL
TEMP. RANGE
www.intersil.com/spacedefense/space.asp
o
ORDERING NUMBER
5962D9568601VPA
5962D9568601VPC
5962D9568601VXC
MKT. NUMBER
( C)
HS7-2510RH-Q
HS7B-2510RH-Q
HS9-2510RH-Q
-55 to 125
-55 to 125
-55 to 125
Pinouts
HS-2510RH GDIP1-T8 (CERDIP)
HS-2510RH
OR
CDFP3-F14 (FLATPACK)
HS-2510RH CDIP2-T8 (SBDIP)
TOP VIEW
TOP VIEW
NC
COMP
BAL
IN-
1
2
3
4
5
6
7
14 NC
13 V+
12 OUT
11 BAL
10 V-
BAL
IN-
IN+
V-
1
2
3
4
8
7
6
5
COMP
V+
-
+
OUT
BAL
-
+
IN+
NC
9
8
NC
NC
NC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
HS-2510RH
Test Circuit
ACOUT
V1
+VCC
-1/10
0.1
1
2K
50pF (NOTE 1)
100K
1 OPEN
S3A
FOR LOOP STABILITY,
USE MIN VALUE CAPACITOR
TO PREVENT OSCILLATION
S7
3
BAL
ADJ
OPEN
1
2
2
50K
2
S1
1
2
-
500K
S9
-1
S5A
S6
1
1
OPEN 2
-
DUT
+
1
+
-
S5B
+
OPEN
1
S2
S8
2
2
1
3
OPEN
OPEN 2
BUFFER
1
V2
2
100K
2
S3B
1
2K
10K
OPEN
100
0.1
1
-VEE
VAC
100
1K
EOUT
x2
5K
2
S4
1
ALL RESISTORS = ±1% (Ω)
ALL CAPACITORS = ±10% (µF)
50K
NOTE:
1. Includes stray capacitances.
FIGURE 1. SIMPLIFIED TEST CIRCUIT
Test Circuit and Waveforms
+15V
INPUT
1K
OUTPUT
50pF
+
-
2K
-15V
FIGURE 2. SIMPLIFIED TEST CIRCUIT
+200mV
0V
+5V
INPUT
INPUT
-200mV
0V
-5V
+5V
90%
OVERSHOOT
90%
OUTPUT
∆V
OUTPUT
10%
10%
-5V
SLEW
RATE
RISE TIME
∆T
= ∆V/∆T
NOTE: Measured on both positive and negative transitions.
Capacitance at Compensation pin should be minimized.
NOTE: Measured on both positive and negative transitions.
Capacitance at Compensation pin should be minimized.
FIGURE 3. SLEW RATE WAVEFORM
FIGURE 4. TRANSIENT RESPONSE WAVEFORM
2
HS-2510RH
o
Typical Performance Curves Unless Otherwise Specified: T = 25 C, VSUPPLY = ±15V
A
100
90
80
BIAS CURRENT
60
85
40
VS = ±20V
VS = ±15
VS = ±10
20
0
80
75
OFFSET CURRENT
-20
-50
-25
0
25
50
o
75
100
125
-50
-55
-25
0
25
50
o
75
100
125
TEMPERATURE ( C)
TEMPERATURE ( C)
FIGURE 5. INPUT BIAS AND OFFSET CURRENT vs
TEMPERATURE
FIGURE 6. OPEN LOOP VOLTAGE GAIN vs TEMPERATURE
100
1.1
SLEW RATE
10K SOURCE RESISTANCE
10
1.0
BANDWIDTH
0 SOURCE RESISTANCE
BANDWIDTH
SLEW RATE
0.9
0.8
1.0
THERMAL NOISE OF 10K RESISTOR
0.1
±10V
±15V
SUPPLY VOLTAGE
±20V
100Hz
1kHz
10kHz
100kHz
1MHz
UPPER 3dB FREQUENCY LOWER 3dB FREQUENCY (10Hz)
FIGURE 7. EQUIVALENT INPUT NOISE vs BANDWIDTH
FIGURE 8. NORMALIZED AC PARAMETERS vs SUPPLY
o
VOLTAGE AT 25 C
1.1
35
VS = ±20
30
BANDWIDTH
SLEW RATE
25
VS = ±15
1.0
SLEW RATE
20
15
BANDWIDTH
VS = ±10
0.9
10
5
0
0.8
10K
100K
1MEG
10MEG
-50
-55
-25
0
25
50
o
75
100
125
TEMPERATURE ( C)
FREQUENCY (Hz)
FIGURE 9. NORMALIZED AC PARAMETERS vs
TEMPERATURE
FIGURE 10. OUTPUT VOLTAGE SWING vs FREQUENCY
o
AT 25 C
3
HS-2510RH
o
Typical Performance Curves Unless Otherwise Specified: T = 25 C, VSUPPLY = ±15V (Continued)
A
120
100
80
4.4
4.2
4.0
3.8
0pF
VS = ±20
VS = ±15
VS = ±10
30pF
60
40
20
100pF
300pF
1000pF
3.6
3.4
3.2
0
-20
10
100
1K
10K
100K
1M
10M 100M
-50
-55
-25
0
25
50
o
75
100
125
FREQUENCY (Hz)
TEMPERATURE ( C)
NOTE: External compensation components are not required for
stability, but may be added to reduce bandwidth, if desired.
FIGURE 12. POWER SUPPLY CURRENT vs TEMPERATURE
FIGURE 11. OPEN LOOP FREQUENCY RESPONSE FOR
VARIOUS VALUES OF CAPACITORS FROM
COMPENSATION PIN TO GROUND
120
V+
o
30
60
90
100
80
o
o
20kΩ
PHASE
RT
60
o
o
o
IN
OUT
40
120
150
180
BAL
20
GAIN
0
V-
-20
10
100
1K
10K
100K
1M
10M 100M
NOTE: Tested offset adjustment is |VOS + 1mV| minimum referred
to output typical range is ±8mV for RT = 20kΩ.
FREQUENCY (Hz)
FIGURE 14. SUGGESTED VOS ADJUSTMENT
FIGURE 13. OPEN LOOP GAIN AND PHASE RESPONSE vs
FREQUENCY
1000
100
INPUT NOISE VOLTAGE
100
10
INPUT NOISE CURRENT
10
1
1
0.1
1
10
100
1K
10K
100K
FREQUENCY (Hz)
FIGURE 15. INPUT NOISE DENSITY vs FREQUENCY
4
HS-2510RH
Burn-In Circuits
HS7-2510RH CERDIP
HS9-2510RH CERAMIC FLATPACK
1
2
3
4
8
7
6
5
1
2
3
4
5
6
7
14
13
12
11
10
9
V+
R1
V+
+
C3
C1
D1
C3
C1
D1
V-
D2
C2
V-
R1
C2
D2
8
NOTES:
2. R1 = 1MΩ, ±5%, 1/4W (Min)
NOTES:
7. R1 = 1MΩ, ±5%, 1/4W (Min)
3. C1 = C2 = 0.01µF/Socket (Min) or 0.1µF/Row (Min)
4. C3 = 0.01µF/Socket (10%)
8. C1 = C2 = 0.01µF/Socket (Min) or 0.1µF/Row (Min)
9. C3 = 0.01µF/Socket (±10%)
5. D1 = D2 = 1N4002 or Equivalent (Per Board)
6. |(V+) - (V-)| = 30V
10. D1 = D2 = 1N4002 or Equivalent (Per Board)
11. |(V+) - (V-)| = 31V ±1V
Irradiation Circuit
HS7-2510RH
C
1
2
3
4
8
7
6
5
C
V1
R
V2
C
NOTES:
12. V1 = +15V ±10%
13. V2 = -15V ±10%
14. R = 1MΩ ±5%
15. C = 0.1µF ±10%
5
HS-2510RH
Schematic Diagram
OFFSET
OFFSET
V+
R6
200
R9
200
R5
200
R8
200
Q1
R11
2K
R7
R10
1.8K 1.8K
Q2
Q3
R1
4K
R12
1.1K
Q8
Q6
Q10
Q16
R2
2K
C2
2.7pF
R13
30
C1
10pF
Q5
R3
960
Q11
Q14
OUTPUT
Q7
Q9
R14
30
Q4
Q17
Q18
COMP
Q12
Q15
R4
11.13K
Q40
INPUT+
Q37
Q19
Q13
Q39
R19
6.3K
1.68K
R25
1.68K
R26
Q38
Q35
Q28
Q29
Q25
Q26
Q20
Q30
Q31
Q36
R20
3K
R23
3K
Q34
Q27
Q22
Q23
R17
Q24
Q21
Q33
R16
1.48K
R18
1.48K
R15
740
R22
240
1.48K
Q32
V-
INPUT-
6
HS-2510RH
Die Characteristics
DIE DIMENSIONS:
Backside Finish:
65 mils x 57 mils x 19 mils
Silicon
(1660µm x 1950µm x 483µm)
ASSEMBLY RELATED INFORMATION:
INTERFACE MATERIALS:
Glassivation:
Substrate Potential (Powered Up):
Unbiased
Type: Nitride
Thickness: 7kÅ ±0.7kÅ
ADDITIONAL INFORMATION:
Worst Case Current Density:
Top Metallization:
5
2
<2 x 10 A/cm
Type: Aluminum
Thickness: 16kÅ ±2kÅ
Transistor Count:
Substrate:
40
Linear Bipolar, DI
Die Attach:
o
Temperature: CERDIP 460 C (Max)
Metallization Mask Layout
HS-2510RH
V+
OUT
BAL
V-
COMP
BAL
-IN
+IN
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
7
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