HS-3374RH_00 [INTERSIL]
Radiation Hardened 8-Bit Bidirectional CMOS/TTL Level Converter; 抗辐射的8位双向CMOS / TTL电平转换器
| 型号： | HS-3374RH_00 |
| 厂家： | 
Intersil |
| 描述： | Radiation Hardened 8-Bit Bidirectional CMOS/TTL Level Converter |
| 文件： | 总3页 (文件大小：514K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HS-3374RH
®
August 2000
File Number 3038.2
Radiation Hardened 8-Bit Bidirectional
CMOS/TTL Level Converter
Features
• Electrically Screened to SMD # 5962-96786
• QML Qualified per MIL-PRF-38535 Requirements
• Radiation Hardened EPI-CMOS
The Intersil HS-3374RH is a radiation hardened 8-bit
bidirectional level converter designed to interface CMOS
logic levels with TTL logic levels in radiation hardened bus
oriented systems. The HS-3374RH is fabricated using a
radiation hardened EPI-CMOS process and features eight
parallel bidirectional buffer/level converters.
5
- Total Dose . . . . . . . . . . . . . . . . . . . . . . 1 x 10 RAD(Si)
12
- Latch-Up Immune. . . . . . . >1 x 10 RAD(Si)/s (Note 1)
• Low Propagation Delay Time
Two control inputs, ENABLE and DISABLE, are used to
determine the direction of data flow, and to set both the in
puts and outputs in the high impedance state. The control
inputs may be driven by either TTL or CMOS logic drivers
capable of sinking one standard TTL load.
- Typical CMOS to TTL Pre-RAD . . . . . . . . . . . . . . . 40ns
- Typical CMOS to TTL Post 100KRAD . . . . . . . . . . 40ns
- Typical TTL to CMOS Pre-RAD . . . . . . . . . . . . . . . 50ns
- Typical TTL to CMOS Post 100KRAD . . . . . . . . . . 50ns
• Low Standby Power
The HS-3374RH is a non-inverting version of the industry
standard CD40116. The non-inverting outputs of the
HS-3374RH reduce PC board chip count by eliminating the
need to restore data back to a non-inverted format.
• +10V CMOS and +5V TTL Power Supply Inputs
• Eight Non-Inverting Three-State Input/Output Channels
• No External TTL Input Pull-Up Resistors Required
• High TTL Sink Current
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
• Equivalent to Sandia SA2996
o
o
• Military Temperature Range. . . . . . . . . . . . -55 C to 125 C
Detailed Electrical Specifications for these devices are
contained in SMD 5962-96786. A “hot-link” is provided
on our homepage for downloading.
NOTE:
1. For operation at 10V and transient levels above
10
1 x 10 RAD(Si)/s, please refer to Application Note 401.
www.intersil.com/spacedefense/space.asp
Pinout
Ordering Information
HS-3374RH
MIL-STD-1835, CDIP2-T22
(SBDIP)
INTERNAL
MKT. NUMBER
TEMP. RANGE
o
ORDERING NUMBER
5962R9678601QWC
5962R9678601VWC
( C)
TOP VIEW
HS1-3374RH-8
HS1-3374RH-Q
-55 to 125
-55 to 125
VDD
A0
A1
A2
A3
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
22
21
VCC
B0
Functional Diagram
20 B1
19 B2
18 B3
VDD = 1
VCC = 22
GND = 11
DISABLE
13
TTL
CMOS
INPUT/OUTPUT
INPUT/OUTPUT
17
B4
16 B5
15 B6
8
8
TTL
CMOS
OUT (IN)
14-21
IN/OUT
14
13
12
B7
2-9
ENABLE 10
11
LEVEL
SHIFTER
DISABLE
NC
GND
ENABLE
10
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
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HS-3374RH
Functional Block Diagram
1 OF 8 IDENTICAL CIRCUITS
VDD
VDD
VDD
VCC
DISABLE
13
VCC
LEVEL
SHIFTER
D
E
B1 TTL
OUTPUT
(INPUT)
2 (3, 4, 5, 6, 7, 8, 9)
A1 CMOS
INPUT (OUTPUT)
VDD
GND
GND
D
21 (20, 19,
18, 17, 16,
15, 14)
LEVEL
SHIFTER
ENABLE
10
LEVEL
SHIFTER
E
GND
GND
NOTES:
2. Enable and disable are TTL type inputs
3. D and E outputs are common to all 8 channels
TRUTH TABLE
INPUT (OUTPUT)
TERMINAL
OUTPUT (INPUT)
TERMINAL
ENABLE
DISABLE
FUNCTION
DATA
NUMBER
DATA
NUMBER
X
1
0
0
1
1
Convert CMOS Level to TTL Level
Convert TTL Level to CMOS Level
High Impedance (Z)
A0
2
3
4
5
6
7
8
9
B0
21
20
19
18
17
16
15
14
A1
B1
A2
B2
0 = Low Level 1 = High Level X = Don’t Care
Z = High Impedance on Both CMOS and TTL sides.
A3
B3
NOTE: An important caveat that is applicable to CMOS devices in
general is that unused inputs should never be left floating. This rule
applies to inputs connected to a three-state bus. The need for
external pull-up resistors during three-state bus conditions is
eliminated by the presence of regenerative latches on the following
HS-3374RH pins: A0 - 7.
A4
B4
A5
B5
A6
B6
The functional block diagram depicts one of these pins with the
regenerative latch. When the CMOS driver assumes the high
impedance state, the latch holds the bus in whatever logic state
(high or low) it was before the three-state condition. A transient
drive current of ±1.5mA at VDD/2 ±0.5V for 10ns is required to
switch the latch. Thus, CMOS device inputs connected to the bus
are not allowed to float during three-state conditions.
A7
B7
WARNING: Do not activate the Disable input by hardwiring to any
TTL input pins. This is an incorrect mode of operation.
2
HS-3374RH
Die Characteristics
DIE DIMENSIONS:
Substrate:
Radiation Hardened Silicon Gate,
Dielectric Isolation
89.4 mils x 76.0 mils x 14 mils ±1 mil
INTERFACE MATERIALS:
Glassivation:
Backside Finish:
Silicon
Type: SiO2
ASSEMBLY RELATED INFORMATION:
Thickness: 11kÅ ±2kÅ
Top Metallization:
Substrate Potential:
Type: AlSi
Unbiased (DI)
Thickness: 8kÅ ±1kÅ
Metallization Mask Layout
HS-3374RH
(20) B1
A2 (4)
A3 (5)
(19) B2
(18) B3
(17) B4
(16) B5
(15) B6
(14) B7
A4 (6)
A5 (7)
A6 (8)
A7 (9)
3
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