HS-81C55RH [INTERSIL]
Radiation Hardened 256 x 8 CMOS RAM; 抗辐射256 ×8 CMOS RAM
| 型号： | HS-81C55RH |
| 厂家： | 
Intersil |
| 描述： | Radiation Hardened 256 x 8 CMOS RAM |
| 文件： | 总14页 (文件大小：88K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HS-81C55RH,
HS-81C56RH
Radiation Hardened
256 x 8 CMOS RAM
March 1996
Features
Description
• Devices QML Qualified in Accordance with
MIL-PRF-38535
The HS-81C55/56RH are radiation hardened RAM and I/O
chips fabricated using the Intersil radiation hardened Self-
Aligned Junction Isolated (SAJI) silicon gate technology.
Latch-up free operation is achieved by the use of epitaxial
starting material to eliminate the parasitic SCR effect seen in
conventional bulk CMOS devices.
• Detailed Electrical and Screening Requirements are
Contained in SMD# 5962-95818 and Intersil’ QM Plan
• Radiation Hardened EPI-CMOS
- Parametrics Guaranteed 1 x 105 RAD(Si)
- Transient Upset > 1 x 108 RAD(Si)/s
- Latch-Up Free > 1 x 1012 RAD(Si)/s
The HS-81C55/56RH is intended for use with the
HS-80C85RH radiation hardened microprocessor system. The
RAM portion is designed as 2048 static cells organized as 256
x 8. A maximum post irradiation access time of 500ns allows
the HS-81C55/56RH to be used with the HS-80C85RH CPU
without any wait states. The HS-81C55RH requires an active
low chip enable while the HS-81C56RH requires an active high
chip enable. These chips are designed for operation utilizing a
single 5V power supply.
• Electrically Equivalent to Sandia SA 3001
• Pin Compatible with Intel 8155/56
• Bus Compatible with HS-80C85RH
• Single 5V Power Supply
Functional Diagram
• Low Standby Current 200µA Max
• Low Operating Current 2mA/MHz
• Completely Static Design
PORT A
IO/M
256 x 8
STATIC
RAM
8
PA0 - PA7
PB0 - PB7
PC0 - PC5
A
B
C
AD0 - AD7
CE OR CE†
ALE
• Internal Address Latches
PORT B
8
• Two Programmable 8-Bit I/O Ports
• One Programmable 6-Bit I/O Port
• Programmable 14-Bit Binary Counter/Timer
• Multiplexed Address and Data Bus
• Self Aligned Junction Isolated (SAJI) Process
• Military Temperature Range -55oC to +125oC
RD
PORT C
8
WR
RESET
TIMER
VDD (10V)
GND
TIMER CLK
TIMER OUT
†81C55RH = CE
81C56RH = CE
Ordering Information
PART NUMBER
5962R9XXXX01QRC
5962R9XXXX01VRC
5962R9XXXX01QXC
5962R9XXXX01VXC
5962R9XXXX02QRC
5962R9XXXX02VRC
5962R9XXXX02QXC
5962R9XXXX02VXC
HS1-81C55RH/Sample
HS9-81C55RH/Sample
HS1-81C56RH/Sample
HS9-81C56RH/Sample
TEMPERATURE RANGE
SCREENING LEVEL
PACKAGE
o
o
-55 C to +125 C
MIL-PRF-38535 Level Q
MIL-PRF-38535 Level V
MIL-PRF-38535 Level Q
MIL-PRF-38535 Level V
MIL-PRF-38535 Level Q
MIL-PRF-38535 Level V
MIL-PRF-38535 Level Q
MIL-PRF-38535 Level V
Sample
40 Lead SBDIP
40 Lead SBDIP
o
o
-55 C to +125 C
o
o
-55 C to +125 C
42 Lead Ceramic Flatpack
42 Lead Ceramic Flatpack
40 Lead SBDIP
o
o
-55 C to +125 C
o
o
-55 C to +125 C
o
o
-55 C to +125 C
40 Lead SBDIP
o
o
-55 C to +125 C
42 Lead Ceramic Flatpack
42 Lead Ceramic Flatpack
40 Lead SBDIP
o
o
-55 C to +125 C
o
+25 C
o
+25 C
Sample
42 Lead Ceramic Flatpack
40 Lead SBDIP
o
+25 C
Sample
o
+25 C
Sample
42 Lead Ceramic Flatpack
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
Spec Number 518056
File Number 3039.1
1
HS-81C55RH, HS-81C56RH
Pinouts
40 LEAD DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T40
TOP VIEW
1
2
3
4
40
39
38
37
36
35
PC3
PC4
VDD
PC2
PC1
PC0
PB7
PB6
TIMER IN
RESET
PC5
TIMER OUT
IO / M
5
6
7
8
9
34 PB5
CE or CE*
RD
33
32
PB4
PB3
WR 10
ALE
31
30
29
28
27
26
25
24
PB2
PB1
*81C55RH = CE
81C56RH = CE
11
AD0 12
PB0
PA7
PA6
PA5
PA4
PA3
13
14
15
16
17
AD1
AD2
AD3
AD4
AD5
AD6 18
AD7 19
GND 20
23 PA2
22 PA1
21 PA0
42 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
INTERSIL OUTLINE K42.A
TOP VIEW
PC3
PC4
1
2
3
4
42
41
40
39
VDD
PC2
PC1
PC0
PB7
TIMER IN
RESET
PC5
5
6
38
37
TIMER OUT
PB6
PB5
PB4
PB3
PB2
PB1
IO/M
7
8
36
35
CE OR CE
RD
WR
9
34
33
32
31
30
29
28
27
10
11
12
13
14
15
16
ALE
AD0
AD1
AD2
AD3
NC
PB0
PA7
PA6
PA5
NC
PA4
AD4
AD5
AD6
17
18
19
26
25
24
PA3
PA2
PA1
PA0
AD7
20
21
23
22
GND
Spec Number 518056
2
HS-81C55RH, HS-81C56RH
Pin Description
SYMBOL
RESET
TYPE
NAME AND FUNCTION
I
Reset: Pulse provided by the HS-80C85RH to initialize the system (connect to HS-80C85RH RESET
OUT). Input high on this line resets the chip and initializes the three I/O ports to input mode. The width
of RESET pulse should typically be two HS-80C85RH clock cycle times.
AD0 - AD7
I/O
Address/Data: Tri-state Address/Data lines that interface with the CPU lower 8-bit Address/Data Bus.
The 8-bit address is latched into the address latch inside the HS-81C55 and HS-81C56RH on the falling
edge of ALE. The address can be either for the memory section or the I/O section depending on the IO/
M input. The 8-bit data is either written into the chip or read from the chip, depending on the WR or RD
input signal.
CE or CE
RD
I
I
Chip Enable: On the HS-81C55RH, this pin is CE and is ACTIVE LOW. On the HS-81C56RH, this pin
is CE and is ACTIVE HIGH.
Read Control: Input low on this line with the Chip Enable active enables and AD0 - AD7 buffers. If IO/
M pin is low, the RAM content will be read out to the AD bus. Otherwise the content of the selected I/O
port or command/status registers will be read to the AD bus.
WR
I
I
Write Control: Input low on this line with the Chip Enable active causes the data on the Address/Data
bus to be written to the RAM or I/O ports and command/status register, depending on IO/M.
ALE
Address Latch Enable: This control signal latches both the address on the AD0 - AD7 lines and the
state of the Chip Enable and IO/M into the chip at the falling edge of ALE.
IO/M
I
I/O Memory: Selects memory if low and I/O and command/status registers if high.
PA0 - PA7 (8)
I/O
Port A: These 8 pins are general purpose I/O pins. The in/out direction is selected by programming the
command register.
PB0 - PB7 (8)
PC0 - PC7 (8)
I/O
I/O
Port B: These 8 pins are general purpose I/O pins. The in/out direction is selected by programming the
command register.
Port C: These 6 pins can function as either input port, output port, or as control signals for PA and PB.
Programming is done through the command register. When PC0 - PC5 are used as control signals, they
will provide the following:
PC0 - A INTR (Port A Interrupt)
PC1 - ABF (Port A Buffer Full)
PC2 - A STB (Port A Strobe)
PC3 - B INTR (Port B Interrupt)
PC4 - B BF (Port B Buffer Full)
PC5 - B STB (Port B Strobe)
TIMER IN
TIMER OUT
VDD
I
O
I
Timer Input: Input to the counter-timer.
Timer Output: This output can be either a square wave or a pulse, depending on the timer mode.
Voltage: +5V.
GND
I
Ground: Ground reference.
Spec Number 518056
3
Specifications HS-81C55RH, HS-81C56RH
Absolute Maximum Ratings
Reliability Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V Thermal Resistance
θ
θ
JC
JA
o
o
Input, Output or I/O Voltage . . . . . . . . . . . . GND-0.3V to VDD+0.3V SBDIP Package. . . . . . . . . . . . . . . . . . . . 40.0 C/W 5.0 C/W
o
o
o
o
Storage Temperature Range . . . . . . . . . . . . . . . . . -65 C to +150 C
Ceramic Flatpack Package . . . . . . . . . . . 45.0 C/W 5.0 C/W
Maximum Package Power Dissipation at +125 C
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.25W
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . . 1.11W
o
o
Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300 C
Typical Derating Factor. . . . . . . . . . . . 2mA/MHz Increase in IDDOP
o
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 If device power exceeds package dissipation capability, provide heat
sinking or derate linearly at the following rate:
o
SBDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25.0mW/ C
o
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . 22.2mW/ C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . +4.75V to +5.25V Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to +0.8V
o
o
Operating Temperature Range. . . . . . . . . . . . . . . . -55 C to +125 C
Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . VDD -0.5V to VDD
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
GROUP A
PARAMETERS
SYMBOL
CONDITIONS
SUBGROUPS TEMPERATURE
MIN
MAX
UNITS
o
o
High Input Leakage
Current
IIH
VDD = 5.25V, VIN = 0V,
Pin under test = VDD
1, 2, 3
-55 C, +25 C,
-
1
µA
o
+125 C
o
o
Low Input Leakage
Current
IIL
VOL
VDD = 5.25V, VIN = 5.25V,
Pin under test = 0V
1, 2, 3
-55 C, +25 C,
-1
-
0.5
-
µA
V
o
+125 C
o
o
Low Output Voltage
High Output Voltage
Static Current
VDD = 5.25V, IOL = 2mA
VDD = 4.75V, IOH = 2mA
VDD = 5.25V
1, 2, 3
-55 C, +25 C,
-
o
+125 C
o
o
VOH
IDDSB
IDDOP
FT
1, 2, 3
-55 C, +25 C,
4.25
V
o
+125 C
o
o
1, 2, 3
-55 C, +25 C,
-
-
-
200
2
µA
mA
-
o
+125 C
o
o
Dynamic Current
Functional Tests
VDD = 5.25V, f = 1MHz
1, 2, 3
-55 C, +25 C,
o
+125 C
o
o
VDD = 4.75V and 5.25V,
VIH = VDD-0.5V, VIL = 0.8V
7, 8A, 8B
-55 C, +25 C,
-
o
+125 C
NOTE: All devices are guaranteed at worst case limits and over radiation. Dynamic current is proportional to operating frequency (2mA/MHz).
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
GROUP A
PARAMETERS
Address Latch Setup Time
Address Hold Time After Latch
Latch to READ/WRITE Control
Valid Data Out From Read Control
Address Stable to Data Out Valid
Latch Enable Width
SYMBOL
TAL
CONDITIONS
Notes 1, 4
Notes 1, 4
Notes 1, 4
Notes 1, 4
Notes 1, 4
Notes 1, 4
Notes 1, 4,7
SUBGROUPS
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
TEMPERATURE
MIN
60
60
200
-
MAX
UNITS
ns
o
o
-55 C ≤ T ≤ +125 C
-
A
o
o
TLA
-55 C ≤ T ≤ +125 C
-
ns
A
o
o
TLC
-55 C ≤ T ≤ +125 C
-
250
500
-
ns
A
o
o
TRD
TAD
TLL
-55 C ≤ T ≤ +125 C
ns
A
o
o
-55 C ≤ T ≤ +125 C
-
ns
A
o
o
-55 C ≤ T ≤ +125 C
200
20
ns
A
o
o
READ/WRITE Control to Latch
Enable
TCL
-55 C ≤ T ≤ +125 C
-
ns
A
o
o
READ/WRITE Control Width
Data In to WRITE Setup Time
Data In Hold Time After WRITE
TCC
TDW
TWD
Notes 1, 4
Notes 1, 4
Notes 1, 4
9, 10, 11
9, 10, 11
9, 10, 11
-55 C ≤ T ≤ +125 C
250
200
25
-
-
-
ns
ns
ns
A
o
o
-55 C ≤ T ≤ +125 C
A
o
o
-55 C ≤ T ≤ +125 C
A
Spec Number 518056
4
Specifications HS-81C55RH, HS-81C56RH
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
GROUP A
PARAMETERS
WRITE to Port Output
SYMBOL
TWP
TPR
CONDITIONS
Notes 1, 4
Notes 1, 4
Notes 1, 4
Notes 1, 4
Notes 1, 4
Notes 1, 4
Notes 1, 4
Notes 1, 4
Notes 1, 4, 5
Notes 1, 4
Notes 1, 4
Notes 1, 4
Notes 1, 4
Notes 1, 4
Notes 1, 4
Notes 1, 4
Notes 1, 4, 6
Notes 1, 4
SUBGROUPS
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
TEMPERATURE
MIN
MAX
300
-
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
o
o
-55 C ≤ T ≤ +125 C
-
50
15
-
A
o
o
Port Input Setup Time
Port Input Hold Time
Strobe to Buffer Full
-55 C ≤ T ≤ +125 C
A
o
o
TRP
-55 C ≤ T ≤ +125 C
-
A
o
o
TSBF
TSS
-55 C ≤ T ≤ +125 C
300
-
A
o
o
Strobe Width
-55 C ≤ T ≤ +125 C
150
-
A
o
o
READ to Buffer Empty
Strobe to INTR Off
TRBE
TSI
-55 C ≤ T ≤ +125 C
300
300
360
-
A
o
o
-55 C ≤ T ≤ +125 C
-
A
o
o
READ to INTR Off
TRDI
TPSS
TPHS
TSBE
TWBF
TWI
-55 C ≤ T ≤ +125 C
A
o
o
Port Setup Time to Strobe
Post Hold Time After Strobe
Strobe to Buffer Empty
WRITE to Buffer full
-55 C ≤ T ≤ +125 C
100
A
o
o
-55 C ≤ T ≤ +125 C
100
-
A
o
o
-55 C ≤ T ≤ +125 C
-
300
300
340
300
300
-
A
o
o
-55 C ≤ T ≤ +125 C
-
-
A
o
o
WRITE to INTR Off
-55 C ≤ T ≤ +125 C
A
o
o
TIMER-IN to TIMER OUT Low
TIMER-IN to TIMER-OUT High
Data Bus Enable from READ Control
TIMER-IN Low Time
TIMER-IN High Time
NOTES:
TTL
-55 C ≤ T ≤ +125 C
-
A
o
o
TTH
-55 C ≤ T ≤ +125 C
-
A
o
o
TRDE
T1
-55 C ≤ T ≤ +125 C
120
40
115
A
o
o
-55 C ≤ T ≤ +125 C
-
A
o
o
T2
-55 C ≤ T ≤ +125 C
-
A
1. All devices guaranteed at worst case limits and over radiation.
2. Operating supply current (IDDOP) is proportional to operating frequency.
3. Output timings are measured with purely capacitive load.
4. For design purposes the limits are given as shown. For compatibility with the 80C85RH microprocessor, the AC parameters are tested
as maximums.
5. Parameter tested as part of the functional test. No read and record data available.
6. At low temperature, T1 is measured down to 10ns. If the reading is less than 10ns, the parameter will read 10ns.
7. Read and Record data available on failing data only.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETERS
SYMBOL
CONDITIONS
TEMPERATURE
MIN
MAX
UNITS
o
Input Capacitance
CIN
VDD = Open, f = 1MHz, All measurements
referenced to device ground
T = +25 C
-
10
pF
A
o
I/O Capacitance
CI/O
COUT
TRDF
TRV
VDD = Open, f = 1MHz, All measurements
referenced to device ground
T = +25 C
-
-
12
10
pF
pF
ns
ns
A
o
Output Capacitance
VDD = Open, f = 1MHz, All measurements
referenced to device ground
T = +25 C
A
o
o
Data Bus Float After
READ
VDD = 4.75V
-55 C, +25 C,
10
-
100
220
o
+125 C
o
o
Recovery Time Between
Controls
VDD = 4.75V
-55 C, +25 C,
o
+125 C
NOTE: The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are
characterized upon initial design release and upon design changes which would affect these characteristics.
Spec Number 518056
5
Specifications HS-81C55RH, HS-81C56RH
Waveforms
READ
CE (81C55RH)
OR
CE (81C56RH)
IO/M
AD0-7
ALE
tAD
ADDRESS
DATA VALID
tAL
tLA
tLL
tRIDE
tRDF
tRD
RD
tCL
tRV
tLC
tCC
WRITE
CE (81C55RH)
OR
CE (81C56RH)
IO/M
AD0-7
ALE
ADDRESS
DATA VALID
tAL
tLA
tDW
tCL
tLL
tLC
tWD
WR
tCL
tCC
tRV
Spec Number 518056
6
HS-81C55RH, HS-81C56RH
Waveforms (Continued)
STROBED INPUT
BF
tSBF
STROBED
INTR
tRBE
tSS
tSI
tRDI
RD
tPSS
tPHS
INPUT DATA
FROM PORT
STROBED OUTPUT
BF
tSBE
STROBE
INTR
tSI
tWBF
tWI
WR
tWP
OUTPUT DATA
TO PORT
Spec Number 518056
7
HS-81C55RH, HS-81C56RH
Waveforms (Continued)
BASIC INPUT
RD
BASIC INPUT
RD
tRP
tWP
tPR
INPUT
INPUT
DATA BUS
DATA BUS
TIMER OUTPUT COUNTDOWN FROM 5 TO 1
LOAD COUNTER CLR
RELOAD COUNTER CLR
2
1
5
4
3
2
1
5
tF
t2
TIMER IN
t1
tR
tCYC
TIMER OUT
(PULSE)
(NOTE 1)
tTL
tTH
tTH
TIMER OUT
(SQUARE WAVE)
(NOTE 1)
tTL
NOTE: THE TIMER OUTPUT IS PERIODIC IF IN AN AUTOMATIC
RELOAD MODE (M, MODE BIT = 1)
Spec Number 518056
8
HS-81C55RH, HS-81C56RH
Metallization Topology
DIE DIMENSIONS:
222 x 202 x 14 ± 1mil (Die Thickness)
METALLIZATION:
Type: AlSi
Thickness: 11kÅ ± 2kÅ
GLASSIVATION:
Type: SiO2
Thickness: 8kÅ ± 1kÅ
Metallization Mask Layout
HS-81C55RH, HS-81C56RH
TIMER OUT (6)
IO/M (7)
(34) PB5
CE OR CE (8)
RD (9)
(33) PB4
(32) PB3
WR (10)
ALE (11)
(31) PB2
(30) PB1
AD0 (12)
(29) PB0
(28) PA7
AD1 (13)
AD2 (14)
(27) PA6
Spec Number 518056
9
HS-81C55RH, HS-81C56RH
Functional Description
7
6
5
4
3
2
1
0
TM2 TM1 IEB IEA PC2 PC1 PB PA
The HS-81C55RH and 81C56RH contains the following:
• 2K Bit Static RAM Organized as 256 x 8
DEFINES
PA0 - PA7
0 = INPUT
• Two 8-Bit I/O Ports (PA and PB) and One 6-Bit I/O Port
(PC)
1 = OUTPUT
DEFINES
PB0 - PB7
• 14-Bit Timer-Counter
00 = ALT1
11 = ALT2
01 = ALT3
10 = ALT4
DEFINES
PC0 - PC5
The IO/M (IO/Memory Select) pin selects either the five reg-
ister (Command, Status, PA0 - PA7, PB0 - PB7, PC0 - PC5)
or the memory (RAM) portion.
ENABLE PORT
A INTERRUPT
0 = INPUT
1 = OUTPUT
The 8-bit address on the Address/Data lines, Chip Enable
input CE or CE and IO/M are all latched on-chip at the falling
edge of ALE.
ENABLE PORT
B INTERRUPT
00 = NOP - DO NOT AFFECT COUNTER
OPERATION
01 = STOP - NOP IF TIMER HAS NOT
STARTED; STOP COUNTING IF
THE TIMER IS RUNNING
8-BIT INTERNAL DATA BUS
10 = STOP AFTER TC - STOP IMME-
DIATELY AFTER PRESENT TC
IS REACHED (NOP IF TIMER
HAS NOT STARTED)
TIMER
COMMAND
11 = START - LOAD MODE AND CNT
LENGTH AND START IMMEDIATE-
LY AFTER LOADING (IF TIMER IS
NOT PRESENTLY RUNNING). IF
TIMER IS RUNNING, START THE
NEW MODE AND CNT LENGTH
IMMEDIATELY AFTER PRESENT
TC IS REACHED.
PC
PB
PA
COMMAND
STATUS
TIMER
MSB
TIMER
LSB
6
8
8
TIMER MODE
FIGURE 3. COMMAND REGISTER BIT ASSIGNMENT
FIGURE 1. INTERNAL REGISTERS
Reading the Status Register
The status register consists of seven latches, one for each
bit six (0-5) for the status of the ports and one (6) for the
status of the timer.
CE (81C55RH)
OR
The status of the timer and the I/O section can be polled by
reading the Status Register (Address XXXXX000). Status
word format is shown in Figure 4. Note that you may never
write to the status register since the command register
shares the same I/O address and the command register is
selected when a write to that address is issued.
CE (81C56RH)
IO/M
AD0 - AD7
ALE
ADDRESS
DATA
VALID
AD7 AD6
TIMER
AD5 AD4 AD3 AD2 AD1 AD0
INTE
B
B
BF
INTR INTE
A
BF
INTR
A
B
A
RD OR WR
FIGURE 2. ON-BOARD MEMORY READ/WRITE CYCLE
PORT A
INTERRUPT
REQUEST
Programming of the Command Register
PORT A BUFFER
FULL/EMPTY
(INPUT/OUTPUT)
The command register consists of eight latches. Four bits (0-
3) define the mode of the ports, two bit (4-5) enable or disable
the interrupt from port C when it acts as control port, and the
last two bits (6-7) are for the timer.
PORT A INTERRUPT ENABLE
PORT B INTERRUPT REQUEST
PORT B BUFFER FULL/EMPTY
(INPUT/OUTPUT)
The command register contents can be altered at anytime by
using the I/O address XXXXX000 during a WRITE operation
with the Chip Enable active and IO/M = 1. The meaning of
each bit of the command byte is defined in Figure 3. The
contents of the command register may never be read.
PORT B INTERRUPT ENABLE
TIMER INTERRUPT (THIS BIT IS LATCHED HIGH WHEN
TERMINAL COUNT IS REACHED, AND IS RESET TO LOW
READING OF THE C/S REGISTER & BY HARDWARE RESET).
FIGURE 4. STATUS REGISTER BIT ASSIGNMENT
Spec Number 518056
10
HS-81C55RH, HS-81C56RH
When the ‘C’ port is programmed to either ALT3 or ALT4, the
control signals for PA and Pb are initialized as follows:
Input/Output Section
:
The I/O section of the HS-81C55RH and HS-81C56RH
consists of five registers: (See Figure 5)
CONTROL
BF
INPUT MODE
Low
OUTPUT MODE
• Command/Status Register (C/S) - Both register are
assigned the address XXXXX000. The C/S address
serves the dual prupose.
Low
High
INTR
Low
STB
Input Control
Input Control
When the C/S registers are selected during WRITE
operation, a command is written into the command
register. The contents of this register are not accessible
through the pins.
I/O ADDRESS†
A7 A6 A5 A4 A3 A2 A1 A0
SELECTION
When the C/S (XXXXX000) is selected during a READ
operation, the status information of the I/O ports and the
timer becomes available on the AD0 - AD7 lines.
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
Interval Command/
Status Register
General Purpose I/O
Port A
• PA Register - This register can be programmed to be
either input or output ports depending on the status of the
contents of the C/S Register. also depending on the
command, this port can operate in either the basic mode
or the strobed mode (See timing diagram). the I/O pins
assigned in relation to this register are PA0 - PA7. The
address of this register is XXXXX001.
General Purpose I/O
Port B
General Purpose I/O or
Control Port C
Low-Order 8 Bits of
Timer Count
• PB Register - This register functions the same as PA
Register. the I/O pins assigned are PB0 - PB7. The
address of this register is XXXXX010
High 6 Bits of Timer
Count and 2 Bits of Timer
Mode
• PC Register - This register has the address XXXXX011
and contains only 6 bits. The 6 bits can be programmed to
be either input ports, output ports or as control signals for
PA and PB by properly programming the AD2 and AD3
bits of the C/S register.
† I/O Address must be qualified by CE = 1(81C56RH) or CE =
0(81C55RH) and IO/M = 1 in order to select the appropriate register.
X = Don’t Care
FIGURE 5. I/O PORT AND TIMER ADDRESSING SCHEME
Figure 6 shows how I/O Ports A and B are structured within
the HS-81C55RH and HS-81C56RH.
When PC0 - PC5 is used as a control port, 3 bits are
assigned for Port A and 3 for Port B. The first bit is an
Interrupt that the HS-81C55RH and HS-81C56RH sends
out. The second is an output signal indicating whether the
buffer is full or empty, and the third is an input pin to
accept a strobe for the strobed input mode. (See Table 1).
Note in the diagram that when the I/O ports are programmed
to be output ports, the contents of the output ports can still
be read by
addressed.
a
READ operation when appropriately
HS-81C55RH AND HS-81C56RH
ONE BIT OF PORT A OR PORT B
(1) OUTPUT MODE
MULTIPLEXER
(2) SIMPLE INPUT
CONTROL
OUTPUT
LATCH
D
Q
(3) STROBED INPUT
(4) = 1 FOR OUTPUT MODE
= 0 FOR INPUT MODE
CLK
CLR
PA/PB
PIN
WRITE
PORT
(1)
(2)
(3)
MUX
MODE (4)
NOTES:
LATCH
1. READ Port = (IO/M = 1)(RD = 0)(CE Active)
Q
D
READ
PORT
(Port Address Selected)
CLK
2. WRITE Port = (IO/M = 1)(wr = 0)(CE Active)
(Port Address Selected)
STB
FIGURE 6. HS-81C55RH AND HS-81C56RH PORT FUNCTION
Spec Number 518056
11
HS-81C55RH, HS-81C56RH
The outputs of the HS-81C55/56RH are “glitch-free”
meaning that you can write a “1” to a bit position that was
previously “1” and the level at the output pin will not change.
TO HS-80C85RH
RST INPUT
PORT A OUTPUT
PORT A
Note also that the output latch is cleared when the port
enters the input mode. the output latch cannot be loaded by
writing to the port if the port is in theinput mode. The result is
that each time a port mode is changed from input to output,
the output pins will go low. When the HS-81C55/56RH is
RESET, the output latches are all cleared and all 3 ports
enter the input mode.
A INTR (SIGNAL DATA RECEIVED)
A BF (SIGNALS DATA READY)
A STB (ACKNOWL. DATA RCV’D)
B STB (LOAD PORT B LATCH)
B BF (SIGNALS BUFFER IS FULL)
TO/FROM
PERIPHERAL
INTERFACE
PORT C
When in the ALT1 or ALT2 modes, the bits of Port C are
structured like the diagram above in the simple input or
output mode, respectively.
B INTR (SIGNALS BUFFER
READY FOR READING)
TO INPUT PORT
(OPTIONAL)
PORT B
INPUT
Reading from an input port with nothing connected to the
pins will provide unpredictable results.
TO HS-80C85RH
RST INPUT
Figure 7 shows how the HS-81C55/56RH I/O ports might be
configured in a typical system.
FIGURE 7. EXAMPLE: COMMAND REGISTER = 00111001
Timer Section
The timer is a 14 bit down counter that counts the TIMER IN
pulses and provides either a square wave or pulse when
terminal count (TC) is reached.
7
6
5
4
3
2
1
0
M2 M1 T13 T12 T11 T10 T9 T8
The timer has the I/O address XXXXX100 for the low order
byte of the register and the I/O address XXXXX101 for the
high order byte of the register. (See Figure 5).
TIMER
MODE
MSB OF
CNT LENGTH
7
6
5
4
3
2
1
0
To program the timer, the COUNT LENGTH REG is loaded
first, one byte at a time, by selecting the timer addresses.
Bits 0-13 of the high order count register will specify the
length of the next count and bits 14-15 of the high order
register will specify the timer output mode (see Figure 8).
The value loaded into the count length register can have any
value from 2H through 3FFH in Bits 0-13.
T7
T6
T5
T4
T3
T2
T1
T0
LSB OF
CNT LENGTH
FIGURE 8. TIMER FORMAT
TABLE 1. PORT CONTROL ASSIGNMENT
PIN
PC0
PC1
PC2
PC3
PC4
PC5
ALT1
Input Port
Input Port
Input Port
Input Port
Input Port
Input Port
ALT2
ALT3
A INTR (Port A Interrupt)
A BF (Port A Buffer Full)
A STB (Port A Strobe)
Output Port
ALT4
Output Port
Output Port
Output Port
Output Port
Output Port
Output Port
A INTR (Port A Interrupt)
A BF (Port A Buffer Full)
A STB (Port A Strobe)
B INTR (Port B Interrupt)
B BF (Port B Buffer Full)
B STB (Port B Strobe)
Output Port
Output Port
Spec Number 518056
12
HS-81C55RH, HS-81C56RH
There are four modes to choose from: M2 and M1 define the
timer mode, as shown in Figure 9.
TIMER OUT WAVEFORMS:
4
START TERMINAL (TERMINAL
COUNT COUNT COUNT)
MODE BITS
M2 M1
5
FIGURE 10. ASYMMETRICAL SQUARE-WAVE OUTPUT RE-
SULTING FROM COUNT OF 9
0
0
1. SINGLE SQ.
WAVE
The counter in the HS-81C55/56RH is not initialized to any
particular mode or count when hardware RESET occurs, but
RESET does stop the counting. Therefore, counting cannot
begin following RESET until a START command is issued
via the C/S register.
2. CONTINUOUS
SQ. WAVE
0
1
1
0
3. SINGLE PULSE
ON TERM. COUNT
1
1
4. CONTINUOUS
PULSES
Please note that the timer circuit on the HS-81C55/56RH
chip is designed to be a square-wave timer, not an event
counter. To achieve this, it counts down by twos twice in
completing one cycle. Thus, its registers do not contain
values directly representing the number of TIMER IN pulses
received. You cannot load an initial value of 1 into the count
register and cause the timer to operate, as its terminal count
value is 10 (binary) or 2 (decimal). (For the detection of
single pulses, it is suggested that one of the hardware inter-
rupt pins on the HS-80C85RH be used.) After the timer has
started counting down, the values residing in the count
registers can be used to calculate the actual number of
TIMER IN pulses required to complete the timer cycle if
desired. To obtain the remaining count, perform the following
operations in order:
FIGURE 9. TIMER MODES
Bits 6-7 (TM2 and TM1) of command register contents are
used to start and stop the counter. there are four commands
to choose from:
TM2
TM1
0
0
0
1
NOP - Do not affect counter operation
STOP-NOP - If timer has not started; stop
counting if the timer is running
1
1
0
1
STOP AFTER TC - Stop immediately after
present TC is reached (NOP if timer has
not started)
1. Stop the count
START - Load mode and CNT length and
start immediately after loading (if timer is
not presently running). If timer is running,
start the new mode and CNT length imme-
diately after present TC is reached.
2. Read in the 16 bit value from the count length registers
3. Reset the upper two mode bits
4. Reset the carry and rotate right one position all 16 bits
through carry
5. If carry is set, add 1/2 of the full original count (1/2 full
count - 1 if full count is odd).
Note that while the counter is counting, you may load a new
count and mode into the count length registers. Before the
new count and mode will be used by the counter, you must
issue a START command to the counter. This applies even
thought you may only want to change the count and use the
previous mode.
NOTE: If you started with an odd count and you read the
count length register before the third count pulse occurs, you
will not be able to discern whether one or two counts has
occurred. Regardless of this, the HS-81C55/56RH always
counts out the right number of pulses in generating the
TIMER OUT waveforms.
In case of an odd-numbered count, the first half-cycle of the
squarewave output, which is high, is one count longer than
the second (low) half-cycle, as shown in Figure 10.
Spec Number 518056
13
HS-81C55RH, HS-81C56RH
Ceramic Metal Seal Flatpack Packages (Flatpack)
K42.A TOP BRAZED
42 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
E
N
1
INCHES
MIN
MILLIMETERS
A
A
e
SYMBOL
MAX
0.100
0.025
0.023
0.013
0.010
MIN
-
MAX
2.54
0.64
0.58
0.33
0.25
NOTES
D
A
b
-
-
-
-
-
-
0.017
0.017
0.007
0.
0.43
0.43
0.18
0.18
b
b1
c
E1
S1
C
L
c1
A
Q
007
E2
D
E
1.045
0.630
-
1.075
0.650
0.680
0.550
26.54
16.00
-
27.31
16.51
17.27
13.97
3
-
c1
LEAD FINISH
E1
E2
e
3
-
0.530
13.46
BASE
METAL
(c)
0.050 BSC
1.27 BSC
11
-
k
-
-
-
8.13
1.14
0.00
-
-
8.89
1.65
-
b1
M
L
0.320
0.045
0.000
-
0.350
0.065
-
-
M
(b)
Q
S1
M
N
8
6
-
SECTION A-A
NOTES:
0.0015
0.04
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark. Alternately, a tab (dimension k)
may be used to identify pin one.
42
42
-
Rev. 0 6/17/94
7. Forbottom-brazedleadpackages,noorganicorpolymericmaterials
shall be molded to the bottom of the package to cover the leads.
2. If a pin one identification mark is used in addition to a tab, the lim-
its of dimension k do not apply.
8. Dimension Q shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension Q minimum
shall be reduced by 0.0015 inch (0.038mm) maximum when sol-
der dip lead finish is applied.
3. This dimension allows for off-center lid, meniscus, and glass
overrun.
4. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness. The maximum lim-
its of lead dimensions b and c or M shall be measured at the cen-
troid of the finished lead surfaces, when solder dip or tin plate
lead finish is applied.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
11. The basic lead spacing is 0.050 inch (1.27mm) between center
lines. Each lead centerline shall be located within ±0.005 inch
(0.13mm) of its exact longitudinal position relative to lead 1 and
the highest numbered (N) lead.
5. N is the maximum number of terminal positions.
6. Measure dimension S1 at all four corners.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
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Intersil Corporation
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
Spec Number 518056
14
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