HS1-303BEH-Q [INTERSIL]
Radiation Hardened CMOS Dual SPDT Analog Switch;
| 型号： | HS1-303BEH-Q |
| 厂家： | 
Intersil |
| 描述： | Radiation Hardened CMOS Dual SPDT Analog Switch 光电二极管 |
| 文件： | 总5页 (文件大小：201K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Radiation Hardened CMOS Dual SPDT Analog Switch
HS-303ARH, HS-303AEH, HS-303BRH, HS-303BEH
The HS-303ARH, HS-303AEH, HS-303BRH, HS-303BEH analog
switches are monolithic devices fabricated using Intersil’s
Features
• QML, Per MIL-PRF-38535
• Radiation Performance
dielectrically isolated Radiation Hardened Silicon Gate (RSG)
process technology to insure latch-up free operation. They are
pinout compatible and functionally equivalent to the
HS-303RH, but offer improved 300kRAD(Si) total dose
capability. These switches offers low-resistance switching
performance for analog voltages up to the supply rails. “ON”
resistance is low and stays reasonably constant over the full
range of operating voltage and current. “ON” resistance also
stays reasonably constant when exposed to radiation.
Break-before-make switching is controlled by 5V digital inputs.
The HS-303ARH should be operated with nominal ±15V
supplies, while the HS-303BRH should be operated with
nominal ±12V supplies.
5
- Total Dose: 3x10 RAD(Si)
2
- SEE: For LET = 60MeV-mg/cm at 60° Incident Angle,
<150pC Charge Transferred to the Output of an Off Switch
• No Latch-Up, Dielectrically Isolated Device Islands
• Pinout and Functionally Compatible with Intersil HS-303RH
and HI-303 Series Analog Switches
• Analog Signal Range Equal to the Supply Voltage Range
• Low Leakage. . . . . . . . . . . . . . . . . . . . .100nA (Max, Post-Rad)
• Low r . . . . . . . . . . . . . . . . . . . . . . . . . . . 70Ω (Max, Post-Rad)
ON
• Low Standby Supply Current. . . . . . . . . . . . . +150µA/-100µA
(Max, Post-Rad)
Specifications
Specifications for Rad Hard QML devices are controlled by the
Defense Supply Center in Columbus (DSCC). The SMD numbers
listed below must be used when ordering.
Detailed Electrical Specifications for the HS-303ARH,
HS-303AEH, HS-303BRH, HS-303BEH are contained in
SMD 5962-95813. A “hot-link” is provided from our website for
downloading
Functional Diagram
Pin Configurations
HS1-303ARH, HS-303BRH
(SBDIP), CDIP2-T14
TOP VIEW
N
P
IN
1
2
3
4
5
6
7
14
13
12
11
10
9
V+
S4
D4
D2
S2
IN2
NC
S3
D
D3
D1
S1
TRUTH TABLE
SW1 AND SW2
OFF
IN1
GND
LOGIC
SW3 AND SW4
8
V-
0
1
ON
ON
OFF
HS-303ARH, HS-303AEH, HS-303BRH, HS-303BEH
(FLATPACK) CDFP3-F14
TOP VIEW
1
2
3
4
5
6
7
14
13
12
11
10
9
V+
S4
D4
D2
S2
IN2
V-
NC
S3
D3
D1
S1
IN1
GND
8
December 12, 2012
FN6411.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2006, 2008, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
HS-303ARH, HS-303AEH, HS-303BRH, HS-303BEH
Ordering Information
ORDERING NUMBER
TEMP. RANGE
PKG.
(Note)
PART NUMBER
HS1-303ARH-8
(°C)
PKG.
DWG. #
5962F9581304QCC
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
14 LD SBDIP
D14.3
5962F9581304QXC
5962F9581304V9A
5962F9581306V9A
5962F9581304VCC
5962F9581306VCC
5962F9581304VXC
HS0-303ARH/SAMPLE
HS1-303ARH/PROTO
HS9-303ARH/PROTO
5962F9581306VXC
5962F9581305QCC
5962F9581305QXC
5962F9581305V9A
5962F9581307V9A
5962F9581305VCC
5962F9581307VCC
5962F9581305VXC
HS0-303BRH/SAMPLE
HS1-303BRH/PROTO
HS9-303BRH/PROTO
5962F9581307VXC
HS9-303ARH-8
14 LD Flatpack
14 Ld SBDIP
14 Ld SBDIP
14 LD SBDIP
14 LD SBDIP
14 LD Flatpack
K14.A
D14.3
D14.3
D14.3
D14.3
K14.A
HS0-303ARH-Q
HS0-303AEH-Q
HS1-303ARH-Q
HS1-303AEH-Q
HS9-303ARH-Q
HS0-303ARH/SAMPLE
HS1-303ARH/PROTO
HS9-303ARH/PROTO
HS9-303AEH-Q
14 LD SBDIP
14 LD Flatpack
14 LD Flatpack
14 LD SBDIP
14 LD Flatpack
14 LD SBDIP
14 LD SBDIP
14 LD SBDIP
14 LD SBDIP
14 LD Flatpack
D14.3
K14.A
K14.A
D14.3
K14.A
D14.3
D14.3
D14.3
D14.3
K14.A
HS1-303BRH-8
HS9-303BRH-8
HS0-303BRH-Q
HS0-303BEH-Q
HS1-303BRH-Q
HS1-303BEH-Q
HS9-303BRH-Q
HS0-303BRH/SAMPLE
HS1-303BRH/PROTO
HS9-303BRH/PROTO
HS9-303BEH-Q
14 LD SBDIP
D14.3
K14.A
K14.A
14 LD Flatpack
14 LD Flatpack
NOTE: These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with
both SnPb and Pb-free soldering operations.
FN6411.2
December 12, 2012
2
HS-303ARH, HS-303AEH, HS-303BRH, HS-303BEH
Substrate:
Die Characteristics
DIE DIMENSIONS:
Radiation Hardened Silicon Gate,
Dielectric Isolation
2690µm x 5200µm (106mils x 205mils)
Thickness: 483µm ± 25.4µm (19mils ± 1mil)
Backside Finish:
Silicon
INTERFACE MATERIALS:
Glassivation:
ASSEMBLY RELATED INFORMATION:
Substrate Potential:
Type: PSG (Phosphorous Silicon Glass)
Unbiased (DI)
Thickness: 8.0kÅ ± 1.0kÅ
Top Metallization:
ADDITIONAL INFORMATION:
Worst Case Current Density:
Type: AlSiCu
Thickness: 16.0kÅ ± 2kÅ
5
2
<2.0 x 10 A/cm
Transistor Count:
196
Metallization Mask Layout
HS-303ARH, HS-303AEH, HS-303BRH, HS-303BEH
V-
V+
GND
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6411.2
December 12, 2012
3
HS-303ARH, HS-303AEH, HS-303BRH, HS-303BEH
Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
c1
LEAD FINISH
D14.3 MIL-STD-1835 CDIP2-T14 (D-1, CONFIGURATION C)
14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
-A-
-D-
E
INCHES
MIN
MILLIMETERS
BASE
METAL
(c)
SYMBOL
MAX
0.200
0.026
0.023
0.065
0.045
0.018
0.015
0.785
0.310
MIN
-
MAX
5.08
0.66
0.58
1.65
1.14
0.46
0.38
19.94
7.87
NOTES
b1
A
b
-
-
M
M
(b)
0.014
0.014
0.045
0.023
0.008
0.008
-
0.36
0.36
1.14
0.58
0.20
0.20
-
2
-B-
b1
b2
b3
c
3
SECTION A-A
S
S
S
D
bbb
C
A - B
-
D
4
BASE
S2
Q
PLANE
2
A
-C-
SEATING
PLANE
c1
D
3
L
-
S1
b2
eA
A A
E
0.220
5.59
-
e
eA/2
aaa
M C A - B S D S
b
c
e
0.100 BSC
2.54 BSC
-
eA
eA/2
L
0.300 BSC
0.150 BSC
7.62 BSC
3.81 BSC
-
ccc
M
C A - B S D S
-
NOTES:
0.125
0.200
3.18
0.38
0.13
0.13
5.08
-
1. Index area: A notch or a pin one identification mark shall be located ad-
jacent to pin one and shall be located within the shaded area shown.
The manufacturer’s identification shall not be used as a pin one identi-
fication mark.
Q
0.015
0.005
0.005
0.060
1.52
5
S1
S2
α
-
-
-
-
6
7
2. The maximum limits of lead dimensions b and c or M shall be measured
at the centroid of the finished lead surfaces, when solder dip or tin plate
lead finish is applied.
o
o
o
o
90
105
90
-
105
0.38
0.76
0.25
0.038
-
aaa
bbb
ccc
M
N
-
-
-
-
0.015
0.030
0.010
0.0015
-
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension M
applies to lead plating and finish thickness.
-
-
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial
-
2
lead paddle. For this configuration dimension b3 replaces dimension
b2.
14
14
8
5. Dimension Q shall be measured from the seating plane to the base plane.
6. Measure dimension S1 at all four corners.
Rev. 0 4/94
7. Measure dimension S2 from the top of the ceramic body to the nearest
metallization or lead.
8. N is the maximum number of terminal positions.
9. Braze fillets shall be concave.
10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
11. Controlling dimension: INCH.
FN6411.2
December 12, 2012
4
HS-303ARH, HS-303AEH, HS-303BRH, HS-303BEH
Ceramic Metal Seal Flatpack Packages (Flatpack)
K14.A MIL-STD-1835 CDFP3-F14 (F-2A, CONFIGURATION B)
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
A
A
e
INCHES MILLIMETERS
MIN
PIN NO. 1
ID AREA
SYMBOL
MAX
0.115
0.022
0.019
0.009
0.006
0.390
0.260
0.290
-
MIN
1.14
0.38
0.38
0.10
0.10
-
MAX
2.92
0.56
0.48
0.23
0.15
9.91
6.60
7.11
-
NOTES
D
A
b
0.045
0.015
0.015
0.004
0.004
-
-
-A-
-B-
S1
-
b1
c
-
-
b
c1
D
E
-
E1
3
0.004
Q
H
A - B
D
0.036
H
A - B
D
S
M
S
S
M
S
0.235
-
5.97
-
-
C
E
E1
E2
E3
e
3
-D-
A
0.125
0.030
3.18
0.76
-
-H-
-C-
-
-
7
L
E2
L
E3
E3
0.050 BSC
1.27 BSC
-
SEATING AND
BASE PLANE
c1
LEAD FINISH
k
0.008
0.270
0.026
0.005
-
0.015
0.370
0.045
-
0.20
6.86
0.66
0.13
-
0.38
9.40
1.14
-
2
L
-
BASE
METAL
Q
S1
M
N
8
(c)
6
b1
0.0015
0.04
-
M
M
(b)
14
14
-
SECTION A-A
Rev. 0 5/18/94
NOTES:
1. Index area: A notch or a pin one identification mark shall be located ad-
jacent to pin one and shall be located within the shaded area shown.
The manufacturer’s identification shall not be used as a pin one identi-
fication mark. Alternately, a tab (dimension k) may be used to identify
pin one.
2. If a pin one identification mark is used in addition to a tab, the limits of
dimension k do not apply.
3. This dimension allows for off-center lid, meniscus, and glass overrun.
4. Dimensions b1 and c1 apply to lead base metal only. Dimension M ap-
plies to lead plating and finish thickness. The maximum limits of lead
dimensions b and c or M shall be measured at the centroid of the fin-
ished lead surfaces, when solder dip or tin plate lead finish is applied.
5. N is the maximum number of terminal positions.
6. Measure dimension S1 at all four corners.
7. For bottom-brazed lead packages, no organic or polymeric materials
shall be molded to the bottom of the package to cover the leads.
8. Dimension Q shall be measured at the point of exit (beyond the menis-
cus) of the lead from the body. Dimension Q minimum shall be reduced
by 0.0015 inch (0.038mm) maximum when solder dip lead finish is
applied.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
FN6411.2
December 12, 2012
5
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