HS9-565BRH/PROTO [INTERSIL]
Radiation Hardened High Speed, Monolithic Digital-to-Analog Converter; 抗辐射高速，单片式数位类比转换器
| 型号： | HS9-565BRH/PROTO |
| 厂家： | 
Intersil |
| 描述： | Radiation Hardened High Speed, Monolithic Digital-to-Analog Converter |
| 文件： | 总7页 (文件大小：170K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HS-565BRH
®
Data Sheet
January 2003
FN4607.3
Radiation Hardened High Speed,
Features
Monolithic Digital-to-Analog Converter
• Electrically Screened to SMD # 5962-96755
• QML Qualified per MIL-PRF-38535 Requirements
• Total Dose . . . . . . . . . . . . . . . . . . . . . 100 krad (Si) (Max)
• DAC and Reference on a Single Chip
The HS-565BRH is a fast, radiation hardened 12-bit current
output, digital-to-analog converter. This part replaces the
HS-565ARH, which is no longer available. The monolithic
chip includes a precision voltage reference, thin-film R-2R
ladder, reference control amplifier and twelve high-speed
bipolar current switches.
• Pin Compatible with AD-565A and HI-565A
• Very High Speed: Settles to 0.50 LSB in 500ns Max
• Monotonicity Guaranteed Over Temperature
• 0.50 LSB Max Nonlinearity Guaranteed Over Temperature
• Low Gain Drift
The Intersil Corporation Dielectric Isolation process provides
latch-up free operation while minimizing stray capacitance
and leakage currents, to produce an excellent combination
of speed and accuracy. Also, ground currents are minimized
to produce a low and constant current through the ground
terminal, which reduces error due to code-dependent ground
currents.
o
(Max., DAC Plus Reference) . . . . . . . . . . . . . . .50ppm/ C
• ±0.75 LSB Accuracy Guaranteed Over Temperature
o
(±0.125 LSB Typical at 25 C)
HS-565BRH die are laser trimmed for a maximum integral
o
nonlinearity error of ±0.25 LSB at 25 C. In addition, the low
Applications
noise buried zener reference is trimmed both for absolute
value and minimum temperature coefficient.
• High Speed A/D Converters
• Precision Instrumentation
• Signal Reconstruction
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
Functional Diagram
Detailed Electrical Specifications for these devices are
contained in SMD 5962-96755. A “hot-link” is provided
on our website for downloading.
BIP.
REF OUT VCC
OFF.
8
11
4
3
20V
SPAN
+
Ordering Information
5K
5K
10V
10
9
10V
SPAN
-
9.95K
INTERNAL
TEMP. RANGE
IREF
o
ORDERING NUMBER
5962R9675502V9A
5962R9675502VJC
5962R9675502VXC
MKT. NUMBER
( C)
DAC
0.5mA
19.95K
6
5
REF
IN
OUT
IO
HS0-565BRH-Q
HS1-565BRH-Q
HS9-565BRH-Q
25
+
-
3.5K
3K
2.5K
(4X IREF
X CODE)
-55 to 125
-55 to 125
-55 to 125
REF
GND
7
12
HS9-565BRH/PROTO HS9-565BRH/PROTO
24 . . . 13
MSB LSB
-VEE PWR
GND
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
HS-565BRH
Pinouts
HS1-565BRH
MIL-STD-1835 CDIP2-T24
(SBDIP)
TOP VIEW
NC
NC
1
2
3
4
5
6
7
8
9
24 BIT 1 IN (MSB)
23 BIT 2 IN
22
VCC
BIT 3 IN
REF OUT
REF GND
REF IN
21 BIT 4 IN
20 BIT 5 IN
19 BIT 6 IN
18 BIT 7 IN
17 BIT 8 IN
16 BIT 9 IN
15 BIT 10 IN
14 BIT 11 IN
13 BIT 12 IN (LSB)
-VEE
BIPOLAR RIN
IDAC OUT
10V SPAN 10
20V SPAN 11
PWR GND 12
HS9-565BRH
MIL-STD-1835 CDFP4-F24
(CERAMIC FLATPACK)
TOP VIEW
BIT 1 IN
(MSB)
1
24
23
22
21
20
19
18
17
16
15
14
13
NC
NC
2
BIT 2 IN
BIT 3 IN
BIT 4 IN
BIT 5 IN
BIT 6 IN
BIT 7 IN
BIT 8 IN
BIT 9 IN
BIT 10 IN
BIT 11 IN
3
VCC
4
REF OUT
REF GND
REF IN
5
6
7
-VEE
8
BIPOLAR RIN
IDAC OUT
10V SPAN
20V SPAN
PWR GND
9
10
11
12
BIT 12 IN
(LSB)
2
HS-565BRH
Definitions of Specifications
Burn-In Bias Circuit
Digital Inputs
1
2
24
23
22
21
20
19
18
17
16
15
14
13
NC
BIT 1
BIT 2
BIT 3
F0
F1
The HS-565BRH accepts digital input codes in binary format
and may be user connected for any one of three binary
codes. Straight binary, Two’s Complement (see note below),
or Offset Binary, (See Operating Instructions).
NC
+15V
3
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
VCC
C1
D1
4
REF OUT BIT 4
REF GND BIT 5
5
DIGITAL
INPUT
ANALOG OUTPUT
6
REF IN
-VEE
BIT 6
BIT 7
BIT 8
BIT 9
-15V
D2
(NOTE)
TWO’S
7
STRAIGHT
BINARY
OFFSET
C2
C3
8
BIP OFF
OUT
MSB...LSB
000....000
100....000
111....111
011....111
BINARY
-FS (Full Scale)
Zero
COMPLEMENT
9
Zero
Zero
+10V
D3
10
11
12
10V SPAN BIT 10
20V SPAN BIT 11
PWR GND BIT 12
0.50 FS
-FS
+FS - 1LSB
+FS - 1LSB
Zero - 1LSB
+FS - 1LSB
0.50 FS - 1LSB Zero - 1LSB
NOTE: Invert MSB with external inverter to obtain Two’s
Complement Coding
NOTES:
Accuracy
D1 = D2 = D3 = IN4002 or Equivalent
F0 to F11:
VIH = 5.0V ±0.5V
VIL = 0.0V ±0.5V
F0 = 100kHz ±10% (50% Duty Cycle)
F1 = F0/2
F2 = F0/4
F3 = F0/8
F4 = F0/16
F5 = F0/32
F6 = F0/64
Nonlinearity - Nonlinearity of a D/A converter is an
important measure of its accuracy. It describes the deviation
from an ideal straight line transfer curve drawn between zero
(all bits OFF) and full scale (all bits ON).
F7 = F0/128
F8 = F0/256
F9 = F0/512
F10 = F0/1024
F11 = F0/2048
Differential Nonlinearity - For a D/A converter, it is the
difference between the actual output voltage change and the
ideal (1 LSB) voltage change for a one bit change in code. A
Differential Nonlinearity of ±1 LSB or less guarantees
monotonicity; i.e., the output always increases and never
decreases for an increasing input.
Radiation Bias Circuit
1
24
23
22
21
20
19
18
17
16
15
14
13
NC
BIT 1
BIT 2
BIT 3
Settling Time
2
NC
+15V
Settling time is the time required for the output to settle to
within the specified error band for any input code transition.
It is usually specified for a full scale or major carry transition,
settling to within 0.50 LSB of final value.
3
VCC
4
5
REF OUT
REF GND
REF IN
-VEE
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
+5V
6
-15V
Drift
7
Gain Drift - The change in full scale analog output over the
specified temperature range expressed in parts per million of
full scale range per C (ppm of FSR/ C). Gain error is
measured with respect to 25 C at high (TH) and low (TL)
8
BIP OFF
OUT
9
o
o
+10V
10
11
12
10V SPAN BIT 10
20V SPAN BIT 11
PWR GND BIT 12
o
temperatures. Gain drift is calculated for both high (TH -
o
o
25 C) and low ranges (25 C - TL) by dividing the gain error by
the respective change in temperature. The specification is the
larger of the two representing worst case drift.
Offset Drift - The change in analog output with all bits OFF
NOTE: Power Supply Levels are ±0.5V
over the specified temperature range expressed in parts per
o
o
million of full scale range per C (ppm of FSR/ C). Offset
o
error is measured with respect to 25 C at high (TH) and low
(TL) temperatures. Offset drift is calculated for both high (TH
o
o
- 25 C) and low (25 C - TL) ranges by dividing the offset
error by the respective change in temperature. The
specification given is the larger of the two, representing
worst case drift.
3
HS-565BRH
Power Supply Sensitivity
No Trim Operation
Power Supply Sensitivity is a measure of the change in gain
and offset of the D/A converter resulting from a change in -
15V or +15V supplies. It is specified under DC conditions
and expressed as parts per million of full scale range per
percent of change in power supply (ppm of FSR/%).
The HS-565BRH will perform as specified without calibration
adjustments. To operate without calibration, substitute 50Ω
resistors for the 100Ω trimming potentiometers: In Figure 1
replace R2 with 50Ω; also remove the network on pin 8 and
connect 50Ω to ground. For bipolar operation in Figure 2,
replace R3 and R4 with 50Ω resistors.
Compliance
With these changes, performance is guaranteed as shown
under Specifications, “External Adjustments”. Typical
unipolar zero will be ±0.50 LSB plus the op amp offset.
Compliance Voltage is the maximum output voltage range
that can be tolerated and still maintain its specified accuracy.
Compliance Limit implies functional operation only and
makes no claims to accuracy.
The feedback capacitor C must be selected to minimize
settling time.
Glitch
A glitch on the output of a D/A converter is a transient spike
resulting from unequal internal ON-OFF switching times.
Worst case glitches usually occur at half scale or the major
carry code transition from 011 . . . 1 to 100 . . . 0 or vice
versa. For example, if turn ON is greater than turn OFF for
011 . . . 1 to 100 . . . 0, an intermediate state of 000 . . . 0
exists, such that, the output momentarily glitches toward
zero output. Matched switching times and fast switching will
reduce glitches considerably.
R4
100Ω
R3
VCC
REF OUT
BIP.
100Ω
4
3
8
OFF.
11
10
20V SPAN
10V SPAN
HS-565BRH
+
-
5K
5K
10V
VO
IREF
9.95K
DAC
DAC
OUT
0.5mA
19.95K
6
5
C
-
IO
REF
IN
+
-
9
3.5K
3K
(4 x IREF
x CODE)
+
2.5K
Applying the HS-565BRH
REF
GND
R (SEE
TABLE 7)
OP AMP Selection
CODE
INPUT
The HS-565BRH’s current output may be converted to
voltage using the standard connections shown in Figures 1
and 2. The choice of operational amplifier should be
reviewed for each application, since a significant trade-off
may be made between speed and accuracy. Remember
settling time for the DAC-amplifier combination is
7
. . . . .
13
24
MSB
-VEE
LSB
PWR
GND
FIGURE 2. BIPOLAR VOLTAGE OUTPUT
2 2
) + (t )
(t
D
A
Calibration
where t , t are settling times for the DAC and amplifier.
Calibration provides the maximum accuracy from a
D
A
converter by adjusting its gain and offset errors to zero, For
the HS-565BRH, these adjustments are similar whether the
current output is used, or whether an external op amp is
added to convert this current to a voltage. Refer to Table 7
for the voltage output case, along with Figure 1 or 2.
+15V
100kΩ
100Ω
R1
50kΩ
R2
-15V
100Ω
VCC
REF OUT
BIP.
OFF.
4
3
8
11
Calibration is a two step process for each of the five output
ranges shown in Table 7. First adjust the negative full scale
(zero for unipolar ranges). This is an offset adjust which
translates the output characteristic, i.e. affects each code by
the same amount.
20V SPAN
HS-565BRH
+
-
5K
5K
10V
10
VO
10V SPAN
IREF
9.95K
DAC
19.95
K
DAC
OUT
0.5mA
6
5
C
-
IO
REF
IN
+
-
9
Next adjust positive FS. This is a gain error adjustment, which
rotates the output characteristic about the negative FS value.
3.5K
3K
(4 x IREF
x CODE)
+
2.5K
REF
GND
R (SEE
TABLE 7)
For the bipolar ranges, this approach leaves an error at the
zero code, whose maximum values is the same as for
integral nonlinearity error. In general, only two values of
output may be calibrated exactly; all others must tolerate
some error. Choosing the extreme end points (plus and
minus full scale) minimizes this distributed error for all other
codes.
CODE
INPUT
7
. . . . .
13
24
MSB
-VEE
LSB
PWR
GND
FIGURE 1. UNIPOLAR VOLTAGE OUTPUT
4
HS-565BRH
(Cases (b) and (c) may be eliminated unless the overshoot
exceeds 0.50 LSB). For example, refer to Figures 3A and 3B
for the measurement of case (d).
Settling Time
This is a challenging measurement, in which the result
depends on the method chosen, the precision and quality of
test equipment and the operating configuration of the DAC
(test conditions). As a result, the different techniques in use
by converter manufacturers can lead to consistently different
results. An engineer should understand the advantage and
limitations of a given test methods before using the specified
settling time as a basis for design.
Procedure
As shown in Figure 3B, settling time equals tX plus the
comparator delay (tD = 15ns). To measure tX,
• Adjust the delay on generator number 2 for a tX of several
microseconds. This assures that the DAC output has
settled to its final wave.
The approach used for several years at Intersil calls for a
strobed comparator to sense final perturbations of the DAC
output waveform. This gives the LSB a reasonable
magnitude (814mV for the HS-565BRH, which provides the
comparator with enough overdrive to establish an accurate
±0.50 LSB window about the final settled value. Also, the
required test conditions simulate the DACs environment for
a common application - use in a successive approximation
A/D converter. Considerable experience has shown this to
be a reliable and repeatable way to measure settling time.
• Switch on the LSB (+5V)
• Adjust the VLSB supply for 50% triggering at
COMPARATOR OUT. This is indicated by traces of equal
brightness on the oscilloscope display as shown in Figure
3B. Note DVM reading.
• Switch to LSB to Pulse (P)
• Readjust the VLSB supply for 50% triggering as before,
and note DVM reading. One LSB equals one tenth the
difference in the DVM readings noted above.
The usual specification is based on a 10V step, produced by
simultaneously switching all bits from off-to-on (tON) or on-
to-off (tOFF). The slower of the two cases is specified, as
measured from 50% of the digital input transition to the final
entry within a window of ±0.50 LSB about the settled value.
Four measurements characterize a given type of DAC:
• Adjust the VLSB supply to reduce the DVM reading by 5
LSBs (DVM reads 10X, so this sets the comparator to
sense the final settled value minus 0.50 LSB). Comparator
output disappears.
• Reduce generator number 2 delay until comparator output
reappears, and adjust for “equal brightness”.
(a) tON, to final value +0.50 LSB
(b) tON, to final value -0.50 LSB
(c) tOFF, to final value +0.50 LSB
(d) OFF, to final value -0.50 LSB
• Measure tX from scope as shown in Figure 3B. Settling
time equals tX + tD, i.e. tX + 15ns.
TABLE 1. OPERATING MODES AND CALIBRATION
CIRCUIT CONNECTIONS
CALIBRATION
OUTPUT
RANGE
PIN 10
TO
PIN 11
TO
RESISTOR
(R)
APPLY
INPUT CODE
MODE
ADJUST
TO SET VO
Unipolar (See Figure 1)
0 to +10V
0 to +5V
±10V
VO
VO
NC
VO
VO
Pin 10
Pin 9
VO
1.43K
1.1K
All 0’s
All 1’s
R1
R2
0V
+9.99756V
All 0’s
All 1’s
R1
R2
0V
+4.99878V
Bipolar (See Figure 2)
1.69K
1.43K
1.1K
All 0’s
All 1’s
R3
R4
-10V
+9.99512V
±5V
Pin 10
Pin 9
All 0’s
All 1’s
R3
R4
-5V
+4.99756V
±2.5V
All 0’s
All 1’s
R3
R4
-2.5V
+2.49878V
5
HS-565BRH
SYNC
IN
PULSE
GENERATOR
NO. 1
PULSE
GENERATOR
NO. 2
OUT
OUT
TRIG
OUT
C
20V ± 20%
BIAS
A
HS-565BRH
TURN ON
8
24
TURN OFF
11
23
.
.
.
5K
5K
+3V
0V
.
9.95K
10
9
.
50%
A
NC
.
DIGITAL
INPUT
.
.
-0.50LSB
STROBE IN
D
.
.
B
+
DAC
OUTPUT
0V
.
~100
kHz
COMPARATOR
OUT
.
B
.
-
14
-400mV
(TURN OFF)
2.5K
SETTLING TIME
tD = COMPARATOR DELAY
P
5
13
2mA
5V
tX
50%
COMP.
STROBE
2V
C
12
LSB
90
10
200K
0.8V
“EQUAL BRIGHTNESS”
VLSB
SUPPLY
DVM
0.1µF
COMP.
OUT
4V
D
0V
FIGURE 3A. .
FIGURE 3B.
Other Considerations
Grounds
Layout
The HS-565BRH has two ground terminals, pin 5 (REF GND)
and pin 12 (PWR GND). These should not be tied together
near the package unless that point is also the system signal
ground to which all returns are connected. (If such a point
exists, then separate paths are required to pins 5 and 12).
Connections to pin 9 (IOUT) on the HS-565BRH are most
critical for high speed performance. Output capacitance of the
DAC is only 20pF, so a small change of additional
capacitance may alter the op amp’s stability and affect settling
time. Connections to pin 9 should be short and few.
Component leads should be short on the side connecting to
pin 9 (as for feedback capacitor C). See the Settling Time
section.
The current through pin 5 is near zero DC (Note); but pin 12
carries up to 1.75mA of code - dependent current from bits
1, 2, and 3. The general rule is to connect pin 5 directly to
the system “quiet” point, usually called signal or analog
ground. Connect pin 12 to the local digital or power ground.
Then, of course, a single path must connect the
Bypass Capacitors
Power supply bypass capacitors on the op amp will serve
the HS-565BRH also. If no op amp is used, a 0.01µF
ceramic capacitor from each supply terminal to pin 12 is
sufficient, since supply current variations are small.
analog/signal and digital/power grounds.
NOTE: Current cancellation is a two step process within the
HS-565BRH in which code dependent variations are eliminated, the
resulting DC current is supplied internally. First an auxiliary 9-bit
R-2R ladder is driven by the complement of the DACs input code.
Together, the main and auxiliary ladders draw a continuous 2.25mA
from the internal ground node, regardless of input code. Part of the
DC current is supplied by the zener voltage reference, and the
remainder is sourced from the positive supply via a current mirror
which is laser trimmed for zero current through the external terminal
(pin 5).
6
HS-565BRH
Die Characteristics
DIE DIMENSIONS:
Backside Finish:
179 mils x 107 mils x 19 mils
Silicon
INTERFACE MATERIALS:
Glassivation:
ASSEMBLY RELATED INFORMATION
Substrate Potential:
Type: AlCu
Tie Substrate to VREF GND
Thickness: 8kÅ ±1kÅ
ADDITIONAL INFORMATION:
Worst Case Current Density:
Top Metallization:
5
2
Type: Al/Copper
Thickness: 16kÅ ±2kÅ
2.0 x 10 A/cm
Transistor Count:
Substrate:
200
Bipolar DI,
Metallization Mask Layout
HS-565BRH
(MSB)
BIT 1
VCC NC NC
A
BIT 2
3
3
1
VREF OUT
BIT 3
VREF
GND
BIT 4
BIT 5
VREF IN
-VS
BIT 6
BIPOLAR
12
BIT 7
BIT 8
IDAC
OUT
BIT 9
10V
SPAN
BIT 10
20V
SPAN
POWER
GND
BIT 12
(LSB)
BIT 11
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
7
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