HS9-80C85RH-Q_技术文档

HS-80C85RH

®

Data Sheet

August 2000

File Number 3036.3

Radiation Hardened 8-Bit CMOS

Microprocessor

Features

• Electrically Screened to SMD # 5962-95824

• QML Qualified per MIL-PRF-38535 Requirements

• Radiation Hardened EPI-CMOS

The HS-80C85RH is an 8-bit CMOS microprocessor

fabricated using the Intersil radiation hardened self-aligned

junction isolated (SAJI) silicon gate technology. Latch-up

free operation is achieved by the use of epitaxial starting

material to eliminate the parasitic SCR effect seen in

conventional bulk CMOS devices.

5

- Parametrics Guaranteed . . . . . . . . . . . 1 x 10 RAD(Si)

8

- Transient Upset . . . . . . . . . . . . . . . . >1 x 10 RAD(Si)/s

12

- Latch-up Free . . . . . . . . . . . . . . . . . >1 x 10 RAD(Si)/s

The HS-80C85RH is a functional logic emulation of the

HMOS 8085 and its instruction set is 100% software

compatible with the HMOS device. The HS80C85RH is

designed for operation with a single 5 volt power supply. Its

high level of integration allows the construction of a radiation

hardened microcomputer system with as few as three ICs

(HS-80C85RH CPU, HS83C55RH ROM I/O, and the

HS-81C55/56RH RAM I/O.

• Low Standby Current . . . . . . . . . . . . . . . . . . . .500µAMax

• Low Operating Current. . . . . . . . . . 5.0mA/MHz (X Input)

1

• Electrically Equivalent to Sandia SA 3000

• 100% Software Compatible with INTEL 8085

• Operation from DC to 2MHz, Post Radiation

• Single 5V Power Supply

Specifications for Rad Hard QML devices are controlled

by the Defense Supply Center in Columbus (DSCC). The

SMD numbers listed here must be used when ordering.

• On-Chip Clock Generator and System Controller

• Four Vectored Interrupt Inputs

• Completely Static Design

Detailed Electrical Specifications for these devices are

contained in SMD 5962-95824. A “hot-link” is provided

on our homepage for downloading.

• Self Aligned Junction Isolated (SAJI) Process

o

• Military Temperature Range. . . . . . . . . . . -55 C to 125 C

www.intersil.com/spacedefense/space.asp

Ordering Information

INTERNAL

MKT. NUMBER

TEMP. RANGE

o

ORDERING NUMBER

5962R9582401QQC

5962R9582401QXC

5962R9582401VQC

5962R9582401VXC

HS9-80C85RH/Proto

( C)

HS1-80C85RH-8

HS9-80C85RH-8

HS1-80C85RH-Q

HS9-80C85RH-Q

HS9-80C85RH/Proto

-55 to 125

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.

HS-80C85RH

Pinouts

40 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE

(SBDIP) MIL-STD-1835, CDIP2-T40

TOP VIEW

42 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE

(FLATPACK) INTERSIL OUTLINE K42.A

TOP VIEW

X1

X2

VDD

1

2

40

39

38

37

36

35

34

33

X1

X2

RESET

OUT

SOD

1

2

3

4

42

41

40

39

VDD

HOLD

HLDA

3

RESET OUT

SOD

HLDA

CLOCK

OUT

RESET

IN

READY

CLOCK OUT

4

SID

5

RESET IN

READY

SID

5

6

38

37

TRAP

6

TRAP

RST 7.5

RST 6.5

7

IO/ M

S1

RST 7.5

RST 6.5

7

8

36

35

IO/ M

8

S1

RST 5.5

INTR

INTA

AD0

9

32 RD

31 WR

RST 5.5

INTR

INTA

AD0

9

34

33

32

31

30

29

28

27

RD

10

11

12

13

14

10

11

12

13

14

15

16

WR

ALE

S0

30

29

28

27

26

25

24

23

ALE

S0

AD1

A15

A14

A13

A12

A11

A15

A14

AD2

AD3

A13

AD3

15

16

17

18

19

20

AD4

A12

A11

AD4

NC

AD5

17

18

19

26

25

24

A10

A9

AD6

A10

AD7

22 A9

AD6

AD7

20

21

23

22

A8

GND

A8

21

GND

Functional Diagram

RST RST RST

5.5 6.5 7.5 TRAP

INTA

INTR

SID

SOD

INTERRUPT CONTROL

SERIAL I/O CONTROL

8-BIT

INTERNAL DATA BUS

ACCUMU-

LATOR (8)

TEMP REG

(8)

FLAG (5)

FLIP FLOPS

INSTRUCTION

REGISTER (8)

B REG (8)

D REG (8)

H REG (8)

C REG (8)

E REG (8)

L REG (8)

STACK POINTER (16)

INSTRUCTION

DECODER

ARITHMETIC

LOGIC

UNIT

(ALU) (8)

PROGRAM COUNTER (16)

AND MACHINE

CYCLE

ENCODING

INCREMENTER

DECREMENTER

ADDRESS LATCH (16)

VDD

POWER

SUPPLY

GND

CLK

GEN

TIMING AND CONTROL

X1

X2

ADDRESS

DATA ADDRESS

BUFFER (8)

RESET

CONTROL

STATUS

DMA

BUFFER (8)

A15-A8

ADDRESS

BUS

AD1-AD0

ADDRESS

BUS

READY

WR

S0

IO/M

HLDA

HOLD

RESET

OUT

CLK

OUT

RD

ALE

S1

RESET

IN

2

HS-80C85RH

Pin Description

SYMBOL

NUMBER

TYPE

DESCRIPTION

A8 - A15

21-28

12-19

O

Address Bus: The most significant 8 bits of the memory address or the 8 bits of the I/O address,

three-stated during Hold and Halt modes and during RESET.

AD0-7

ALE

I/O

O

Multiplexed Address/Data Bus: Lower 8 bits of the memory address (or I/O address) appear on the bus

during the first clock cycle (T state) of a machine cycle. It then becomes the data bus during the second

and third clock cycles.

32

Address Latch Enable: It occurs during the first clock state of a machine cycle and enables the address

to get latched into the on-chip latch of peripherals. The falling edge of ALE is set to guarantee setup and

hold times for the address information. The falling edge of ALE can also be used to strobe the status

information. ALE is never three-stated.

S0, S1, and

IO/M

31, 35,

and 36

O

Machine Cycle Status:

IO/M

0

S1

0

S0

1

STATUS

Memory write

I/O write

0

1

0

1

0

1

0

I/O read

0

1

Opcode fetch

Interrupt acknowledge

Halt

1

T

0

T

X

Hold

T

Reset

T = three-State (high impedance)

X = Unspecified

S1 can be used as an advanced R/W status. IO/M, S0 and S1 become valid at the beginning of a machine

cycle and remain stable throughout the cycle. The falling edge of ALE may be used to latch the state of

these lines.

RD

34

33

O

Read Control: A low level on RD indicates the selected memory or I/O device is to be read and that the

Data Bus is available for the data transfer, three-stated during Hold and Halt modes and during RESET.

WR

Write Control: A low level on WR indicates the data on the Data Bus is to be written into the selected

memory or I/O location. Data is set up at the trailing edge of WR, three-stated during Hold and Halt modes

and during RESET.

READY

HOLD

35

39

I

Ready: If READY is high during a read or write cycle, it indicates that the memory or peripheral is ready

to send or receive data. If READY is low, the CPU will wait an integral number of clock cycles for READY

to go high before completing the read or write cycle. READY must conform to specified setup and hold

times.

Hold: Indicates that another master is requesting the use of the address and data buses. The CPU, upon

receiving the hold request, will relinquish the use of the bus as soon as the completion of the current bus

transfer. Internal processing can continue. The processor can regain the bus only after the HOLD is

removed. When the HOLD is acknowledged, the Address, Data Bus, RD, WR, and IO/M lines are

3-stated.

HLDA

INTR

38

10

O

I

Hold Acknowledge: Indicates that the CPU has received the HOLD request and that it will relinquish the

bus in the next clock cycle. HLDA goes low after the Hold request is removed. The CPU takes the bus

one half clock cycle after HLDA goes low.

Interrupt Request: Is used as a general purpose interrupt. It is sampled only during the next to the last

clock cycle of an instruction and during Hold and Halt states. If it is active, the Program Counter (PC) will

be inhibited from incrementing and an INTA will be issued. During this cycle a RESTART or CALL

instruction can be inserted to jump to the interrupt service routine. The INTR is enabled and disabled by

software. It is disabled by Reset and immediately after an interrupt is accepted.

3

HS-80C85RH

Pin Description (Continued)

SYMBOL

NUMBER

TYPE

DESCRIPTION

INTA

11

O

Interrupt Acknowledge: Is used instead of (and has the same timing as) RD during the Instruction cycle

after an INTR is accepted. It can be used to activate an 8259A Interrupt chip or some other interrupt port.

RST 5.5

RST 6.5

RST 7.5

9

8

7

I

Restart Interrupts: These three inputs have the same timing as INTR except they cause an internal

RESTART to be automatically inserted.

The priority of these interrupts is ordered as shown in Table 6. These interrupts have a higher priority than

INTR. In addition, they may be individually masked out using the SIM instruction.

TRAP

6

I

Trap: Trap interrupt is a non-maskable RESTART interrupt. It is recognized at the same time as INTR or

RST 5.5-7.5. It is unaffected by any mask or Interrupt Enable. It has the highest priority of any interrupt.

(See Table 6.)

RESET IN

36

Reset In: Sets the Program Counter to zero and resets the Interrupt Enable and HLDA flip-flops. The data

and address buses and the control lines are three-stated during RESET and because of the

asynchronous nature of RESET the processor’s internal registers and flags may be altered by RESET

with unpredictable results. RESET IN is a Schmitt-triggered input, allowing connection to an R-C network

for power-on RESET delay (see Figure 1). Upon power-up, RESET IN must remain low for at least 10

“clock cycle” after minimum VDD has been reached. For proper reset operation after the power-up

duration, RESET IN should be kept low a minimum of three clock periods. The CPU is held in the reset

condition as long as RESET IN is applied.

RESET OUT

3

O

Reset Out: Reset Out indicates CPU is being reset. Can be used as a system reset. The signal is

synchronized to the processor clock and lasts an integral number of clock periods.

X1

X2

1

2

I

O

X1 and X2: Are connected to a crystal, LC, or RC network to drive the internal clock generator. X, can

also be an external clock Input from a logic gate. The input frequency is divided by 2 to give the

processor’s internal operating frequency.

CLK

SID

37

5

O

I

Clock: Clock output for use as a system clock. The period of CLK is twice the X1, X2 input period.

Serial Input Data Line: The data on this line is loaded into accumulator bit 7 whenever a RIM instruction

is executed.

SOD

VCC

GND

4

O

I

Serial Output Data Line: The output SOD is set or reset as specified by the SlM instruction.

40

20

Power: +5V supply.

Ground: Reference.

I

RESET IN

C1

R1

VDD

TYPICAL POWER-ON RESET RC VALUES (NOTE)

R1 = 75kΩ

C1 = 1µF

NOTE: Values may have to vary due to applied power supply ramp up time.

FIGURE 1. POWER-ON RESET CIRCUIT

4

HS-80C85RH

Waveforms

X

INPUT

1

t2

t

f

r

CLK

OUTPUT

t1

tXKR

tXKF

tCYC

FIGURE 2. CLOCK

T1

T2

T3

T1

CLK

tLCK

tCA

A

ADDRESS

8-15

tRAE

tAD

tRDH

DATA IN

AD -AD

0

7

tLL

tLA

tCL

tAFR

tLDR

tRD

ALE

tAL

tCC

RD/INTA

tLC

tAC

FIGURE 3. READ

T1

T2

T3

T1

CLK

tLCK

A

ADDRESS

tLDW

8-15

tCA

DATA OUT

AD -AD

0

7

ADDRESS

tLA

tLL

tAL

tDW

tWD

ALE

WR

tWDL

tCC

tLC

tCL

tAC

FIGURE 4. WRITE

5

HS-80C85RH

Waveforms (Continued)

T2

THOLD

T1

CLK

HOLD

HLDA

tHDS

tHACK

tHDH

tHABF

tHABE

BUS

(ADDRESS, CONTROLS)

FIGURE 5. HOLD

T1

T2

TWAIT

T3

CLK

tLCK

tCA

A

ADDRESS

8-15

tRAE

tAD

tRDH

DATA IN

ADDRESS

tLA

AD -AD

0

7

tLL

tCL

tAFR

tLDR

ALE

tAL

tRD

tCC

tLC

RD/INTA

tLRY

tAC

tARY

tRYS tRYH

READY

NOTE: READY must remain stable during setup and hold times.

FIGURE 6. READ OPERATION WITH WAIT CYCLE (TYPICAL) - SAME READY TIMING APPLIES TO WRITE

T1

T2

T3

T4

T5

T6

THOLD T1

T2

A8-15

A0-7

CALL INST.

BUS FLOATING (NOTE)

RD

INTR

tHABE

INTR

tINS

tINH

HOLD

tHDH

tHDS

HLDA

tHABF

tHACK

NOTE: IO/M is also floating during this time.

FIGURE 7. INTERRUPT AND HOLD

6

HS-80C85RH

TABLE 1. ELECTRICAL PERFORMANCE CHARACTERISTICS

(NOTE 1)

o

PARAMETER

Input Capacitance

SYMBOL

CIN

CONDITIONS

VDD = Open, f = 1MHz

TEMPERATURE ( C)

MIN

MAX

12

UNITS

pF

T

= 25

-

A

I/O Capacitance

Output Capacitance

NOTE:

CI/O

13

pF

COUT

12

pF

1. All measurements referenced to device ground.

TABLE 2. INTERRUPT PRIORITY, RESTART ADDRESS, AND SENSITIVITY

ADDRESS BRANCHED TO (1) WHEN

NAME

PRIORITY

INTERRUPT OCCURS

TYPE TRIGGER

Rising edge and high level until sampled.

Rising edge (latched).

TRAP

1

2

3

4

5

24H

3CH

RST 7.5

RST 6.5

RST 5.5

INTR

34CH

High level until sampled.

2CH

High level until sampled.

See Note 2

High level until sampled.

NOTES:

2. The processor pushes the PC on the stack before branching to the indicated address.

3. The address branched to depends on the instruction provided to the CPU when the interrupt is acknowledged.

TABLE 3. BUS TIMING SPECIFICATION AS A t

DEPENDENT

CYC

SYMBOL

tAL

HS-8OC85RH

(1/2)T- 175

SYMBOL

tCC

HS-8OC85RH

(3/2 + N)T - 175

Minimum

Maximum

Minimum

tLA

(1/2)T- 175

tCL

(1/2)T - 190

(3/2)T - 500

(1/2)T - 160

(1/2)T +125

(2/2)T - 200

(1/2)T-210

tLL

(1/2)T-50

tARY

tHACK

tHABF

tHABE

tAC

Maximum

Minimum

Maximum

Minimum

Maximum

tLCK

tLC

(1/2)T- 125

(1/2)T- 100

tAD

(5/2 + N)T - 375

(3/2 + N)T - 375

(1/2)T- 130

tRD

tRAE

tCA

t1

(1/2)T - 100

(3/2 + N)T - 175

(1/2)T-100

t2

(1/2)T- 150

(3/2)T - 200

(4/2)T - 325

tDW

tWD

tRV

tLDR

NOTE: N is equal to the total WAIT states T = tCYC.

7

HS-80C85RH

TABLE 4. INSTRUCTION SET SUMMARY

INSTRUCTION CODE

TABLE 4. INSTRUCTION SET SUMMARY (Continued)

INSTRUCTION CODE

MNE-

MONIC

OPERATIONS

MNE-

OPERATIONS

DESCRIPTION

D

DESCRIPTION

MONIC

RNZ

RP

D

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1 0

MOVE, LOAD, AND STORE

1

0

Return on no zero

Return on positive

Return on minus

MOVr1,

r2

0

1

0

D

S

Move register to

register

1

0

1

0

RM

MOV M.r

MOV r.M

MVl r

1

0

D

0

S

1

0

S

1

0

S

0

1

Move register to

memory

RPE

Return on parity

even

D

1

D

1

Move memory to

register

RPO

1

0

1

0

1

0

1

Return on parity

odd

Move immediate

register

RESTART

RST

1

A

Restart

MVl M

LXl B

Move immediate

memory

INPUT/OUTPUT

IN

1

0

1

0

1

Input

0

Load immediate

register Pair B & C

OUT

Output

LXl D

0

1

0

Load immediate

register Pair D & E

INCREMENT AND DECREMENT

INR r

0

D

1

D

1

D

0

1

0

1

0

1

Increment register

Decrement register

Increment memory

LXl H

1

0

Load immediate

DCR r

INR M

DCR M

register Pair H & L

STAX B

STAX D

LDAX B

LDAX D

STA

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Store A indirect

Load A indirect

Store A direct

1

0

Decrement

memory

INX B

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Increment B & C

registers

INX D

POP B

POP D

POP H

Increment D & E

registers

LDA

Load A direct

Pop register Pair

B & C off stack

SHLD

LHLD

Store H & L direct

Load H & L direct

Pop register Pair

D & E off stack

XCHG

Exchange D & E,

H & L Registers

Popregister Pair

H & L off stack

STACK OPS

PUSH B

PUSH D

PUSH H

1

0

1

0

1

0

1

0

1

0

1

Push register Pair

B & C on stack

POP

PSW

Pop A and Flags

off stack

1

Push register Pair

D & E on stack

XTHL

Exchange top ot

stack, H & L

1

Push register Pair

H & L on stack

SPHL

H & L to stack

pointer

PUSH

PSW

Push A and Flags

on stack

LXI SP

INX SP

DCX SP

Load immediate

stack pointer

CZ

1

0

1

0

1

0

1

0

1

0

1

0

Call on zero

Increment stack

pointer

CNZ

CP

1

Call on no zero

Call on positive

Call on minus

Decrement stack

pointer

CM

JUMP

CPE

CPO

RETURN

RET

RC

Call on parity even

Call on parity odd

JMP

1

0

1

Jump

unconditional

JC

1

0

1

0

1

0

1

0

1

0

Jump on carry

1

0

1

0

1

0

1

0

1

0

Return

JNC

JZ

Jump on no carry

Jump on zero

Return on carry

Return on no carry

Return on zero

RNC

RZ

JNZ

JP

Jump on no zero

Jump on positive

8

HS-80C85RH

TABLE 4. INSTRUCTION SET SUMMARY (Continued)

INSTRUCTION CODE

TABLE 4. INSTRUCTION SET SUMMARY (Continued)

INSTRUCTION CODE

MNE-

OPERATIONS

DESCRIPTION

MNE-

OPERATIONS

DESCRIPTION

MONIC

D

MONIC

ADD M

ADC M

D

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1 0

JM

1

0

1

0

Jump on minus

1

0

C

0

1

0

Add memory to A

JPE

1

0

1

0

1

0

Jump on parity

even

1

0

1

0

Add memory to A

with carry

JPO

1

0

1

0

1

0

1

Jump on parity odd

ADl

ACl

1

0

1

0

Add immediate to A

PCHL

H & L to program

counter

Add immediate to

A with carry

CALL

CC

DAD B

DAD D

DAD H

DAD SP

0

1

0

1

0

1

0

1

Add B & C to H & L

Add D & E to H & L

Add H & L to H & L

1

0

1

0

1

0

1

0

Call unconditional

Call on carry

CNC

Call on no carry

Add stack pointer

to H & L

LOGICAL

ANA r

XRA r

SUBTRACT

1

0

1

0

1

S

And register with A

SUB r

SBB r

SUB M

SBB M

SUl

1

0

1

0

1

0

1

0

1

0

1

S

1

S

1

S

0

Subtract register

from A

Exclusive OR

register with A

Subtract register

from A with borrow

ORA r

CMP r

1

0

1

0

1

S

OR register with A

Compare register

with A

Subtract memory

from A

ANA M

XRA M

1

0

1

0

1

0

And memory with A

Subtract memory

from A with borrow

Exclusive OR

memory with A

Subtract

immediate from A

ORA M

CMP M

1

0

1

0

1

0

OR memory with A

Compare memory

with A

SBl

Subtract

immediate from A

with borrow

ANI

XRI

ORl

CPl

1

0

1

0

1

0

1

0

And immediate

with A

SPECIALS

CMA

STC

Exclusive OR

immediate with A

0

1

0

1

0

1

0

1

0

1

Complement A

Set carry

OR immediate

with A

CMC

DAA

Complement carry

Decimal adjust A

Compare

immediate with A

CONTROL

El

ROTATE

RLC

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Enable Interrupts

Disable Interrupt

No-operation

Halt

0

1

0

1

0

1

Rotate A left

DI

RRC

Rotate A right

NOP

RAL

Rotate A left

through carry

HLT

RIM

Read Interrupt

Mask

RAR

0

1

0

1

0

1

0

1

Rotate A right

through carry

SlM

0

1

0

Set Interrupt Mask

INX H

Increment H & L

registers

NOTES:

4. DDS or SSS: B000, C001, D010, E011, H100, L101, Memory

110, A111

DCX B

DCX D

DCX H

ADD

0

1

0

1

0

1

0

1

Decrement B & C

Decrement D & E

Decrement H & L

5. Two possible cycle times (6/12) indicate instruction cycles

dependent on condition flags.

† All mnemonics copyrighted, Intel Corporation 1976

ADD r

ADC r

1

0

1

S

Add register to A

with carry

9

HS-80C85RH

Interrupt and Serial I/O

Functional Description

The HS-80C85RH has 5 interrupt inputs: INTR, RST 5.5, RST

6.5, RST 7.5, and TRAP INTR is maskable (can be enabled or

disabled by El or Dl software instructions), and causes the CPU

to fetch in an RST instruction, externally placed on the data

bus, which vectors a branch to any one of eight fixed memory

locations (Restart addresses). The decimal addresses of these

dedicated locations are: 0, 8, 16, 24, 32, 40, 48, and 56. Any of

these addresses may be used to store the first instruction(s) of

a routine designed to service the requirements of an

interrupting device. Since the (RST) is a call, completion of the

instruction also stores the old program counter contents on the

STACK. Each of the three RESTART inputs, 5.5, 6.5, and 7.5,

has a programmable mask. TRAP is also a RESTART interrupt

but it is nonmaskable.

The HS-80C85RH is a complete 8-bit parallel central

processing unit implemented in a self aligned, silicon gate,

CMOS technology. Its static design allows the device to be

operated at any external clock frequency from a maximum of

4MHz down to DC. The processor clock can be stopped in

either the high or low state and held there indefinitely. This

type of operation is especially useful for system debug or

power critical applications. The device is designed to fit into

a minimum system of three ICs: CPU (HS-80C85RH),

RAM/IO (HS-81C55/56RH) and ROM/IO Chip

(HS-83C55RH).

Since the HS-80C85RH is implemented in CMOS, all of the

advantages of CMOS technology are inherent in the device.

These advantages include low standby and operating

power, high noise immunity, moderately high speed, wide

operating temperature range, and designed-in radiation

hardness. Thus the HS-80C85RH is ideal for weapons and

space applications.

The three maskable interrupts cause the internal execution

of RESTART (saving the program counter in the stack and

branching to the RESTART address) if the interrupts are

enabled and if the interrupt mask is not set. The

nonmaskable TRAP causes the internal execution of a

RESTART vector independent of the state of the interrupt

enable or masks. (See Table 9.)

The HS-80C85RH has twelve addressable 8-bit registers.

Four of them can function only as two 16-bit register pairs.

Six others can be used interchangeably as 8-bit registers or

as 16-bit register pairs. The HS-80C85RH register set is as

follows:

There are two different types of inputs in the restart

interrupts. RST 5.5 and RST 6.5 are high level-sensitive and

are recognized with the same timing as INTR. RST 7.5 is

rising edge sensitive.

MNEMONIC

ACC or A

REGISTER

Accumulator

CONTENTS

8 bits

For RST 7.5, only a pulse is required to set an internal flip-flop

which generates the internal interrupt request (a normally high

level signal with a low going pulse is recommended for

highest system noise immunity). The RST 7.5 request flip-flop

remains set until the request is serviced. Then it is reset

automatically. This flip-flop may also be reset by using the

SlM instruction or by issuing a RESET IN to the 80C85RH.

The RST 7.5 internal flip-flop will be set by a pulse on the RST

7.5 pin even when the RST 7.5 interrupt is masked out.

PC

Program Counter

16-bit Address

BC, DE, HL

General-Purpose

Registers; Data

Pointer (HL)

8 bits x 6 or

16 bits x 3

SP

Stack Pointer

Flag Register

16-bit Address

Flags or F

5 Flags (8-bit space)

The status of the three RST interrupt masks can only be

affected by the SIM instruction and RESET IN.

The HS-80C85RH uses a multiplexed Data Bus. The

address is split between the higher 8-bit Address Bus and

the lower 8-bit Address/Data Bus. During the first T state

(clock cycle) of a machine cycle the low order address is

sent out on the Address/Data bus. These lower 8 bits may

be latched externally by the Address Latch Enable signal

(ALE). During the rest of the machine cycle the data bus is

used for memory or I/O data.

The interrupts are arranged in a fixed priority that determines

which interrupt is to be recognized if more than one is

pending as follows: TRAP-highest priority, RST 7.5, RST

6.5, RST 5.5, INTR-lowest priority. This priority scheme does

not take into account the priority of a routine that was started

by a higher priority interrupt. RST 5.5 can interrupt an RST

7.5 routine if the interrupts are re-enabled before the end of

the RST 7.5 routine.

The HS-80C85RH provides RD, WR, S0, S1, and IO/M

signals for bus control. An Interrupt Acknowledge signal

(INTA) is also provided. HOLD and all Interrupts are

synchronized with the processor’s internal clock. The

HS-80C85RH also provides Serial Input Data (SID) and

Serial Output Data (SOD) lines for simple serial interface.

The TRAP interrupt is useful for catastrophic events such as

power failure or bus error. The TRAP input is recognized just

as any other interrupt but has the highest priority. It is not

affected by any flag or mask. The TRAP input is both edge

and level sensitive. The TRAP input must go high and

remain high until it is acknowledged. It will not be recognized

again until it goes low, then high again. This avoids any false

triggering due to noise or logic glitches. Figure 8 illustrates

In addition to these features, the HS-80C85RH has three

maskable, vector interrupt pins, one nonmaskable TRAP

interrupt, and a bus vectored interrupt, INTR.

10

HS-80C85RH

the TRAP interrupt request circuitry within the HS-80C85RH.

Note that the servicing of any interrupt (TRAP, RST 7.5, RST

6.5, RST 5.5, INTR) disables all future interrupts (except

TRAPs) until an EI instruction is executed.

1. A 20pF capacitor should be connected from X2 to ground

to assure oscillator start-up at the correct frequency.

2. A 10MΩ resistor is required between X1 and X2 for bias

point stabilization. In addition, the crystal should have the

following characteristics:

INSIDE THE

EXTERNAL

1) Parallel resonance at twice the desired internal clock

frequency

2) CL (load capacitance) ≤ 30pF

3) CS (shunt capacitance) ≤ 7pF

4) RS (equivalent shunt resistance) ≤ 75Ω

5) Drive level: 10mW

80C85RH

TRAP

INTERRUPT

REQUEST

TRAP

RESET IN

RESET

SCHMITT

TRIGGER

INTERRUPT

REQUEST

CLK

D

VDD

Q

6) Frequency tolerance: ±0.005% (suggested)

D

F/F

A parallel-resonant LC circuit may be used as the frequency-

determining network for the HS-80C85RH, providing that its

frequency tolerance of approximately ±10% is acceptable.

The components are chosen from the formula:

CLEAR

TRAP F.F.

INTERNAL

TRAP

ACKNOWLEDGE

1

f = ----------------------------------------------------

FIGURE 8. TRAP AND RESET IN CIRCUIT

2π L(Cext + Cint)

The TRAP interrupt is special in that is disables interrupts, but

preserves the previous interrupt enable status. Perform- ing

the first RIM instruction following a TRAP interrupt allows you

to determine whether interrupts were enabled or disabled

prior to the TRAP. All subsequent RIM instructions provide

current interrupt enable status. Performing a RIM instruction

following INTR, or RST 5.5-7.5 will provide current interrupt

enable status, revealing that interrupts are disabled.

To minimize variations in frequency, it is recommended that

you choose a value for Cext that is at least twice that of Cint,

or 30pF. The use of an LC circuit is not recommended for

frequencies higher than approximately 4MHz.

An RC circuit may be used as the frequency-determining

network for the HS-80C85RH if maintaining a precise clock

frequency is of no importance. Variations in the on-chip timing

generation can cause a wide variation in frequency when

using the RC mode. Its advantage is its low component cost.

The driving frequency generated by the circuit shown is

approximately 3MHz. It is not recommended that frequencies

greatly higher or lower than this be attempted.

The serial I/O system is also controlled by the RIM and SIM

instructions. SID is read by RIM, and SIM sets the SOD data.

Driving the X1 and X2 Inputs

You may drive the clock inputs of the HS-80C85RH with a

crystal, an LC tuned circuit, an RC network, or an external clock

source. The driving frequency may be any value from DC to

4MHz and must be twice the desired internal clock frequency.

Figure 9 shows the recommended clock driver circuits.

For driving frequencies up to and including 4MHz you may

supply the driving signal to X1 and leave X2 open-circuited

(Figure 9D).

The following guidelines should be observed when a crystal

is used to drive the HS-80C85RH clock input:

80C85RH

X1

X2

X1

1

2

20pF

REXT =

10MΩ

CINT =

15pF

-6K

2

20pF

X2

FIGURE 9A. QUARTZ CRYSTAL CLOCK DRIVER

FIGURE 9B. RC CIRCUIT CLOCK DRIVER

LOW TIME > 60ns

X1

80C85RH

X1

1

CINT =

15pF

LEXT

CEXT

2

X2

(NOTE)

NOTE: X2 Left Floating.

FIGURE 9C. LC TUNED CIRCUIT CLOCK DRIVER

FIGURE 9D. 0-4MHz INPUT FREQUENCY EXTERNAL CLOCK

DRIVER CIRCUIT

FIGURE 9. CLOCK DRIVER CIRCUITS

11

HS-80C85RH

HS-80C85RH Caveats

Generating An HS-80C85RH Wait State

1. An important caveat that is applicable to CMOS devices

in general is that unused inputs should never be left

floating. This rule also applies to inputs connected to a

three-state bus. The need for external pull-up resistors

during three-state bus conditions is eliminated by the

presence of regenerative latches on the following

HS-80C85RH output pins: AD0-AD7, A8-A15, and IO/M.

Figure 10 depicts an output and corresponding

If your system requirements are such that slow memories or

peripheral devices are being used, the circuit shown in

Figure 11 may be used to insert one WAIT state in each

HS-80C85RH machine cycle.

The D flip-flops should be chosen so that:

1. CLK is rising edge-triggered

2. CLEAR is low-level active

regenerative latch. When the output driver assumes the

high impedance state, the latch holds the bus in whatever

logic state (high or low) it was before the three-state

condition. A transient drive current of approximately

±1.0mA at 0.5VDD for 10ns is required to switch the

latch. Thus, CMOS device inputs connected to the bus

are not allowed to float during three-state conditions.

The READY line is used to extend the read and write pulse

lengths so that the 80C85RH can be used with slow

memory. HOLD causes the CPU to relinquish the bus when

it is through with it by floating the Address and Data Buses.

TO

80C85RH

2. The RD and WR pins of the HS-80C85RH contain internal

dynamic pull-up transistors to avoid spurious selection of

memory devices when the RD and WR pins assume the

high impedance state. This eliminates the need for

external resistive pull-ups on these pins.

CLEAR

80C85RH

READY

INPUT

CLK

ALE

(NOTE)

CLK

D

OUTPUT

“D”

F/F

“D”

F/F

Q

VDD

D

NOTE: ALE and CLK (OUT) should be buffered if CLK input of latch

exceeds 80C85RH IOL or IOH.

3. The RESET IN and X1 inputs on the HS-80C85RH are

schmit trigger inputs. This eliminates the possibility of

internal oscillations in response to slow rise time input

signals at these pins.

FIGURE 11. GENERATION OF A WAIT STATE FOR

HS-80C85RH CPU

4. A high frequency bypass capacitor of approximately

0.1µF should be connected between VDD and GND to

shunt power supply transients.

System Interface

The HS-80C85RH family includes memory components,

which are directly compatible to the HS-8OC8SRH CPU. For

example, a system consisting of the three radiation-

hardened chips, HS-80C85RH, HS-81C56RH, and

HS-83C55RH will have the following features:

5. The HS-80C85RH is functional within 10 input clock

cycles after application of power (assuming that reset has

been asserted from power-on). Start up conditions in the

crystal controlled oscillator mode must also account for

the characteristics of the oscillator.

1. 2K Bytes ROM

2. 256 Bytes RAM

3. 1 Timer/Counter

4. 4 8-bit I/O Ports

5. 1 6-bit I/O Port

OUTPUT

DRIVER

6. 4 Interrupt Levels

7. Serial In/Serial Out Ports

REGENERATIVE

LATCH

This minimum system, using the standard I/O technique is

as shown in Figure 12.

FIGURE 10. OUTPUT DRIVER AND LATCH FOR PINS

AD0-AD7, A8-A15 AND IO/M

In addition to standard 1/0, the memory mapped I/O offers

an efficient I/O addressing technique. With this technique, an

area of memory address space is assigned for I/O address,

thereby, using the memory address for I/O manipulation.

Figure 13 shows the system configuration of Memory

Mapped I/O using HS-80C85RH.

The HS-80C85RH CPU can also interface with the standard

radiation-hardened memory that does not have the

multiplexed address/data bus. It will require use of the

HS-82C12RH (8-bit latch) as shown in Figure 14.

12

HS-80C85RH

VSS VDD

X1

X2

RESET IN

HOLD

TRAP

RST 7.5

RST 6.5

RST 5.5

INTR

HLDA

SOD

HS-80C85RH

RESET

SID

S1

S0

RDY CLK

INTA

ADDR/

OUT

ADDR DATA ALE RD WR IO/M

VSS VDD

(8)

CE

WR

PORT

(8)

(6)

A

RD

ALE

PORT

B

PORT

C

DATA/

ADDR

IN

TIMER

OUT

IO/M

RESET

IOW

RD

ALE

CE

PORT

A

(8)

A0-10

DATA/

ADDR

IO/M

RESET

RDY (NOTE)

CLK

PORT

B

IOR

VDD

VSS VDD

VDD

NOTE: Optional connection.

FIGURE 12. HS-80C85RH MINIMUM SYSTEM (STANDARD I/O TECHNIQUE)

A8-15

AD0-7

ALE

RD

HS-80C85RH

WR

IO/M

CLK

RESET OUT

READY

VDD

TIMER OUT

HS-83C55RH

(ROM +I/O)

HS-81C56RH

(RAM + I/O + COUNTER/TIMER)

(6)

(8)

NOTE: Optional connection.

FIGURE 13. HS-80C85RH MINIMUM SYSTEM (MEMORY MAPPED I/O)

13

HS-80C85RH

VSS VDD

X1

X2

RESET IN

TRAP

HOLD

HLDA

SOD

SID

RST 7.5

RST 6.5

RST 5.5

INTR

HS-80C85RH

S1

RESET

OUT

RDY CLK

INTA

ADDR

S0

ADDR/

DATA ALE RD WR IO/M

(8)

IO/M (CS)

WR

RD

STANDARD

MEMORY

HS-82C12RH

DATA

ADDR (CS)

CLK

RESET

IO/M (CS)

WR

I/O PORTS,

CONTROLS

(16)

RD

DATA

STANDARD

I/O

ADDR

VDD

FIGURE 14. HS-80C85RH SYSTEM (USING STANDARD MEMORIES)

14

HS-80C85RH

A machine cycle normally consists of three T states, with the

Basic System Timing

exception of OPCODE FETCH, which normally has either

four or six T states (unless WAIT or HOLD states are forced

by the receipt of READY or HOLD inputs). Any T state must

be one of ten possible states, shown in Table 11.

The HS-80C85RH has a multiplexed Data Bus. ALE is used

as a strobe to sample the lower 8-bits of address on the Data

Bus. Figure 15 shows an instruction fetch, memory read and

I/O write cycle (as would occur during processing of the OUT

instruction). Note that during the I/O write and read cycle that

the I/O port address is copied on both the upper and lower

half of the address.

TABLE 6. HS-80C85RH MACHINE STATE CHART

STATUS AND BUSES

CONTROL

MACHINE

STATE S1, S0 IO/M A8-15 AD0-7 RD, WR INTA ALE

There are seven possible types of machine cycles. Which of

these seven takes place is defined by the status of the three

status lines (lO/M, S1, S0) and the three control signals (RD,

WR, and INTA). (See Table 10.) The status lines can be

used as advanced controls (for device selection, for

example), since they become active at the T1 state, at the

outset of each machine cycle. Control lines RD and WR are

used as command lines since they become active when the

transfer of data is to take place.

T1

X

1

X

1

X

1

X

1

1†

0

T2

TWAIT

T3

X

0

X

0

T4

0††

TS

X

TS

1

0

T5

1

X

1

0

T6

1

X

1

0

TABLE 5. HS-80C85RH MACHINE CYCLE CHART

TRESET

THALT

THOLD

X

0

TS

0

STATUS

CONTROL

0

MACHINE CYCLE

Opcode Fetch (OF)

IO/M S1 S0 RD WR INTA

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

X

0

Memory Read (MR)

Memory Write (MW)

0 = Logic “0”

1 = Logic “1”

TS = High Impedance

X = Unspecified

I/O Read

I/O Write

(IOR)

(IOW)

†

ALE not generated during 2nd and 3rd machine cycles of DAD

instruction.

†† IO/M = 1 during T4, T6 of INA machine cycle.

Acknowledge (INA)

of INTR

Bus Idle

(BI)

DAD Ack. of

RST, TRAP

HALT

0

1

0

1

0

1

TS

TS TS

M1

T3

M2

T2

M3

T1

T2

T4

T1

T3

T1

T2

T3

T

CLK

A8-A15

PCH (HIGH ORDER ADDRESS)

(PC + 1)H

IO PORT

AD0-7

ALE

(PC+1)L

PCL

IO PORT

(LOW ORDER DATA FROM

ADDRESS)

DATA TO

DATA FROM

MEMORY (I/O

PORT ADDRESS)

MEMORY

MEMORY OR

PERIPHERAL

(INSTRUCTION)

RD

WR

IO/M

STATUS

11

S1-S0 (FETCH)

10 (READ)

01 WRITE

FIGURE 15. 80C85RH BASIC SYSTEM TIMING

15

HS-80C85RH

Die Characteristics

DIE DIMENSIONS:

Substrate:

Radiation Hardened Silicon Gate,

229 mils x 240 mils x 14 mils ±1 mil

Dielectric Isolation

INTERFACE MATERIALS:

Glassivation:

Backside Finish:

Silicon

Type: SiO

2

ASSEMBLY RELATED INFORMATION:

Thickness: 8kÅ ±1kÅ

Top Metallization:

Substrate Potential:

Type: SiAl

Unbiased (DI)

Thickness: 11kÅ ±2kÅ

Metallization Mask Layout

HS-80C85RH

TRAP (6)

RST 7.5 (7)

RST 6.5 (8)

RST 5.5 (9)

(35) READY

(34) IO/M

(33) S1

(32) RD

INTR (10)

INTA (11)

(31) WR

(30) ALE

AD0 (12)

(29) S0

(28) A15

AD1 (13)

AD2 (14)

(27) A14

(26) A13

(25) A12

AD3 (15)

AD4 (16)

16


型号：	HS9-80C85RH-Q
厂家：	Intersil
描述：	Radiation Hardened 8-Bit CMOS Microprocessor 抗辐射的8位CMOS微处理器外围集成电路微处理器
文件：	总16页 (文件大小：910K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HS9-80C85RH-Q [INTERSIL]

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