HSP43220GM-25/883 [INTERSIL]
Decimating Digital Filter; 抽取数字滤波器
| 型号： | HSP43220GM-25/883 |
| 厂家： | 
Intersil |
| 描述： | Decimating Digital Filter |
| 文件： | 总7页 (文件大小：194K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HSP43220/883
TM
Data Sheet
March 1999
FN2802.3
Decimating Digital Filter
Features
The HSP43220/883 Decimating Digital Filter is a linear
phase low pass decimation filter which is optimized for
filtering narrow band signals in a broad spectrum of a signal
processing applications. The HSP43220/883 offers a single
chip solution to signal processing application which have
historically required several boards of ICs. This reduction in
component count results in faster development times, as
well as reduction of hardware costs.
• This Circuit is Processed in Accordance to MIL-STD-883
and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Single Chip Narrow Band Filter with up to 96dB
Attenuation
• DC to 25.6MHz Clock Rate
• 16-Bit 2’s Complement Input
The HSP43220/883 is implemented as a two stage filter
structure. As seen in the Block Diagram, the first stage is a
High Order Decimation Filter (HDF) which utilizes an
efficient decimation (sample rate reduction) technique to
obtain decimation up to 1024 through a coarse low-pass
filtering process. The HDF provides up to 96dB aliasing
rejection in the signal pass band. The second stage consists
of a Finite Impulse Response (FIR) decimation filter
structured as a transversal FIR filter with up to 512
symmetric taps which can implement filters with sharp
transition regions. The FIR can perform further decimation
by up to 16 if required, while preserving the 96dB aliasing
attenuation obtained by the HDF. The combined total
decimation capability is 16,384.
• 20-Bit Coefficients in FIR
• 24-Bit Extended Precision Output
• Programmable Decimation up to a Maximum of 16,384
• Standard 16-Bit Microprocessor Interface
• Filter Design Software Available DECI•MATE™
Applications
• Very Narrow Band Filters
• Zoom Spectral Analysis
• Channelized Receivers
Ordering Information
The HSP43220/883 accepts 16-bit parallel data in 2’s
complement format at sampling rates up to 30MSPS. It
provides a 16-bit microprocessor compatible interface to
simplify the task of programming and three-state outputs to
allow the connection of several ICs to a common bus. The
HSP43220/883 also provides the capability to bypass either
the HDF or the FIR for additional flexibility.
TEMP.
PKG.
NO.
o
PART NUMBER
HSP43220GM-15/883
HSP43220GM-25/883
RANGE ( C)
PACKAGE
-55 to 125 84 Ld PGA
-55 to 125 84 Ld PGA
G84.A
G84.A
Block Diagram
DECIMATION UP TO 1024
DECIMATION UP TO 16
INPUT CLOCK
DATA INPUT
24
HIGH ORDER
DECIMATION
FILTER
FIR
DECIMATION
FILTER
16
16
DATA OUT
DATA READY
CONTROL AND COEFFICIENTS
FIR CLOCK
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1
DECIMATE™ is a trademark of Intersil Corporation. IBM PC, XT, AT, PS/2™ are trademarks of IBM Corporation.
HSP43220/883
Absolute Maximum Ratings
Thermal Information
o
o
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8V
Input, Output Voltage. . . . . . . . . . . . . . . . . . . GND -5V to V 0.5V
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 1
Thermal Resistance (Typical, Note 1)
PGA Package. . . . . . . . . . . . . . . . . . . .
θ
( C/W)
θ
( C/W)
JA
JC
CC
35
5
o
Maximum Package Power Dissipation at 125 C
PGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . .175 C
Maximum Storage Temperature Range . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C
1.52
o
Operating Conditions
o
o
o
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to 5.5V
o
o
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
Die Characteristics
Number of Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48,250
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS
Devices Guaranteed and 100% Tested
GROUP A
SUB-
GROUPS
LIMITS
TEST
CONDITIONS
o
PARAMETER
Logical One Input Voltage
Logical Zero Input Voltage
Output HIGH Voltage
SYMBOL
TEMP ( C)
-55 ≤ T ≤ 125
MIN
TYP
UNITS
V
V
V
= 5.5V
1, 2, 3
1, 2, 3
1, 2, 3
2.2
-
-
0.8
-
V
V
V
IH
CC
A
V
- 4.5V
-55 ≤ T ≤ 125
A
IL
CC
V
I
= 400µA,
-55 ≤ T ≤ 125
2.6
OH
OH
A
V
= 4.5V (Note 2)
CC
Output LOW Voltage
Input Leakage Current
Output Leakage Current
V
I
V
= 2.0mA
1, 2, 3
1, 2, 3
1, 2, 3
-55 ≤ T ≤ 125
-
0.4
+10
+10
V
OL
OL
A
= 4.5V (Note 2)
CC
I
V
V
= V
or GND,
= 5.5V
-55 ≤ T ≤ 125
-10
-10
µA
µA
I
IN
CC
A
CC
I
V
V
= V
or GND,
-55 ≤ T ≤ 125
A
O
OUT
CC
= 5.5V
= 5.5V
= 4.5V
CC
CC
CC
Clock Input High
V
V
V
1, 2, 3
1, 2, 3
1, 2, 3
-55 ≤ T ≤ 125
3.0
-
V
V
IHC
A
Clock Input Low
V
-55 ≤ T ≤ 125
-
-
0.8
500
ILC
A
Standby Power Supply Current
I
V
V
= V
or GND,
-55 ≤ T ≤ 125
µA
CCSB
IN
CC
A
= 5.5V,
CC
Outputs Open
Operating Power Supply Current
I
f = 15.0MHz,
1, 2, 3
7, 8
-55 ≤ T ≤ 125
-
-
120
-
mA
CCOP
A
V
= 5.5V (Note 3)
CC
Functional Test
NOTES:
FT
(Note 4)
-55 ≤ T ≤ 125
A
2. Interchanging of force and sense conditions is permitted.
3. Operating supply current is proportional to frequency, typical rating is 8mA/MHz.
4. Tested as follows: f = 1MHz, V = 2.6, V = 0.4, V ≥ 1.5V, V ≤ 1.5V, V
= 3.4V and V = 0.4V.
ILC
IH IL OH
OL
IHC
2
HSP43220/883
TABLE 2. AC ELECTRICAL PERFORMANCE SPECIFICATIONS
Devices Guaranteed and 100% Tested
GROUP A
SUB-
SYMBOL (NOTE 5) GROUPS
-15 (15MHz)
MIN MAX
-25 (25.6MHz)
(NOTES)
o
PARAMETER
Input Clock Period
TEMP ( C)
MIN
39
39
16
16
0
MAX
UNITS
ns
t
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
-55 ≤ T ≤ 125
66
66
26
26
0
-
-
-
-
-
-
-
-
CK
A
FIR Clock Period
t
-55 ≤ T ≤ 125
ns
FIR
A
Clock Pulse Width Low
Clock Pulse Width High
t
-55 ≤ T ≤ 125
ns
SPWL
A
t
-55 ≤ T ≤ 125
ns
SPWH
A
Clock Skew Between
FIR_CLK and CK_IN
t
-55 ≤ T ≤ 125
T
-25
T
-19
ns
SK
A
FIR
FIR
RESET Pulse Width Low
t
9, 10, 11
9, 10, 11
-55 ≤ T ≤ 125
4 T
-
-
4 T
-
-
ns
ns
RSPW
A
CK
CK
CK
Recovery Time On
RESET
t
-55 ≤ T ≤ 125
8 T
8 T
RTRS
A
CK
ASTARTIN Pulse Width
Low
t
9, 10, 11
9, 10, 11
9, 10, 11
-55 ≤ T ≤ 125
T
+10
-
T +10
CK
-
ns
ns
ns
AST
A
CK
STARTOUT Delay From
CK_IN
t
-55 ≤ T ≤ 125
-
35
-
20
STOD
A
STARTIN Setup to
CK _IN
t
-55 ≤ T ≤ 125
25
-
15
-
STIC
A
Setup Time on DATA_IN
Hold Time on All Inputs
Write Pulse Width Low
Write pulse Width High
t
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
-55 ≤ T ≤ 125
20
0
-
-
-
-
-
16
0
-
-
-
-
-
ns
ns
ns
ns
ns
SET
A
t
-55 ≤ T ≤ 125
A
HOLD
t
-55 ≤ T ≤ 125
26
26
28
15
20
24
WL
A
t
-55 ≤ T ≤ 125
A
WH
Setup Time on Address
Bus Before the Rising
Edge of Write
t
-55 ≤ T ≤ 125
A
STADD
Setup Time on Chip
Select Before the
Rising Edge of Write
t
9, 10, 11
9, 10, 11
-55 ≤ T ≤ 125
28
28
-
-
-
24
24
-
-
-
ns
ns
STCS
A
Setup Time on Control
Bus Before the Rising
Edge of Write
t
-55 ≤ T ≤ 125
A
STCB
DATA_RDY Pulse Width
Low
t
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
-55 ≤ T ≤ 125
2T
-20
2T
-10
ns
ns
ns
ns
ns
DRPWL
A
FIR
FIR
-
DATA_OUT Delay
Relative to FIR_CK
t
-55 ≤ T ≤ 125
-
50
35
30
20
35
25
25
20
FIRDV
FIRDR
A
DATA_RDY Valid Delay
Relative to FIR_CK
t
-55 ≤ T ≤ 125
-
-
-
-
-
-
A
DATA_OUT Delay
Relative to OUT_SELH
t
-55 ≤ T ≤ 125
A
OUT
OEV
Output Enable to
Data Out Valid
t
Note 6
-55 ≤ T ≤ 125
A
NOTES:
5. AC Testing: V
= 4.5V and 5.5V. Inputs are driven at 3.0V for a Logic “1” and 0.0V for a Logic “0”. Input and output timing measurements are
CC
made at 1.5V for both a Logic “1” and “0”. CLK is driven at 4.0V and 0V and measured at 2.0V.
6. Transition is measured at ±200mV from steady state voltage with loading as specified by test load circuit and C = 40pF.
L
3
HSP43220/883
TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS
Devices Guaranteed and 100% Tested
-15 (15MHz)
-25 (25.6MHz)
TEST
CONDITIONS
o
PARAMETER
SYMBOL
NOTES
7, 9
7, 9
7, 9
7, 9
7
TEMP ( C)
-55 ≤ T ≤ 125
MIN
29
29
27
2
MAX
MIN
19
19
17
2
MAX
UNITS
ns
CK_IN Pulse Width Low
CK_IN Pulse Width High
CK_IN Setup to FIR_CK
CK_IN Hold from FIR_CK
Input Capacitance
t
-
-
-
-
CH1L
A
t
-55 ≤ T ≤ 125
ns
CH1H
A
t
-55 ≤ T ≤ 125
-
-
ns
CIS
CIH
A
t
-55 ≤ T ≤ 125
-
-
ns
A
o
C
V
= Open, f = 1MHz,
T
= 25 C
-
12
-
12
pF
IN
OUT
OEZ
CC
A
All measurements are
referenced to device
GND
o
Output Capacitance
C
V
= Open, f = 1MHz,
7
T
= 25 C
-
10
-
10
pF
CC
A
All measurements are
referenced to device
GND
Output Disable Delay
Output Rise Time
Output Fall Time
NOTES:
t
7, 8
7, 8
7, 8
-55 ≤ T ≤ 125
-
-
-
20
8
-
-
-
20
8
ns
ns
ns
A
t
-55 ≤ T ≤ 125
A
OR
t
-55 ≤ T ≤ 125
8
8
OF
A
7. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized
upon initial design and after major process and/or design changes.
8. Loading is as specified in the test load circuit with C = 40pF.
L
9. Applies only when H_BYP = 1 or H_DRATE = 0.
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
Initial Test
METHOD
100%/5004
100%/5004
100%
SUBGROUPS
-
Interim Test
-
PDA
1
Final Test
100%
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 7, 9
Group A
-
Groups C and D
Samples/5005
4
HSP43220/883
Burn-In Circuit
HSP43220/883
TOP VIEW
PINS DOWN
1
2
3
4
5
6
7
8
9
10
11
DATA_ DATA_ DATA_ DATA_ DATA_ DATA_ DATA_
IN 1 IN 2 IN 4 IN 7 IN 8 IN 11 IN 14
A
B
C
D
E
F
GND
VCC
GND
GND
START START DATA_ DATA_ DATA_ DATA_ DATA_ DATA_
DATA_
OUT 1
CLK_IN
V
CC
IN
OUT
IN 0
IN 3
IN 6
IN 13
IN 12
IN 15
DATA_ DATA_ DATA_
DATA_ DATA_
OUT 0 OUT 2
ASTART
IN
V
CC
IN 0
IN 9
IN 10
DATA_ DATA_
OUT 3 OUT 4
A1
CS
RESET
WR
DATA_ DATA_ DATA_
A0
OUT 5
OUT 3
OUT 7
C_BUS C_BUS C_BUS
10 15 14
DATA_
OUT 9
DATA_
OUT 8
V
CC
C_BUS C_BUS C_BUS
DATA_
OUT 10
DATA_
OUT 11
G
H
J
GND
12
11
13
DATA_ DATA_
OUT 13 OUT 12
C_BUS
9
V
CC
C_BUS
7
OUT_
SELH
FIR_
CK
DATA_ DATA_
OUT 16 OUT 14
GND
GND
C_BUS C_BUS C_BUS C_BUS OUT_
EMP
DATA_ DATA_ DATA_ DATA_
OUT 22 OUT 19 OUT 17 OUT 15
K
L
V
GND
CC
8
5
4
1
C_BUS C_BUS C_BUS C_BUS OUT_
DATA_
RDY
DATA_ DATA_ DATA_ DATA_
OUT 23 OUT 21 OUT 20 OUT 18
V
CC
6
3
2
0
ENX
BURN-IN CIRCUIT SIGNALS
BURN-IN
BURN-IN
SIGNAL
BURN-IN
SIGNAL
PIN LEAD
A1
PIN NAME
GND
PIN LEAD
PIN NAME
SIGNAL
PIN LEAD
F11
G1
PIN NAME
DATA_OUT 3
C_BUS 12
C_BUS 11
C_BUS 13
DATA_OUT 10
GND
GND
F2
C1
C2
ASTARTIN
F15
V
/2
CC
F5
A2
DATA_IN 1
DATA_IN 2
DATA_IN 4
DATA_IN 7
DATA_IN 8
DATA_IN 11
DATA_IN 14
V
V
CC
CC
A3
F3
C5
DATA_IN 5
DATA_IN 9
DATA_IN 10
DATA_OUT 0
DATA_OUT 2
A1
F6
F2
F3
G2
F4
F6
A4
F5
C6
G3
A5
F8
C7
G9
V
/2
CC
A6
F1
C10
C11
D1
V
V
/2
G10
G11
HI
GND
CC
A7
F4
/2
DATA_OUT 11
C_BUS 9
V
/2
CC
CC
A8
F7
F14
F16
F2
A9
V
V
D2
RESET
H2
V
V
CC
CC
CC
CC
A10
A11
B1
GND
GND
GND
F15
D10
D11
E1
DATA_OUT 3
DATA_OUT 4
CS
V
/2
H10
H11
J1
DATA_OUT 13
DATA_OUT 12
GND
V
V
/2
CC
CC
CC
GND
V
/2
/2
CC
STARTIN
STARTOUT
DATA_IN 0
DATA_IN 3
DATA_IN 6
F11
F11
F13
GND
F8
B2
V
/2
E2
WR
J2
C_BUS 7
OUT_SEL
GND
CC
B3
F1
E3
A0
J5
F10
GND
F0
B4
F4
F7
E9
DATA_OUT 5
DATA_OUT 6
V
/2
J6
CC
B5
E10
V
/2
J8
FIR_CK
CC
5
HSP43220/883
BURN-IN CIRCUIT SIGNALS (CONTINUED)
BURN-IN
BURN-IN
SIGNAL
BURN-IN
SIGNAL
PIN LEAD
B6
PIN NAME
DATA_IN 13
DATA_IN 12
DATA_IN 15
CK_IN
PIN LEAD
E11
F1
PIN NAME
DATA_OUT 7
C_BUS 10
SIGNAL
PIN LEAD
J10
J11
K1
PIN NAME
DATA_OUT 16
DATA_OUT 14
C_BUS 8
F6
F5
F8
F0
V
/2
V
V
/2
/2
CC
F3
CC
B7
CC
F1
B8
F2
C_BUS 15
F8
F7
B9
F3
C_BUS 14
K2
C_BUS 5
F6
F5
F2
B10
B11
K5
V
V
F9
DATA_OUT9
V
/2
K3
C_BUS 4
CC
CC
CC
DAT_OUT 1
OUT_ENP
V
/2
F10
K11
L1
V
V
CC
K4
C_BUS 1
CC
F9
CC
DATA_OUT 15
C_BUS 6
V
/2
L6
DATA_RDY
V
/2
CC
CC
K6
V
V
F7
L7
V
V
CC
CC
CC
CC
K7
GND
GND
L2
C_BUS 3
F4
F3
F1
F9
L8
DATA_OUT 23
DATA_OUT 21
DATA_OUT 20
DATA_OUT 18
V
V
V
V
/2
/2
/2
/2
CC
CC
CC
CC
K8
DATA_OUT 22
DATA_OUT 19
DATA_OUT 17
V
/2
L3
C_BUS 2
L9
CC
CC
CC
K9
V
V
/2
/2
L4
C_BUS 0
L10
L11
K10
L5
OUT_ENX
NOTES:
10. V /2 (2.7 ±10%) used for outputs only.
CC
11. 47kΩ (±20%) resistor connected to all pins except V
and GND.
CC
12. V
= 5.5 ±0.5V.
CC
13. 0.1µF (minimum) capacitor between V
and GND per position.
CC
14. F0 = 100kHz ±10%, F1 = F0/2, F2 = F1/2....F16 = F15/2, 40% - 60% duty cycle.
15. Input voltage limits: V = 0.8 maximum, V = 4.5V ±10%.
IL IH
Metal Topology
DIE DIMENSIONS:
WORST CASE CURRENT DENSITY:
5
2
348 x 349.2 x 19 ±1 mils
1.18 x 10 A/cm
METALLIZATION:
GLASSIVATION:
Type: Si - Al, or Si - Al - Cu
Thickness: 8kÅ
Type: Nitrox
Thickness: 10kÅ
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
6
HSP43220/883
Ceramic Pin Grid Array Packages (CPGA)
G84.A MIL-STD-1835 CMGA3-P84C (P-AC)
84 LEAD CERAMIC PIN GRID ARRAY PACKAGE
–A–
D
S1
INCHES
MIN
MILLIMETERS
D1
SYMBOL
MAX
0.345
0.145
0.0215
0.020
0.058
0.080
1.180
MIN
5.46
1.78
0.41
0.41
1.07
-
MAX
8.76
3.68
NOTES
A
A1
b
0.215
0.070
0.016
0.016
0.042
-
-
3
8
-
0.55
b1
b2
C
0.51
–B–
1.47
4
-
S
2.03
D
1.140
28.96
29.97
-
E1
E
D1
E
1.000 BSC
25.4 BSC
-
1.140
1.180
28.96
29.97
-
E1
e
1.000 BSC
25.4 BSC
-
0.100 BSC
0.008 REF
2.54 BSC
0.20 REF
6
-
k
L
0.120
0.140
0.060
3.05
3.56
1.52
-
Q
0.040
0.003
-
1.02
0.08
-
5
10
-
C
S
S
0.000 BSC
0.00 BSC
INDEX CORNER
SEE NOTE 9
b1
S1
M
N
-
-
11
11
1
2
SEE
NOTE 7
121
121
Rev. 1 6/28/95
b
SECTION B-B
A
0.008
C
NOTES:
SEATING PLANE
AT STANDOFF
1. “M” represents the maximum pin matrix size.
–C–
2. “N” represents the maximum allowable number of pins. Number
of pins and location of pins within the matrix is shown on the
pinout listing in this data sheet.
B
B
k
A1
3. Dimension “A1” includes the package body and Lid for both cav-
ity-up and cavity-down configurations. This package is cavity up.
Dimension “A1” does not include heatsinks or other attached
features.
L
b2
e
4. Standoffs are intrinsic and shall be located on the pin matrix di-
agonals. The seating plane is defined by the standoffs at dimen-
sions Q.
5. Dimension “Q” applies to cavity-up configurations only.
6. All pins shall be on the 0.100 inch grid.
Q
7. Datum C is the plane of pin to package interface for both cavity
up and down configurations.
SECTION A-A
b
8. Pin diameter includes solder dip or custom finishes. Pin tips shall
have a radius or chamfer.
M
M
M
M
B
Ø0.030
Ø0.010
C
C
A
A
A
9. Corner shape (chamfer, notch, radius, etc.) may vary from that
shown on the drawing. The index corner shall be clearly unique.
10. Dimension “S” is measured with respect to datums A and B.
11. Dimensioning and tolerancing per ANSI Y14.5M-1982.
12. Controlling dimension: INCH.
L
A1
Q
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