HSP45106883 [INTERSIL]
16-Bit Numerically Controlled Oscillator; 16位数控振荡器
| 型号： | HSP45106883 |
| 厂家： | 
Intersil |
| 描述： | 16-Bit Numerically Controlled Oscillator |
| 文件： | 总6页 (文件大小：122K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HSP45106/883
TM
Data Sheet
May 1999
FN2815.3
16-Bit Numerically Controlled Oscillator
Features
The Intersil HSP45106/883 is a high performance 16-bit
quadrature Numerically Controlled Oscillator (NCO16). The
NCO16 simplifies applications requiring frequency and
phase agility such as frequency-hopped modems, PSK
modems, spread spectrum communications, and precision
signal generators. As shown in the Block Diagram, the
HSP45106/883 is divided into a Phase/Frequency Control
Section (PFCS) and a Sine/Cosine Section.
• This Circuit is Processed in Accordance to MIL-STD-883
and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• 25.6MHz Clock Rate
• 32-Bit Center and Offset Frequency Control
• 16-Bit Phase Control
• 8 Level PSK Supported Through Three Pin Interface
• Simultaneous 16-Bit Sine and Cosine Outputs
• Output in Two’s Complement or Offset Binary
• <0.006Hz Tuning Resolution at 25.6MHz
• Serial or Parallel Outputs
The inputs to the Phase/Frequency Control Section consist
of a microprocessor interface and individual control lines.
The frequency resolution is 32 bits, which provides for
resolution of better than 0.006Hz at 25.6MHz. User
programmable center frequency and offset frequency
registers give the user the capability to perform phase
coherent switching between two sinusoids of different
frequencies. Further, a programmable phase control register
allows for phase control of better than 0.006o. In applications
requiring up to 8 level PSK, three discrete inputs are
provided to simplify implementation.
• Spurious Frequency Components < -90dBc
• 16-Bit Microprocessor Compatible Control Interface
Applications
• Direct Digital Synthesis
The output of the PFCS is a 32-bit phase argument which is
input to the Sine/Cosine Section for conversion into
sinusoidal amplitude. The outputs of the Sine/Cosine
Section are two 16-bit quadrature signals. The spurious free
dynamic range of this complex vector is greater than 90dBc.
• Quadrature Signal Generation
• Modulation - FM, FSK, PSK (BPSK, QPSK, 8PSK)
• Precision Signal Generation
For added flexibility when using the NCO16 in conjunction
with DAC’s, a choice of either parallel of serial outputs with
either two’s complement or offset binary encoding is
provided. In addition, a synchronization signal is available
which signals serial word boundaries.
Ordering Information
TEMP.
PKG.
NO.
o
PART NUMBER
RANGE ( C)
PACKAGE
HSP45106GM-25/883
-55 to 125 85 Ld PGA
G85.A
Block Diagram
SIN/COS
ARGUMENT
MICROPROCESSOR
16
INTERFACE
SINE
PHASE/
32
SINE/
FREQUENCY
CONTROL
SECTION
DISCRETE
CONTROL SIGNALS
COSINE
SECTION
16
COSINE
CLOCK
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1
HSP45106/883
Absolute Maximum Ratings
Thermal Information
o
o
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V
Input, Output Voltage Applied . . . . . . . . . .GND -0.5V to V +0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 1
Thermal Resistance (Typical, Note 1)
PGA Package. . . . . . . . . . . . . . . . . . . .
Maximum Package Power Dissipation at 125 C
θ
( C/W)
θ
( C/W)
JA
JC
36.0
7.0
CC
o
PGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.39W
o
o
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 175 C
Operating Conditions
o
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
o
o
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
o
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C
Die Characteristics
Gate Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18,750
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
GROUP A
SUBGROUPS
TEMPERATURE
o
PARAMETER
Logical One Input Voltage
Logical Zero Input Voltage
Output HlGH Voltage
SYMBOL
TEST CONDITIONS
( C)
MIN
2.2
-
MAX
UNITS
V
V
V
V
= 5.5V
= 4.5V
1, 2, 3
1, 2, 3
1, 2, 3
55 ≤ T ≤ +125
-
0.8
-
V
V
V
lH
CC
A
55 ≤ T ≤ +125
IL
CC
A
V
I
= -400µA
55 ≤ T ≤ +125
2.6
OH
OH
A
V
= 4.5V (Note 2)
CC
Output LOW Voltage
Input Leakage Current
Output Leakage Current
V
I
V
= +2.0mA
1, 2, 3
1, 2, 3
1, 2, 3
55 ≤ T ≤ +125
-
0.4
+10
+10
V
OL
OL
A
= 4.5V (Note 2)
CC
I
V
V
= V
or GND
55 ≤ T ≤ +125
-10
-10
µA
µA
I
IN
CC
= 5.5V
A
CC
I
V
V
= V
CC
or GND
55 ≤ T ≤ +125
A
O
OUT
= 5.5V
= 5.5V
= 4.5V
CC
CC
CC
Clock lnput High
Clock Input Low
V
V
V
1, 2, 3
1, 2, 3
1, 2, 3
55 ≤ T ≤ +125
3.0
-
V
V
IHC
A
V
55 ≤ T ≤ +125
-
-
0.8
500
ILC
A
Standby Power Supply
Current
I
V
V
= V
or GND
55 ≤ T ≤ +125
µA
CCSB
IN
CC
= 5.5V, (Note 5)
A
CC
Operating Power Supply Cur-
rent
I
f = 25.6MHz
= 5.5V (Notes 3, 5)
1, 2, 3
7, 8
55 ≤ T ≤ +125
-
-
205
-
mA
-
CCOP
A
V
CC
Functional Test
NOTES:
FT
(Note 4)
55 ≤ T ≤ +125
A
2. Interchanging of force and sense conditions is permitted.
3. Operating supply current is proportional to frequency, typical rating is 8mA/MHz.
4. Tested as follows: f = 1MHz, V = 2.6, V = 0.4, V ≥ 1.5V, V ≤ 1.5V, V
= 3.4V, and V = 0.4V.
ILC
IH IL OH
OL
IHC
5. Loading is as specified in the test load circuit with C = 40pF.
L
2
HSP45106/883
TABLE 2. AC ELECTRICAL PERFORMANCE SPECIFICATIONS
-25 (25.6MHz)
GROUP A
SUBGROUP
TEMPERATURE
o
PARAMETER
CLK Period
SYMBOL
NOTES
( C)
MIN
39
15
15
39
15
15
13
MAX
UNITS
ns
t
t
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
-55 ≤ T ≤ 125
-
-
-
-
-
-
-
CP
CH
A
CLK High
CLK Low
WR Period
WR High
WR Low
-55 ≤ T ≤ 125
ns
A
t
-55 ≤ T ≤ 125
ns
CL
WP
WH
A
t
-55 ≤ T ≤ 125
ns
A
t
-55 ≤ T ≤ 125
ns
A
t
-55 ≤ T ≤ 125
ns
WL
A
Setup Time A(2:0), CS to WR
Going High
t
-55 ≤ T ≤ 125
ns
AWS
AWH
CWS
CWH
A
Hold Time A(2:0), CS from WR Go-
ing High
t
t
9, 10, 11
9, 10, 11
9, 10, 11
-55 ≤ T ≤ 125
2
15
1
-
-
-
ns
ns
ns
A
Setup Time C(15:0) to WR
Going High
-55 ≤ T ≤ 125
A
Hold Time C(15:0) from WR
Going High
t
-55 ≤ T ≤ 125
A
Setup Time WR High to CLK High
t
Note 8
9, 10, 11
9, 10, 11
-55 ≤ T ≤ 125
16
15
-
-
ns
ns
WC
A
Setup Time MOD(2:0) to CLK
Going High
t
-55 ≤ T ≤ 125
A
MCS
MCH
Hold Time MOD(2:0) from CLK Go-
ing High
t
9, 10, 11
9, 10, 11
-55 ≤ T ≤ 125
1
-
-
ns
ns
A
Setup Time ENPOREG,
t
-55 ≤ T ≤ 125
12
ECS
A
ENOFREG, ENCFREG,
ENPHAC, ENTIREG, INHOFR,
PMSEL, INITPAC, BINFMT, TEST,
PAR/SER, PACI, INITTAC to CLK
Going High
Setup Time ENPOREG,
ENOFREG, ENCFREG,
ENPHAC, ENTIREG, INHOFR,
PMSEL, INITPAC, BINFMT, TEST,
PAR/SER, PACI, INITTAC from
CLK Going High
t
9, 10, 11
-55 ≤ T ≤ 125
1
-
ns
ns
ECH
A
CLK to Output Delay SIN(15:0),
COS(15:0), TICO
t
9, 10, 11
-55 ≤ T ≤ 125
-
18
DO
A
CLK to Output Delay DACSTRB
Output Enable Time
NOTES:
t
9, 10, 11
9, 10, 11
-55 ≤ T ≤ 125
2
-
18
12
ns
ns
DSO
A
t
Note 7
-55 ≤ T ≤ 125
A
OE
6. AC Testing: V
= 4.5V and 5.5V. Inputs are driven at 3.0V for Logic “1” and 0.0V for a Logic “0”. Input and output timing measurements are
CC
made at 1.5V for both a Logic “1” and 0”. CLK is driven at 4.0V and 0V and measured at 2.0V. Output load per test load circuit with switch closed
and C = 40pF.
L
7. Transition is measured at ±200mV from steady state voltage with loading as specified by test load circuit and C = 40pF.
L
8. If ENOFRCTL, ENCFRACTL, ENTICTL, or ENPHREG are active, care must be taken to not violate setup and hold times to these registers when
writing data into the chip via the C(15:0) port.
3
HSP45106/883
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
-25 (25MHz)
TEMPERATURE
o
PARAMETER
SYMBOL
CONDITIONS
NOTES
( C)
MIN
MAX
UNITS
C
Input Capacitance
IN
V
= Open, f = 1MHz, all measure-
9
T
T
= 25
-
10
pF
CC
A
A
ments are referenced to device GND.
Output Capacitance
C
V
= Open, f = 1MHz, all measure-
9
= 25
-
10
pF
OUT
CC
ments are referenced to device GND.
Output Disable Delay
Output Rise Time
Output Fall Time
NOTES:
t
9, 10
9, 10
9, 10
-55 ≤ T ≤ 125
-
-
-
15
8
ns
ns
ns
OEZ
A
t
From 0.8V to 2.0V
From 20.V to 0.8V
-55 ≤ T ≤ 125
A
OR
t
-55 ≤ T ≤ 125
8
OF
A
9. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized
upon initial design and after major process and/or design changes.
10. Loading is as specified in the test load circuit with switch closed and C = 40pF.
L
TABLE 4. ELECTRICAL TEST REQUIREMENTS
METHOD
CONFORMANCE GROUPS
Initial Test
SUBGROUPS
100%/5004
100%/5004
100%
-
Interim Test
PDA
-
1
Final Test
Group A
100%
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 7, 9
-
Groups C and D
Samples/5005
4
HSP45106/883
Burn-In Circuit
HSP45106/833 (PGA)
11
10
9
8
7
6
5
4
3
2
1
DAC
STRB
L
GND
SIN0
SIN1
SIN3
SIN5
SIN4
SIN9 SIN12 SIN13 SIN14
L
K
J
FMT
V
CLK
SIN2
V
SIN8 SIN10 GND SIN15 OES COSO
K
J
CC
CC
PAR/
SEL
INIPAC
SIN6
SIN7 SIN11
OEC COS1
COS2 COS3
ENP
HAC
H
G
F
PACI
H
G
F
ENTI INITT INHOF
REG AC
COS6 COS4 COS5
R
ENCF ENPO ENOF
REG
COS7 COS8
V
CC
REG
REG
E
D
C
B
A
CS
GND
WR
COS11 COS10 COS9
E
D
C
B
A
V
TEST
GND COS12
INDEX
CC
MOD2 MOD0
MOD1 A2
PMSEL A0
C10
C12
C11
C9
C13
C8
C6
COS15 COS13
PIN
A1
C15
C14
V
C4
C5
C1
C3
TICO COS14
CC
GND
C7
C2
C0
PIN “A1”
PGA
PIN
PIN
NAME
BURN-IN
SIGNAL
PGA
PIN
PIN
NAME
BURN-IN
SIGNAL
PGA
PIN
PIN
NAME
BURN-IN
SIGNAL
PGA
PIN
PIN
NAME
BURN-IN
SIGNAL
A1
A2
C0
C2
F7
F7
B11
C1
MOD1
COS13
COS15
C6
F13
F9
F10
F11
G1
G2
G3
G9
G10
G11
H1
ENOFREG
ENPOREG
ENCFREQ
COS5
F8
F4
F7
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
L1
OES
SIN15
GND
F14
V
V
/2
/2
V
/2
CC
CC
GND
A3
C3
F7
C2
CC
F8
A4
C5
F8
C5
V
V
V
/2
/2
/2
SIN10
SIN8
V
/2
CC
CC
CC
CC
CC
A5
C7
F8
C6
C9
F10
F10
F12
F14
COS4
V
/2
A6
C8
F10
F10
F11
GND
F8
C7
C10
COS6
V
V
CC
CC
A7
C11
C14
GND
A0
C10
C11
D1
MOD0
MOD2
COS12
GND
INHOFR
INITTAC
ENTIREG
COS3
F11
F13
F12
SIN2
CLK
V
CC
F0
/2
A8
A9
V
/2
V
V
CC
CC
CC
A10
A11
B1
D2
GND
V
/2
BINFMT
DACSTRB
SIN14
SIN13
SIN12
SIN9
F6
CC
CC
PMSEL
COS14
TICO
C1
F14
D10
D11
E1
TEST
F14
H2
COS2
V
/2
V
V
V
V
V
V
V
V
V
V
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
V
V
/2
/2
V
V
CC
H10
H11
J1
PACI
F11
F10
L2
CC
CC
B2
COS9
COS10
COS11
WR
V
/2
ENPHAC
COS1
L3
CC
F7
CC
CC
B3
E2
V
V
/2
/2
V
/2
L4
CC
B4
C4
F8
E3
J2
OEC
F14
L5
CC
F4
B5
V
V
E9
J5
SIN11
V
/2
L6
SIN4
CC
CC
CC
CC
CC
B6
C13
C12
C15
A1
F11
F11
F11
F7
E10
E11
F1
GND
GND
F6
J6
SIN7
V
V
/2
/2
L7
SIN5
B7
CS
J7
SIN6
L8
SIN3
B8
V
V
J10
J11
K1
PAR/SER
INITPAC
COS0
F13
F12
L9
SIN1
CC
CC
B9
F2
COS8
COS7
V
/2
L10
L11
SIN0
CC
CC
B10
NOTES:
A2
F10
F3
V
/2
V
/2
GND
GND
CC
11. V /2 (2.7V ±10%) used for outputs only.
CC
12. 47kΩ (±20%) resistor connected to all pins except V
and GND.
CC
13. V
= 5.5V ±0.5V.
CC
14. 0.1µF (min) capacitor between V
and GND per position.
CC
15. F0 = 100kHz ±10%, F1 = F0/2, F2 = F1/2...., F11 = F10/2, 40% - 60% Duty Cycle.
16. Input voltage limits: V = 0.8V max., V = 4.5V ±10%.
IL IH
5
HSP45106/883
Die Characteristics
DIE DIMENSIONS:
GLASSIVATION:
251 mils x 240 mils x 19 ±1mils
Type: Nitrox
Thickness: 10kÅ
METALLIZATION:
WORST CASE CURRENT DENSITY:
Type: Si-Al, or Si-Al-Cu
Thickness: 8kÅ
5
2
0.8 x 10 A/cm
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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6
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