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HTCS138MS [INTERSIL]

Radiation Hardened Inverting 3-to-8 Line Decoder/Demultiplexer; 抗辐射反相3至8线译码器/多路解复用器
HTCS138MS
型号： HTCS138MS
厂家： Intersil    Intersil
描述：

Radiation Hardened Inverting 3-to-8 Line Decoder/Demultiplexer
抗辐射反相3至8线译码器/多路解复用器

解复用器
文件： 总9页 (文件大小：308K)
中文：  中文翻译
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HCTS138MS  
®
Data Sheet  
September 12, 2005  
FN2462.3  
Radiation Hardened Inverting  
Features  
• 3 Micron Radiation Hardened SOS CMOS  
3-to-8 Line Decoder/Demultiplexer  
The Intersil HCTS138MS is a Radiation Hardened 3-to-8 line  
Decoder/Demultiplexer. The outputs are active in the low  
state. Two active low and one active high enables (E1, E2,  
E3) are provided. If the device is enabled, the binary inputs  
(A0, A1, A2) determine which one of the eight normally high  
outputs will go to a low logic level.  
• Total Dose 200K RAD (Si)  
• SEP Effective LET No Upsets: >100 MEV-cm2/mg  
• Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/Bit-  
Day (Typ)  
• Latch-Up Free Under Any Conditions  
The HCTS138MS utilizes advanced CMOS/SOS technology  
to achieve high-speed operation. This device is a member of  
radiation hardened, high-speed, CMOS/SOS Logic Family.  
• Fanout (Over Temperature Range)  
- Bus Driver Outputs - 15 LSTTL Loads  
• Military Temperature Range: -55oC to +125oC  
• Significant Power Reduction Compared to LSTTL ICs  
• DC Operating Voltage Range: 4.5V to 5.5V  
The HCTS138MS is supplied in a 16 lead Ceramic flatpack  
(K suffix) or a SBDIP Package (D suffix).  
Pinouts  
• LSTTL Input Compatibility  
- VIL = 0.8V Max  
- VIH = VCC/2 Min  
16 LEAD CERAMIC DUAL-IN-LINE  
METAL SEAL PACKAGE (SBDIP)  
MIL-STD-1835 CDIP2-T16  
TOP VIEW  
• Input Current Levels Ii ≤ 5µA at VOL, VOH  
A0  
A1  
1
2
3
4
5
6
7
8
16 VCC  
15 Y0  
14 Y1  
13 Y2  
12 Y3  
11 Y4  
10 Y5  
A2  
Ordering Information  
E1  
TEMP  
SCREENING  
E2  
PART NUMBER  
RANGE  
LEVEL  
PACKAGE  
E3  
HCTS138DMSR  
-55oC to Intersil Class S 16 Lead SBDIP  
+125oC  
Equivalent  
Y7  
9
Y6  
GND  
HCTS138KMSR  
HCTS138HMSR  
-55oC to Intersil Class S 16 Lead Ceramic  
+125oC  
+25oC  
Equivalent  
Flatpack  
Die  
Die  
16 LEAD CERAMIC METAL SEAL  
FLATPACK PACKAGE (FLATPACK)  
MIL-STD-1835 CDFP4-F16  
TOP VIEW  
A0  
A1  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
VCC  
Y0  
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
A2  
E1  
E2  
E3  
Y7  
GND  
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.  
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.  
Copyright Intersil Americas Inc. 1995, 1999, 2005. All Rights Reserved  
All other trademarks mentioned are the property of their respective owners.  
HCTS138MS  
Functional Diagram  
1
2
A0  
15  
14  
13  
Y0  
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
Y7  
A1  
12  
11  
10  
9
3
A2  
4
5
6
E1  
E2  
E3  
7
TRUTH TABLE  
INPUTS  
ENABLE  
OUTPUTS  
Y3 Y4  
E3  
X
E2  
X
X
H
L
E1  
A2  
X
X
X
L
A1  
X
X
X
L
A0  
X
X
X
L
Y0  
H
H
H
L
Y1  
H
H
H
H
L
Y2  
H
H
H
H
H
L
Y5  
H
H
H
H
H
H
H
H
L
Y6  
H
H
H
H
H
H
H
H
H
L
Y7  
H
H
H
H
H
H
H
H
H
H
L
H
X
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
L
X
H
H
H
H
H
H
H
H
L
L
L
H
L
H
H
H
H
H
H
H
L
L
H
H
L
H
H
H
H
H
H
L
L
H
L
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
L
H
L
H
H
H
L
H
H
H
H
L
H
H
H = High Level, L = Low Level, X = Don’t Care  
FN2462.3  
2
September 12, 2005  
Specifications HCTS138MS  
Absolute Maximum Ratings  
Reliability Information  
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V  
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VCC +0.5V  
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA  
DC Drain Current, Any One Output. . . . . . . . . . . . . . . . . . . . . . .±25mA  
(All Voltage Reference to the VSS Terminal)  
Thermal Resistance  
SBDIP Package . . . . . . . . . . . . . . . . . . . .  
θJA  
θJC  
73oC/W  
24oC/W  
Ceramic Flatpack Package . . . . . . . . . . . 114oC/W 29oC/W  
Maximum Package Power Dissipation at +125oC Ambient  
SBDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.68W  
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . . . . .0.44W  
If device power exceeds package dissipation capability, provide  
heat sinking or derate linearly at the following rate:  
Storage Temperature Range (TSTG) . . . . . . . . . . -65oC to +150oC  
Lead Temperature (Soldering 10sec) . . . . . . . . . . . . . . . . . .+265oC  
Junction Temperature (TJ). . . . . . . . . . . . . . . . . . . . . . . . . . .+175oC  
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1  
SBDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13.7mW/oC  
Ceramic Flatpack Package . . . . . . . . . . . . . . . . . . . . . .8.8mW/oC  
CAUTION: As with all semiconductors, stress listed under “Absolute Maximum Ratings” may be applied to devices (one at a time) without resulting in permanent dam-  
age. This is a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The conditions listed under “Electri-  
cal Performance Characteristics” are the only conditions recommended for satisfactory device operation..  
Operating Conditions  
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V  
Input Rise and Fall Times at VCC = 4.5V (TR, TF) . . . . . 500ns Max  
Operating Temperature Range (TA) . . . . . . . . . . . -55oC to +125oC  
Input Low Voltage (VIL) . . . . . . . . . . . . . . . . . . . . . . . . . 0.0V to 0.8V  
Input High Voltage (VIH) . . . . . . . . . . . . . . . . . . . . . . VCC/2 to VCC  
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS  
GROUP A  
SUBGRO  
UPS  
LIMITS  
(NOTE 1)  
PARAMETER  
SYMBOL  
CONDITIONS  
TEMPERATURE  
+25oC  
MIN  
MAX  
UNITS  
µA  
Quiescent Current  
ICC  
VCC = 5.5V,  
VIN = VCC or GND  
1
2, 3  
1
-
40  
+125oC, -55oC  
+25oC  
-
750  
µA  
Output Current (Sink)  
IOL  
IOH  
VOL  
VCC = 4.5V, VIH = 4.5V,  
VOUT = 0.4V, VIL = 0V  
7.2  
6.0  
-7.2  
-6.0  
-
-
mA  
mA  
mA  
mA  
V
2, 3  
1
+125oC, -55oC  
+25oC  
-
-
Output Current  
(Source)  
VCC = 4.5V, VIH = 4.5V,  
VOUT = VCC -0.4V,  
VIL = 0V  
2, 3  
1, 2, 3  
+125oC, -55oC  
+25oC, +125oC, -55oC  
-
Output Voltage Low  
VCC = 4.5V, VIH = 2.25V,  
IOL = 50µA, VIL = 0.8V  
0.1  
VCC = 5.5V, VIH = 2.75V,  
1, 2, 3  
1, 2, 3  
1, 2, 3  
+25oC, +125oC, -55oC  
+25oC, +125oC, -55oC  
+25oC, +125oC, -55oC  
-
0.1  
V
V
V
IOL = 50µA, VIL = 0.8V  
Output Voltage High  
VOH  
VCC = 4.5V, VIH = 2.25V,  
IOH = -50µA, VIL = 0.8V  
VCC  
-0.1  
-
-
VCC = 5.5V, VIH = 2.75V,  
IOH = -50µA, VIL = 0.8V  
VCC  
-0.1  
Input Leakage  
Current  
IIN  
FN  
VCC = 5.5V, VIN = VCC or  
GND  
1
+25oC  
-
-
-
±0.5  
±5.0  
-
µA  
µA  
-
2, 3  
+125oC, -55oC  
Noise Immunity  
Functional Test  
VCC = 4.5V, VIH = 2.25V,  
VIL = 0.8V, (Note 2)  
7, 8A, 8B  
+25oC, +125oC, -55oC  
NOTES:  
1. All voltages reference to device GND.  
2. For functional tests VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.  
FN2462.3  
3
September 12, 2005  
Specifications HCTS138MS  
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS  
GROUP A  
LIMITS  
(NOTES 1, 2)  
SUBGRO  
UPS  
PARAMETER  
SYMBOL  
CONDITIONS  
TEMPERATURE  
+25oC  
MIN  
MAX  
25  
UNITS  
ns  
Address to Output  
TPLH  
VCC = 4.5V  
9
10, 11  
9
2
2
2
2
2
2
2
2
+125oC, -55oC  
+25oC  
30  
ns  
TPHL  
TPLH  
TPHL  
VCC = 4.5V  
VCC = 4.5V  
VCC = 4.5V  
28  
ns  
10, 11  
9
+125oC, -55oC  
+25oC  
39  
ns  
Enable to Output  
26  
ns  
10, 11  
9
+125oC, -55oC  
+25oC  
31  
ns  
26  
ns  
10, 11  
+125oC, -55oC  
34  
ns  
NOTES:  
1. All voltages referenced to device GND.  
2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = 3V.  
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS  
LIMITS  
PARAMETER  
SYMBOL  
CONDITIONS  
NOTES  
TEMPERATURE  
+25oC  
MIN  
MAX  
89  
UNITS  
pF  
Capacitance Power  
Dissipation  
CPD  
VCC = 5.0V, f = 1MHz  
1
1
1
1
1
1
-
-
-
-
-
-
+125oC, -55oC  
+25oC  
102  
10  
pF  
Input Capacitance  
CIN  
VCC = 5.0V, f = 1MHz  
VCC = 4.5V  
pF  
+125oC, -55oC  
+25oC  
10  
pF  
Output Transition  
Time  
TTHL  
TTLH  
15  
ns  
+125oC, -55oC  
22  
ns  
NOTE:  
1. The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly tested.  
These parameters are characterized upon initial design release and upon design changes which affect these characteristics.  
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS  
200K RAD  
LIMITS  
(NOTES 1, 2)  
PARAMETER  
Quiescent Current  
Output Current (Sink)  
SYMBOL  
ICC  
CONDITIONS  
TEMPERATURE  
+25oC  
MIN  
-
MAX  
0.75  
-
UNITS  
mA  
VCC = 5.5V, VIN = VCC or GND  
IOL  
VCC = 4.5V, VIN = VCC or GND,  
VOUT = 0.4V  
+25oC  
6.0  
mA  
Output Current (Source)  
IOH  
VCC = 4.5V, VIN = VCC or GND,  
VOUT = VCC -0.4V  
+25oC  
-6.0  
-
mA  
FN2462.3  
4
September 12, 2005  
Specifications HCTS138MS  
TABLE 4. DC POST RADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)  
200K RAD  
LIMITS  
(NOTES 1, 2)  
CONDITIONS  
PARAMETER  
SYMBOL  
TEMPERATURE  
MIN  
MAX  
UNITS  
Output Voltage Low  
VOL  
VCC = 4.5V and 5.5V, VIH = VCC/2,  
VIL = 0.8V at 200K RAD, IOL = 50µA  
+25oC  
-
0.1  
V
Output Voltage High  
VOH  
VCC = 4.5V and 5.5V, VIH = VCC/2,  
VIL = 0.8V at 200K RAD, IOH = -50µA  
+25oC  
VCC  
-0.1  
-
V
Input Leakage Current  
IIN  
FN  
VCC = 5.5V, VIN = VCC or GND  
+25oC  
+25oC  
-
-
±5  
µA  
Noise Immunity  
Functional Test  
VCC = 4.5V, VIH = 2.25V,  
VIL = 0.8V, (Note 3)  
-
-
Address to Output  
Enable to Output  
NOTES:  
TPLH  
TPHL  
TPLH  
TPHL  
VCC = 4.5V  
VCC = 4.5V  
VCC = 4.5V  
VCC = 4.5V  
+25oC  
+25oC  
+25oC  
+25oC  
2
2
2
2
30  
39  
31  
34  
ns  
ns  
ns  
ns  
1. All voltages referenced to device GND.  
2. AC measurements assume RL = 500Ω, CL = 50pF, Input TR = TF = 3ns, VIL = GND, VIH = 3V.  
3. For functional tests VO ≥ 4.0V is recognized as a logic “1”, and VO ≤ 0.5V is recognized as a logic “0”.  
TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25oC)  
GROUP B  
PARAMETER  
SUBGROUP  
DELTA LIMIT  
12µA  
ICC  
5
5
IOL/IOH  
-15% of 0 Hour  
TABLE 6. APPLICABLE SUBGROUPS  
CONFORMANCE GROUPS  
METHOD  
100%/5004  
100%/5004  
100%/5004  
100%/5004  
100%/5004  
100%/5004  
100%/5004  
Sample/5005  
Sample/5005  
Sample/5005  
Sample/5005  
GROUP A SUBGROUPS  
READ AND RECORD  
ICC, IOL/H  
Initial Test (Preburn-In)  
1, 7, 9  
1, 7, 9  
Interim Test I (Postburn-In)  
Interim Test II (Postburn-In)  
PDA  
ICC, IOL/H  
ICC, IOL/H  
1, 7, 9  
1, 7, 9, Deltas  
1, 7, 9  
Interim Test III (Postburn-In)  
PDA  
ICC, IOL/H  
1, 7, 9, Deltas  
2, 3, 8A, 8B, 10, 11  
1, 2, 3, 7, 8A, 8B, 9, 10, 11  
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas  
1, 7, 9  
Final Test  
Group A (Note 1)  
Group B  
Subgroup B-5  
Subgroup B-6  
Subgroups 1, 2, 3, 9, 10, 11  
Group D  
NOTE:  
1, 7, 9  
1. Alternate group A inspection in accordance with method 5005 of MIL-STD-883 may be exercised.  
FN2462.3  
September 12, 2005  
5
Specifications HCTS138MS  
TABLE 7. TOTAL DOSE IRRADIATION  
TEST  
READ AND RECORD  
CONFORMANCE GROUPS  
Group E Subgroup 2  
NOTE:  
METHOD  
PRE RAD  
POST RAD  
PRE RAD  
POST RAD  
5005  
1, 7, 9  
Table 4  
1, 9  
Table 4 (Note 1)  
1. Except FN test which will be performed 100% Go/No-Go.  
TABLE 8. STATIC AND DYNAMIC BURN-IN TEST CONNECTIONS  
OSCILLATOR  
OPEN  
GROUND  
1/2 VCC = 3V ± 0.5V  
VCC = 6V ± 0.5V  
16  
50kHz  
25kHz  
STATIC BURN-IN I TEST CONNECTIONS (Note 1)  
7, 9 - 15  
STATIC BURN-IN II TEST CONNECTIONS (Note 1)  
7, 9 - 15  
DYNAMIC BURN-IN TEST CONNECTIONS (Note 2)  
4, 5, 8  
1 - 6, 8  
8
-
1 - 6, 16  
3, 6, 16  
-
-
-
7, 9 - 15  
2
1
NOTES:  
1. Each pin except VCC and GND will have a resistor of 10KΩ ± 5% for static burn-in  
2. Each pin except VCC and GND will have a resistor of 680Ω ± 5% for dynamic burn-in  
TABLE 9. IRRADIATION TEST CONNECTIONS  
OPEN  
GROUND  
VCC = 5V ± 0.5V  
1 - 6, 16  
7, 9 - 15  
8
NOTE: Each pin except VCC and GND will have a resistor of 47KΩ ± 5% for irradiation testing.  
Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures.  
FN2462.3  
September 12, 2005  
6
HCTS138MS  
Inters il Space Level Product Flow - ‘MS’  
Wafer Lot Acceptance (All Lots) Method 5007  
(Includes SEM)  
100% Interim Electrical Test 1 (T1)  
100% Delta Calculation (T0-T1)  
GAMMA Radiation Verification (Each Wafer) Method 1019,  
4 Samples/Wafer, 0 Rejects  
100% Static Burn-In 2, Condition A or B, 24 hrs. min.,  
+125oC min., Method 1015  
100% Nondestructive Bond Pull, Method 2023  
Sample - Wire Bond Pull Monitor, Method 2011  
Sample - Die Shear Monitor, Method 2019 or 2027  
100% Internal Visual Inspection, Method 2010, Condition A  
100% Temperature Cycle, Method 1010, Condition C,  
10 Cycles  
100% Constant Acceleration, Method 2001, Condition per  
Method 5004  
100% PIND, Method 2020, Condition A  
100% External Visual  
100% Interim Electrical Test 2 (T2)  
100% Delta Calculation (T0-T2)  
100% PDA 1, Method 5004 (Notes 1and 2)  
100% Dynamic Burn-In, Condition D, 240 hrs., +125oC or  
Equivalent, Method 1015  
100% Interim Electrical Test 3 (T3)  
100% Delta Calculation (T0-T3)  
100% PDA 2, Method 5004 (Note 2)  
100% Final Electrical Test  
100% Fine/Gross Leak, Method 1014  
100% Radiographic, Method 2012 (Note 3)  
100% External Visual, Method 2009  
Sample - Group A, Method 5005 (Note 4)  
100% Data Package Generation (Note 5)  
100% Serialization  
100% Initial Electrical Test (T0)  
100% Static Burn-In 1, Condition A or B, 24 hrs. min.,  
+125oC min., Method 1015  
NOTES:  
1. Failures from Interim electrical test 1 and 2 are combined for determining PDA 1.  
2. Failures from subgroup 1, 7, 9 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the failures  
from subgroup 7.  
3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004.  
4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005.  
5. Data Package Contents:  
• Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity).  
• Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage.  
• GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test  
equipment, etc. Radiation Read and Record data on file at Intersil.  
• X-Ray report and film. Includes penetrometer measurements.  
• Screening, Electrical, and Group A attributes (Screening attributes begin after package seal).  
• Lot Serial Number Sheet (Good units serial number and lot number).  
• Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test.  
• The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed  
by an authorized Quality Representative.  
FN2462.3  
7
September 12, 2005  
HCTS138MS  
AC Timing Diagrams  
VIH  
INPUT  
VS  
VIL  
TPLH  
VS  
TPHL  
VOH  
VOL  
VOH  
VOL  
OUTPUT  
TTLH  
TTHL  
80%  
80%  
20%  
20%  
OUTPUT  
AC VOLTAGE LEVELS  
PARAMETER  
VCC  
HCTS  
4.50  
3.00  
1.30  
0
UNITS  
V
V
V
V
V
VIH  
VS  
VIL  
GND  
0
AC Load Circuit  
DUT  
TEST  
POINT  
CL  
RL  
CL = 50pF  
RL = 500Ω  
FN2462.3  
8
September 12, 2005  
HCTS138MS  
GLASSIVATION:  
Die Characteris tics  
Type: SiO2  
DIE DIMENSIONS:  
85 x 101 mils  
Thickness: 13kÅ ± 2.6kÅ  
WORST CASE CURRENT DENSITY:  
METALLIZATION:  
Type: SiAl  
Metal Thickness: 11kÅ ± 1kÅ  
<2.0 x 105A/cm2  
BOND PAD SIZE:  
100µm x 100µm  
4 x 4 mils  
Metallization Mas k Layout  
HCTS138MS  
A1  
(2)  
A0  
(1)  
VCC  
(16)  
Y0  
(15)  
(14) Y1  
A2 (3)  
NC  
NC  
(13) Y2  
E1 (4)  
(12) Y3  
E2 (5)  
E3 (6)  
(11) Y4  
NC  
NC  
(8)  
GND  
(9)  
Y6  
(10)  
Y5  
(7)  
Y7  
NOTE: The die diagram is a generic plot from a similar HCS device. It is intended to indicate approximate die size and bond pad location. The  
mask series for the HCTS138 is TA14461A.  
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.  
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality  
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without  
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and  
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result  
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.  
For information regarding Intersil Corporation and its products, see www.intersil.com  
FN2462.3  
9
September 12, 2005  

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