HUF76419D3 [INTERSIL]
20A, 60V, 0.043 Ohm, N-Channel, Logic Level UltraFET Power MOSFET; 20A ， 60V ， 0.043 Ohm的N通道，逻辑电平UltraFET功率MOSFET
| 型号： | HUF76419D3 |
| 厂家： | 
Intersil |
| 描述： | 20A, 60V, 0.043 Ohm, N-Channel, Logic Level UltraFET Power MOSFET |
| 文件： | 总9页 (文件大小：334K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HUF76419D3, HUF76419D3S
Data Sheet
October 1999
File Number 4668.1
20A, 60V, 0.043 Ohm, N-Channel, Logic
Level UltraFET Power MOSFET
Packaging
Features
JEDEC TO-251AA
JEDEC TO-252AA
• Ultra Low On-Resistance
- r
- r
= 0.037Ω, VGS = 10V
= 0.043Ω, VGS = 5V
DS(ON)
DS(ON)
DRAIN
(FLANGE)
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
• Simulation Models
®
©
- Temperature Compensated PSPICE and SABER
Electrical Models
GATE
SOURCE
©
- Spice and SABER Thermal Impedance Models
- www.semi.Intersil.com
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
HUF76419D3S
HUF76419D3
• Switching Time vs R
GS
Curves
Symbol
D
S
Ordering Information
PART NUMBER
HUF76419D3
PACKAGE
BRAND
76419D
76419D
G
TO-251AA
TO-252AA
HUF76419D3S
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HUF76419D3ST
o
Absolute Maximum Ratings
T = 25 C, Unless Otherwise Specified
C
HUF76419D3,
HUF76419D3S
UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
60
60
16
V
V
V
DSS
Drain to Gate Voltage (R
GS
= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Drain Current
o
Continuous (T = 25 C, V
= 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
= 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
20
20
20
A
A
A
A
C
GS
D
D
o
Continuous (T = 25 C, V
C
GS
o
Continuous (T = 100 C, V
= 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
= 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
C
GS
D
o
Continuous (T = 100 C, V
19
C
GS
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
Figure 4
DM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .UIS
Figures 6, 17, 18
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
Derate Above 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
0.5
W
W/ C
D
o
o
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T , T
J
-55 to 175
C
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
Package Body for 10s, See Techbrief TB334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
o
300
260
C
C
L
o
pkg
NOTE:
1. T = 25 C to 150 C.
o
o
J
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
CAUTION: These devices are sensitive to electrostatic discharge. Follow proper ESD Handling Procedures.
4-1
UltraFET™ is a trademark of Intersil Corporation. PSPICE® is a registered trademark of MicroSim Corporation.
©
SABER is a Copyright of Analogy Inc. 1-888-INTERSIL or 407-727-9207 | Copyright © Intersil Corporation 1999.
HUF76419D3, HUF76419D3S
o
Electrical Specifications
T = 25 C, Unless Otherwise Specified
C
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
BV
DSS
I
I
= 250µA, V
= 250µA, V
= 0V (Figure 12)
o
60
55
-
-
-
-
-
-
-
-
V
D
GS
GS
GS
GS
= 0V , T = -40 C (Figure 12)
C
V
D
Zero Gate Voltage Drain Current
I
V
V
V
= 55V, V
= 50V, V
= 0V
= 0V, T = 150 C
1
µA
µA
nA
DSS
DS
DS
GS
o
-
250
100
C
Gate to Source Leakage Current
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
Drain to Source On Resistance
I
=
16V
-
GSS
V
V
= V , I = 250µA (Figure 11)
1
-
-
3
V
Ω
Ω
Ω
GS(TH)
GS
DS
D
GS
GS
GS
r
I
I
I
= 20A, V
= 20A, V
= 19A, V
= 10V (Figures 9, 10)
= 5V (Figure 9)
0.031
0.036
0.038
0.037
0.043
0.046
DS(ON)
D
D
D
-
= 4.5V (Figure 9)
-
THERMAL SPECIFICATIONS
o
Thermal Resistance Junction to Case
R
TO-251,TO-252
-
-
-
-
2.00
100
C/W
θJC
o
Thermal Resistance Junction to
Ambient
R
C/W
θJA
SWITCHING SPECIFICATIONS (V
= 4.5V)
GS
Turn-On Time
t
V
V
= 30V, I = 19A
-
-
-
-
-
-
-
12
124
28
50
-
205
ns
ns
ns
ns
ns
ns
ON
DD
D
= 4.5V, R
= 13Ω
GS
GS
Turn-On Delay Time
Rise Time
t
-
d(ON)
(Figures 15, 21, 22)
t
-
r
Turn-Off Delay Time
Fall Time
t
-
-
d(OFF)
t
f
Turn-Off Time
t
115
OFF
SWITCHING SPECIFICATIONS (V
Turn-On Time
= 10V)
t
GS
V
V
R
= 30V, I = 20A
D
= 10V,
= 13Ω
-
-
-
-
-
-
-
62
ns
ns
ns
ns
ns
ns
ON
DD
GS
Turn-On Delay Time
Rise Time
t
6.5
35
50
50
-
-
d(ON)
GS
t
-
r
(Figures 16, 21, 22)
Turn-Off Delay Time
Fall Time
t
-
-
d(OFF)
t
f
Turn-Off Time
t
150
OFF
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Q
V
V
V
= 0V to 10V
= 0V to 5V
= 0V to 1V
V
= 30V,
-
-
-
-
-
23
12.5
0.9
2.7
5.9
27.5
15
1.05
-
nC
nC
nC
nC
nC
g(TOT)
GS
GS
GS
DD
= 20A,
I
I
D
Gate Charge at 5V
Q
g(5)
= 1.0mA
g(REF)
Threshold Gate Charge
Q
g(TH)
(Figures 14, 19, 20)
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
CAPACITANCE SPECIFICATIONS
Input Capacitance
Q
gs
gd
Q
-
C
V
= 25V, V = 0V,
GS
-
-
-
900
250
45
-
-
-
pF
pF
pF
ISS
DS
f = 1MHz
(Figure 13)
Output Capacitance
C
OSS
RSS
Reverse Transfer Capacitance
C
Source to Drain Diode Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
1.25
1.0
UNITS
V
Source to Drain Diode Voltage
V
I
I
I
I
= 20A
= 10A
-
-
-
-
-
-
-
-
SD
SD
SD
SD
SD
V
Reverse Recovery Time
t
= 20A, dI /dt = 100A/µs
SD
74
ns
rr
Reverse Recovered Charge
Q
= 20A, dI /dt = 100A/µs
SD
200
nC
RR
4-2
HUF76419D3, HUF76419D3S
Typical Performance Curves
1.2
1.0
0.8
0.6
0.4
0.2
0
25
20
15
10
5
V
= 10V
GS
V
= 4.5V
GS
0
0
25
50
75
100
150
175
125
o
25
50
75
100
125
150
175
o
T
, CASE TEMPERATURE ( C)
T , CASE TEMPERATURE ( C)
C
C
FIGURE 1. NORMALIZED POWER DISSIPATION vs
CASE TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
DUTY CYCLE - DESCENDING ORDER
0.5
1
0.2
0.1
0.05
0.02
0.01
P
DM
0.1
t
1
t
2
NOTES:
DUTY FACTOR: D = t /t
1
2
SINGLE PULSE
PEAK T = P
x Z
x R + T
J
DM
θJC
θJC C
0.01
-5
-4
10
-3
10
-2
-1
0
1
10
10
t, RECTANGULAR PULSE DURATION (s)
10
10
10
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
500
100
o
= 25 C
T
C
FOR TEMPERATURES
o
ABOVE 25 C DERATE PEAK
CURRENT AS FOLLOWS:
175 - T
V
= 10V
C
GS
I = I
25
150
V
= 5V
GS
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10
-5
-4
-3
10
-2
10
-1
10
0
1
10
10
10
10
t, PULSE WIDTH (s)
FIGURE 4. PEAK CURRENT CAPABILITY
4-3
HUF76419D3, HUF76419D3S
Typical Performance Curves (Continued)
200
100
200
100
If R = 0
= (L)(I )/(1.3*RATED BV
t
- V )
DD
AV
If R ≠ 0
= (L/R)ln[(I *R)/(1.3*RATED BV
AS
DSS
t
AV
- V ) +1]
DD
AS DSS
100µs
o
STARTING T = 25 C
J
OPERATION IN THIS
AREA MAY BE
10
10
LIMITED BY r
DS(ON)
1ms
10ms
100
o
STARTING T = 150 C
J
SINGLE PULSE
= MAX RATED T = 25 C
o
T
J
C
1
1
0.01
1
10
, DRAIN TO SOURCE VOLTAGE (V)
200
0.1
1
10
100
V
t
, TIME IN AVALANCHE (ms)
DS
AV
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
50
50
PULSE DURATION = 80µs
V
= 10V
GS
DUTY CYCLE = 0.5% MAX
V
= 15V
DD
40
30
20
40
30
20
10
0
V
= 4V
GS
V
= 5V
GS
V
= 3.5V
GS
o
T
= 25 C
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
J
10
0
o
T
= 175 C
J
o
T
= -55 C
J
o
V
= 3V
GS
T
= 25 C
C
1
2
3
4
5
0
1
2
3
4
V
, GATE TO SOURCE VOLTAGE (V)
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
GS
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. SATURATION CHARACTERISTICS
50
2.5
2.0
1.5
PULSE DURATION = 80µs
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
DUTY CYCLE = 0.5% MAX
o
T
= 25 C
C
45
40
35
I
= 20A
I
= 10A
D
D
1.0
0.5
30
25
V
= 10V, I = 20A
D
GS
-80
-40
0
40
80
120
160
200
2
4
6
8
10
o
V
, GATE TO SOURCE VOLTAGE (V)
T , JUNCTION TEMPERATURE ( C)
GS
J
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
4-4
HUF76419D3, HUF76419D3S
Typical Performance Curves (Continued)
1.2
1.1
1.0
0.9
1.2
1.0
0.8
I
= 250µA
D
V
= V , I = 250µA
DS
GS
D
0.6
0.4
-80
-40
0
40
80
120
160
200
-80
-40
0
40
80
120
160
200
o
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
10
2000
V
= 30V
DD
C
= C
+ C
ISS
GS GD
1000
8
6
4
2
0
C
≅ C
DS
+ C
GD
OSS
WAVEFORMS IN
DESCENDING ORDER:
100
20
I
I
= 20A
= 10A
D
D
V
= 0V, f = 1MHz
1.0
GS
C
= C
GD
RSS
0
5
10
15
20
25
30
60
0.1
10
Q , GATE CHARGE (nC)
g
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
300
180
V
= 4.5V, V = 30V, I = 19A
DD D
GS
V
= 10V, V
DD
= 30V, I = 20A
D
t
GS
r
250
200
150
100
150
120
90
t
d(OFF)
t
f
t
f
t
r
60
t
d(OFF)
50
0
30
0
t
d(ON)
t
d(ON)
0
10
20
30
40
50
0
10
20
30
40
50
R
, GATE TO SOURCE RESISTANCE (Ω)
GS
R
, GATE TO SOURCE RESISTANCE (Ω)
GS
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
4-5
HUF76419D3, HUF76419D3S
Test Circuits and Waveforms
V
DS
BV
DSS
L
t
P
V
DS
I
VARY t TO OBTAIN
P
AS
+
V
DD
R
REQUIRED PEAK I
AS
G
V
DD
-
V
GS
DUT
t
P
I
0V
AS
0
0.01Ω
t
AV
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
V
DS
V
Q
DD
R
g(TOT)
L
V
DS
V
= 10V
GS
V
Q
GS
g(5)
+
-
V
DD
V
= 5V
V
GS
GS
DUT
V
= 1V
GS
I
0
g(REF)
Q
g(TH)
Q
Q
gd
gs
I
g(REF)
0
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
V
t
t
DS
ON
OFF
t
d(OFF)
t
d(ON)
t
t
f
R
L
r
V
DS
90%
90%
+
V
GS
V
DD
10%
10%
0
-
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
0
FIGURE 21. SWITCHING TIME TEST CIRCUIT
FIGURE 22. SWITCHING TIME WAVEFORM
4-6
HUF76419D3, HUF76419D3S
PSPICE Electrical Model
.SUBCKT HUF76419D3 2 1 3 ;
rev 8 July 1999
CA 12 8 1.20e-9
CB 15 14 1.20e-9
CIN 6 8 8.49e-10
LDRAIN
DPLCAP
DRAIN
2
5
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
10
RLDRAIN
RSLC1
51
DBREAK
+
RSLC2
5
EBREAK 11 7 17 18 68.35
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
ESLC
11
51
-
50
+
-
17
18
-
DBODY
RDRAIN
6
8
EBREAK
ESG
EVTHRES
+
+
16
21
-
19
8
MWEAK
LGATE
EVTEMP
+
IT 8 17 1
RGATE
GATE
1
6
-
18
22
MMED
9
LDRAIN 2 5 1.0e-9
LGATE 1 9 2.51e-9
LSOURCE 3 7 3.57e-9
20
MSTRO
8
RLGATE
LSOURCE
CIN
SOURCE
3
7
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RSOURCE
RLSOURCE
S1A
S2A
RBREAK
12
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1.12e-2
RGATE 9 20 3.12
RLDRAIN 2 5 10
RLGATE 1 9 25.1
RLSOURCE 3 7 35.7
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 1.60e-2
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
15
13
8
14
13
17
18
RVTEMP
19
-
S1B
S2B
13
CB
CA
IT
14
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
22
RVTHRES
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*98),3))}
.MODEL DBODYMOD D (IS = 8.51e-13 RS = 1.03e-2 TRS1 = 1.08e-3 TRS2 = 9.91e-7 CJO = 1.06e-9 TT = 4.90e-8 M = 0.5)
.MODEL DBREAKMOD D (RS = 2.39e-1 TRS1 = 1.23e-4 TRS2 = 1.11e-6)
.MODEL DPLCAPMOD D (CJO = 7.42e-10 IS = 1e-30 M = 0.85)
.MODEL MMEDMOD NMOS (VTO = 1.98 KP = 2.1 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.12)
.MODEL MSTROMOD NMOS (VTO = 2.33 KP = 50 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.75 KP = 0.08 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 31.2 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.14e-3 TC2 = 1.02e-9)
.MODEL RDRAINMOD RES (TC1 = 1.19e-2 TC2 = 3.22e-5)
.MODEL RSLCMOD RES (TC1 = 9.91e-4 TC2 = 3.17e-5)
.MODEL RSOURCEMOD RES (TC1 = 1.0e-3 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 = -2.34e-3 TC2 = -5.33e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.45e-3 TC2 = 0)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.5 VOFF= -3.0)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.0 VOFF= -5.5)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.2 VOFF= 0.1)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.1 VOFF= -0.2)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
4-7
HUF76419D3, HUF76419D3S
SABER Electrical Model
REV 8 July 1999
template huf76419d3 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is = 8.51e-13, cjo = 1.06e-9, tt = 4.90e-8, m = 0.50)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 7.42e-10, is = 1e-30, m = 0.85 )
m..model mmedmod = (type=_n, vto = 1.98, kp = 2.10, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 2.33, kp = 50, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.75, kp = 0.08, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5.5, voff = -3.0)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -3.0, voff = -5.5)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.2, voff = 0.1)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.1, voff = -0.2)
LDRAIN
RLDRAIN
RDBODY
DPLCAP
DRAIN
2
5
10
RSLC1
51
RDBREAK
72
DBREAK
11
RSLC2
c.ca n12 n8 = 1.2e-9
c.cb n15 n14 = 1.2e-9
c.cin n6 n8 = 8.49e-10
ISCL
50
-
d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod
71
RDRAIN
6
8
ESG
EVTHRES
+
+
16
21
-
19
8
MWEAK
LGATE
EVTEMP
+
i.it n8 n17 = 1
DBODY
RGATE
GATE
1
6
-
18
22
EBREAK
+
MMED
l.ldrain n2 n5 = 1.0e-9
l.lgate n1 n9 = 2.51e-9
l.lsource n3 n7 = 3.57e-9
9
20
MSTRO
8
17
18
-
RLGATE
LSOURCE
CIN
SOURCE
3
7
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
RSOURCE
RLSOURCE
S1A
S2A
14
13
RBREAK
12
res.rbreak n17 n18 = 1, tc1 = 1.14e-3, tc2 = 1.02e-9
res.rdbody n71 n5 = 1.03e-2, tc1 = 1.08e-3, tc2 = 9.91e-7
res.rdbreak n72 n5 = 2.39e-1, tc1 = 1.23e-4, tc2 = 1.11e-6
res.rdrain n50 n16 = 1.12e-2, tc1 = 1.19e-2, tc2 = 3.22e-5
res.rgate n9 n20 = 3.12
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 25.1
res.rlsource n3 n7 = 35.7
15
13
17
18
8
RVTEMP
19
-
S1B
S2B
13
CB
CA
IT
14
+
+
VBAT
6
8
5
8
EGS
EDS
+
res.rslc1 n5 n51 = 1e-6, tc1 = 9.91e-4, tc2 =3.17e-5
res.rslc2 n5 n50 = 1e3
-
-
8
22
res.rsource n8 n7 = 1.60e-2, tc1 = 1e-3, tc2 =0
res.rvtemp n18 n19 = 1, tc1 = -1.45e-3, tc2 = 0
res.rvthres n22 n8 = 1, tc1 = -2.34e-3, tc2 = -5.33e-6
RVTHRES
spe.ebreak n11 n7 n17 n18 = 68.35
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/98))** 3))
}
}
4-8
HUF76419D3, HUF76419D3S
}
SPICE Thermal Model
JUNCTION
th
REV 16 July 1999
HUF76419D3T
CTHERM1 th 6 1.35e-3
CTHERM2 6 5 1.50e-2
CTHERM3 5 4 5.50e-3
CTHERM4 4 3 3.00e-3
CTHERM5 3 2 1.20e-2
CTHERM6 2 tl 3.00
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
CTHERM1
6
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
RTHERM1 th 6 1.32e-2
RTHERM2 6 5 3.30e-2
RTHERM3 5 4 9.28e-2
RTHERM4 4 3 5.21e-1
RTHERM5 3 2 7.86e-1
RTHERM6 2 tl 1.04e-1
5
SABER Thermal Model
SABER thermal model HUF76419D3T
4
3
2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 1.35e-3
ctherm.ctherm2 6 5 = 1.50e-2
ctherm.ctherm3 5 4 = 5.50e-3
ctherm.ctherm4 4 3 = 3.00e-3
ctherm.ctherm5 3 2 = 1.20e-2
ctherm.ctherm6 2 tl = 3.00
rtherm.rtherm1 th 6 = 1.32e-2
rtherm.rtherm2 6 5 = 3.30e-2
rtherm.rtherm3 5 4 = 9.28e-2
rtherm.rtherm4 4 3 = 5.21e-1
rtherm.rtherm5 3 2 = 7.86e-1
rtherm.rtherm6 2 tl = 1.04e-1
tl
CASE
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA
EUROPE
ASIA
Intersil Corporation
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
Intersil (Taiwan) Ltd.
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
4-9
相关型号：
HUF76419D3ST_NL
Power Field-Effect Transistor, 20A I(D), 60V, 0.043ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252AA,
FAIRCHILD
HUF76419S3ST_F085
Power Field-Effect Transistor, 29A I(D), 60V, 0.035ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-263AB, ROHS COMPLIANT PACKAGE-3/2
FAIRCHILD
HUF76419S3ST_NL
Power Field-Effect Transistor, 29A I(D), 60V, 0.04ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-263AB,
FAIRCHILD
©2020 ICPDF网 联系我们和版权申明