ICL8069DMSQ [INTERSIL]
Low Voltage Reference; 低电压基准
| 型号： | ICL8069DMSQ |
| 厂家： | 
Intersil |
| 描述： | Low Voltage Reference |
| 文件： | 总6页 (文件大小：121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICL8069
®
Data Sheet
J anuary 2004
FN3172.3
Low Voltage Reference
Features
The ICL8069 is a 1.2V temperature-compensated voltage
reference. It uses the band-gap principle to achieve excel-
lent stability and low noise at reverse currents down to 50µA.
Applications include analog-to-digital converters, digital-to-
analog converters, threshold detectors, and voltage
regulators. Its low power consumption makes it especially
suitable for battery operated equipment.
• Low Bias Current (Min) . . . . . . . . . . . . . . . . . . . . . . .50µA
• Low Dynamic Impedance
• Low Reverse Voltage
• Low Cost
Pinouts
ICL8069 (SOIC)
TOP VIEW
Ordering Information
TEMP.
PART
NUMBER
MAXIMUM RANGE
PKG.
DWG. #
o
NC
NC
NC
V-
1
2
3
4
8
7
6
5
V+
TEMPCO
( C)
PACKAGE
o
ICL8069CCZR 0.005%/ C
0 to 70 SIPPackage Z3.05
(TO-92)
NC
NC
NC
o
ICL8069DCZR 0.01%/ C
0 to 70 SIPPackage Z3.05
(TO-92)
o
ICL8069CCBA 0.005%/ C
0 to 70 8 Ld SOlC
M8.15
ICL8069 (SIP TO-92)
TOP VIEW
NC
1
V+
2
V-
3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ICL8069
Functional Block Diagrams
SIMPLE REFERENCE (1.2V OR LESS)
+5V
6.8kΩ
ICL8069
V+
V-
10kΩ
4.7µF
(NOTE 1)
V
OUT
BUFFERED 10V REFERENCE USING A SINGLE SUPPLY
+15V
ICL8069
V-
V+
7
15kΩ
2
3
-
6
8
LM108
+
5
+10V
OUT
1kΩ
1kΩ
4
0.01µF
8.2kΩ
DOUBLE REGULATED 100mV REFERENCE FOR ICL7107 ONE-CHIP DPM CIRCUIT
+5V
2.2kΩ
ICL7107
+V
10kΩ
V+
ICL8069
1kΩ
V-
REF HI
COMMON
REF LO
2
ICL8069
Absolute Maximum Ratings
Thermal Information
o
o
Reverse Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Note 3
Forward Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
Reverse Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
Thermal Resistance (Typical, Note 1)
θ
( C/W)
θ
( C/W)
JA
JC
SOIC Package . . . . . . . . . . . . . . . . . . .
SIP (TO-92) Package. . . . . . . . . . . . . .
170
200
N/A
N/A
Power Dissipation Limited by MAX Forward/Reverse Current
Maximum Junction Temperature (SOIC Package) . . . . . . . . .150 C
o
Operating Conditions
o
o
Maximum Storage Temperature Range . . . . . . . . . -65 C to 150 C
Temperature Ranges
ICL8069C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 70 C
o
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C
o
o
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
o
Electrical Specifications
T
= 25 C Unless Otherwise Specified
A
PARAMETER
Reverse Breakdown Voltage
TEST CONDITIONS
= 500µA
MIN
TYP
1.23
15
1
MAX
UNITS
I
1.20
1.25
V
R
Reverse Breakdown Voltage Change
Reverse Dynamic Impedance
50µA ≤ l ≤ 5mA
-
-
-
-
-
-
20
2
2
1
-
mV
R
l
l
l
= 50µA
= 500µA
= 500µA
Ω
R
R
F
1
Ω
V
Forward Voltage Drop
RMS Noise Voltage
Long Term Stability
0.7
5
10Hz ≤ F ≤ 10kHz, l = 500µA
µV
R
o
l
= 4.75mA, T = 25 C
1
-
ppm/kHR
R
A
Breakdown Voltage Temperature Coefficient
ICL8069C
I = 500µA, T = Operating
R A
Temperature Range
o
-
-
-
-
-
0.005
0.01
5
%/ C
o
ICL8069D
Reverse Current Range
NOTES:
%/ C
1.18V to 1.27V
0.050
mA
2. If circuit strays in excess of 200pF are anticipated, a 4.7µF shunt capacitor will ensure stability under all operating conditions.
3. In normal use, the reverse voltage cannot exceed the reference voltage. However when plugging units into a powered-up test fixture, an
instantaneous voltage equal to the compliance of the test circuit will be seen. This should not exceed 20V.
3
ICL8069
Typical Performance Curves
14
12
10
8
100mA
1mA
100µ
10µ
o
-55 C
6
4
o
25 C,
o
2
125 C
o
125 C
o
-55 C
0
o
25 C
1µ
-2
10µ
0.2
0.4
0.6
0.8
1.0
1.2
1.4
100µ
1mA
10mA
REVERSE VOLTAGE (V)
REVERSE CURRENT (A)
FIGURE 1. VOLTAGE CHANGE AS A FUNCTION OF
REVERSE CURRENT
FIGURE 2. REVERSE VOLTAGE AS A FUNCTION OF
CURRENT
1.245
I
= 500µA
R
1.240
1.235
1.230
1.225
1.220
1.215
-50
-25
0
25
50
o
75
100
125
TEMPERATURE ( C)
FIGURE 3. REVERSE VOLTAGE AS A FUNCTION OF TEMPERATURE
4
ICL8069
Single-In-Line Plas tic Packages (SIP)
L
Z3.05 (JEDEC STYLE TO-92 MODIFIED)
3 LEAD PLASTIC SINGLE-IN-LINE PACKAGE
e1
W
e
INCHES
MIN
MILLIMETERS
SYMBOL
MAX
0.195
0.020
0.155
0.055
0.105
0.610
0.095
0.060
0.022
0.195
MIN
4.32
0.36
3.30
1.14
2.41
12.70
2.16
1.14
0.41
4.45
MAX
4.95
0.51
3.94
1.40
2.67
15.49
2.41
1.52
0.56
4.95
NOTES
D
A
b
0.170
0.014
0.130
0.045
0.095
0.500
0.085
0.045
0.016
0.175
1
2
E
1
E-PIN Ø 0.0625
e
-
R
A
e1
L
-
-
b
E
R
S1
W
D
α
-
S1
-
2
1
(2X)
α
o
o
o
o
4
6
4
6
-
NOTES:
Rev. 0 2/94
1. Package body dimensions do not include any mold flash or pro-
trusions.
2. Package outline dimensions do not include burrs.
3. Controlling dimension: INCH.
5
ICL8069
Small Outline Plas tic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
N
INDEX
AREA
0.25(0.010)
M
B M
H
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
NOTES
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
1
2
3
L
-
9
SEATING PLANE
A
0.0075
0.1890
0.1497
0.0098
0.1968
0.1574
-
-A-
o
h x 45
D
3
4
-C-
α
µ
0.050 BSC
1.27 BSC
-
e
A1
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
C
B
0.10(0.004)
5
0.25(0.010) M
C A M B S
L
6
N
α
8
8
7
NOTES:
o
o
o
o
0
8
0
8
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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