ICM7228AIBI_技术文档

ICM7228

8-Digit, Microprocessor-

Compatible, LED Display Decoder Driver

August 1997

Features

Description

• Improved 2nd Source to Maxim ICM7218

• Fast Write Access Time of 200ns

The Intersil ICM7228 display driver interfaces microproces-

sors to an 8-digit, 7-segment, numeric LED display. Included

on chip are two types of 7-segment decoder, multiplex scan

circuitry, LED display segment drivers, LED display digit

drivers and an 8-byte static memory as display RAM.

• Multiple Microprocessor Compatible Versions

• Hexadecimal, Code B and No Decode Modes

• Individual Segment Control with “No Decode” Feature

• Digit and Segment Drivers On-Chip

• Non-Overlapping Digits Drive

Data can be written to the ICM7228A and ICM7228B’s display

RAM in sequential 8-digit update or in single-digit update for-

mat. Data is written to the ICM7228C and ICM7228D display

RAM in parallel random access format. The ICM7228A and

ICM7228C drive common anode displays. The ICM7228B and

ICM7228D drive common cathode displays. All versions can

display the RAM data as either Hexadecimal or Code B format.

The ICM7228A and ICM7228B incorporate a No Decode mode

allowing each bit of each digit's RAM word to drive individual

display segments resulting in independent control of all display

segments. As a result, bargraph and other irregular display

segments and formats can be driven directly by this chip.

• Common Anode and Common Cathode LED Versions

• Low Power CMOS Architecture

• Single 5V Supply

Applications

• Instrumentation

• Test Equipment

• Hand Held Instruments

• Bargraph Displays

The Intersil ICM7228 is an alternative to both the Maxim

ICM7218 and the Intersil ICM7218 display drivers. Notice that

the ICM7228A/B has an additional single digit access mode.

This could make the Intersil ICM7218A/B software incompatible

with ICM7228A/B operation.

• Numeric and Non-Numeric Panel Displays

• High and Low Temperature Environments where LCD

Display Integrity is Compromised

Ordering Information

o

PART NUMBER

ICM7228AIPI

DATA ENTRY PROTOCOL

Sequential

Random

DISPLAY TYPE

Common Anode

Common Cathode

Common Anode

Common Cathode

Common Anode

Common Cathode

Common Anode

Common Cathode

Common Anode

Common Cathode

Common Anode

Common Cathode

Common Anode

Common Cathode

Common Anode

Common Cathode

TEMP. RANGE ( C)

PACKAGE

28 Ld PDIP

PKG. NO.

E28.6

-40 to 85

ICM7228BIPI

-40 to 85

28 Ld PDIP

E28.6

F28.6

M28.3

F28.6

ICM7228CIPI

-40 to 85

28 Ld PDIP

ICM7228DIPI

Random

-40 to 85

28 Ld PDIP

ICM7228AIJI

Sequential

Random

-40 to 85

28 Ld CERDIP

28 Ld SOIC

ICM7228BIJI

-40 to 85

ICM7228CIJI

-40 to 85

ICM7228DIJI

Random

-40 to 85

ICM7228AIBI

Sequential

Random

-40 to 85

ICM7228BIBI

-40 to 85

28 Ld SOlC

ICM7228CIBI

-40 to 85

28 Ld SOlC

ICM7228DIBI

Random

-40 to 85

28 Ld SOlC

ICM7228AMJI883B

ICM7228BMJI883B

ICM7228CMJI883B

ICM7228DMJI883B

Sequential

Random

-55 to 125

28 Ld CERDIP

Random

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

File Number 3160.1

9-17

ICM7228

Pinouts

ICM7228A

(CERDIP, PDIP, SOIC)

COMMON ANODE

TOP VIEW

ICM7228B

(CERDIP, PDIP, SOIC)

COMMON CATHODE

TOP VIEW

SEG c

SEG e

SEG b

DP

1

2

3

4

5

6

7

8

9

28 V

DIGIT 4

DIGIT 6

DIGIT 3

DIGIT 1

1

2

3

4

5

6

7

8

9

28 V

SS

27 SEG a

27 DIGIT 7

26 SEG g

25 SEG d

24 SEG f

26 DIGIT 5

25 DIGIT 2

24 DIGIT 8

23 SEG g

22 SEG f

ID6 (HEXA/CODE B)

ID5 (DECODE)

ID7 (DATA COMING)

WRITE

ID6 (HEXA/CODE B)

ID5 (DECODE)

ID7 (DATA COMING)

WRITE

23 DIGIT 3

22 DIGIT 6

21 DIGIT 7

21 SEG e

MODE

20

MODE

20

DIGIT 4

SEG c

ID4 (SHUTDOWN) 10

ID1 11

19 V

ID4 (SHUTDOWN) 10

ID1 11

19 V

DD

18 DIGIT 8

17 DIGIT 5

16 DIGIT 2

15 DIGIT 1

18 SEG d

17 SEG b

16 SEG a

15 DP

ID0 12

ID2 13

ID3 14

ICM7228C

ICM7228D

(CERDIP, PDIP, SOIC)

COMMON ANODE

TOP VIEW

(CERDIP, PDIP, SOIC)

COMMON CATHODE

TOP VIEW

SEG c

1

2

3

4

5

6

7

8

9

28 V

DIGIT 4

1

2

3

4

5

6

7

8

9

28 V

SS

SEG e

SEG b

27 SEG a

26 SEG g

25 SEG d

24 SEG f

23 DIGIT 3

22 DIGIT 6

21 DIGIT 7

DIGIT 6

DIGIT 3

27 DIGIT 7

26 DIGIT 5

25 DIGIT 2

24 DIGIT 8

23 SEG g

22 SEG f

DP

DIGIT 1

DA0 (DIGIT ADDRESS 0)

DA1 (DIGIT ADDRESS 1)

ID7 (INPUT DP)

DA0 (DIGIT ADDRESS 0)

DA1 (DIGIT ADDRESS 1)

ID7 (INPUT DP)

WRITE

21 SEG e

HEXA/CODE B/SHUTDOWN

20

HEXA/CODE B/SHUTDOWN

20

DIGIT 4

SEG c

DA2 (DIGIT ADDRESS 2) 10

19 V

DA2 (DIGIT ADDRESS 2) 10

19 V

DD

ID1 11

ID0 12

ID2 13

ID3 14

18 DIGIT 8

17 DIGIT 5

16 DIGIT 2

15 DIGIT 1

ID1 11

ID0 12

ID2 13

ID3 14

18 SEG d

17 SEG b

16 SEG a

15 DP

9-18

ICM7228

Functional Block Diagram

ICM7228A, ICM7228B

ICM7228C, ICM7228D

ID0 - ID7

INPUT

DATA

ID4 - ID7

CONTROL

INPUTS MODE

8

HEXADECIMAL/

CODE B/

SHUTDOWN

ID0 - ID3

ID7

DATA INPUT

DA0 - DA2

DIGIT

ADDRESS

WRITE

1

WRITE

1

4

8

1

5

3

DECODE

SHUTDOWN

CONTROL

LOGIC

1

SHUTDOWN

THREE LEVEL

INPUT LOGIC

HEXA/CODE B

1

8

WRITE ADDRESS

COUNTER

8

WRITE ADDRESS

COUNTER

8-BYTE

STATIC

RAM

8-BYTE

STATIC

RAM

8

1

8

1

7

4

READ

ADDRESS, DIGIT

MULTIPLEXER

8

READ

ADDRESS

MULTIPLEXER

8

4

HEXADECIMAL/

CODE B

3

5

7

DECODER

MULTIPLEX

OSCILLATOR

HEXADECIMAL/

CODE B

DECODER

MULTIPLEX

OSCILLATOR

7

1

DECODE

NO-DECODE

8

1

8

1

7

INTERDIGIT

BLANKING

DECIMAL

POINT

7

INTERDIGIT

BLANKING

DECIMAL

POINT

8 SEGMENT

DRIVERS

8 DIGIT

DRIVERS

8 SEGMENT

DRIVERS

8 DIGIT

DRIVERS

9-19

ICM7228

Absolute Maximum Ratings

Thermal Information

o

Supply Voltage (V

DD

Digit Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500mA

Segment Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . .100mA

Input Voltage (Note 1) (Any Terminal). . .(V -0.3V)<V <(V +0.3V)

SS IN DD

- V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V

SS

Thermal Resistance (Typical, Note 2)

CERDIP Package . . . . . . . . . . . . . . . .

PDIP Package . . . . . . . . . . . . . . . . . . .

SOIC Package. . . . . . . . . . . . . . . . . . .

Maximum Junction Temperature

θ

( C/W)

θ

( C/W)

JA

JC

55

60

75

12

N/A

o

IPI, IBI Sufﬁx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 C

MJI, IJI Sufﬁx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 C

Maximum Storage Temperature Range . . . . . . . . . .-65 C to 150 C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300 C

Operating Conditions

o

Operating Temperature Range

IPI, IJI, IBI Sufﬁx . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C

MJl Sufﬁx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C

o

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTES:

1. Due to the SCR structure inherent in the CMOS process used to fabricate these devices, connecting any terminal to a voltage greater

than V

or less then V may cause destructive device latchup. For this reason, it is recommended that no inputs row sources operating

DD

SS

on a different power supply be applied to the device before its own supply is established, and when using multiple supply systems the

supply to the ICM7228 should be turned on ﬁrst.

2. θ is measured with the component mounted on an evaluation PC board in free air.

JA

Electrical Speciﬁcations

V

= +5.0V ±10%, V = 0V, Unless Otherwise Speciﬁed

SS

DD

INDUSTRIAL TEMPERATURE RANGE, IPI, IJI, LBI DEVICES

o

T

= 25 C

-40 C TO 85 C

A

PARAMETER

TEST CONDITIONS

Operating

MIN

TYP

-

MAX

6

MIN

TYP

-

MAX

UNITS

Supply Voltage Range, V

4

2

-

4

2

-

6

V

SUPPLY

Power Down Mode

-

Quiescent Supply Current, I

Shutdown, ICM7228A, IMC7228B

Shutdown, 7228C, 7228D

1

100

450

1

100

450

µA

Q

-

2.5

200

-

2.5

200

Operating Supply Current, I

Common Anode, ICM7228A/C

-

DD

Segments = ON; Outputs = OPEN

Common Anode, ICM7228A/C

Segments = OFF; Outputs = OPEN

-

100

250

175

-

450

-

100

450

-

Common Cathode, ICM7228B/D

Segments = ON; Outputs = OPEN

-

250

Common Cathode, ICM7228B/D

Segments = OFF; Outputs = OPEN

-

200

50

-

175

40

-

175

Digit Drive Current, I

Common Anode, ICM7228A/C

-

mA

µA

mA

µA

DIG

V

= V - 2.0V

DD

OUT

Common Cathode, ICM7228B/D

= V + 1.0V

-

V

OUT

SS

Digit Leakage Current, I

Shutdown Mode, V

= 2.0V

1

100

-

1

-

100

-

DLK

OUT

Common Anode, ICM7228A/C

Shutdown Mode, V = 5.0V

-

1

-

OUT

Common Cathode, 7228B/D

Peak Segment Drive Current, I

SEG

Common Anode, ICM7228A/C

20

10

-

25

12

1

20

10

-

V

= V + 1.0V

SS

OUT

Common Cathode, 7228B/D

= V - 2.0V

-

V

OUT

DD

Segment Leakage Current, I

Shutdown Mode, V

= V

DD

50

1

-

50

1

SLK

OUT

Common Anode, ICM7228A/C

Shutdown Mode, V = V

-

1

-

OUT

SS

Common Cathode, ICM7228B/D

Input Leakage Current, I

IL

All Inputs Except Pin 9

-

ICM7228C, ICM7228D V = V

IN

SS

All Inputs Except Pin 9

-

-1

-

-1

ICM7228C, ICM7228D V = 5.0V

IN

9-20

ICM7228

Electrical Speciﬁcations

V

= +5.0V ±10%, V = 0V, Unless Otherwise Speciﬁed

DD

SS

INDUSTRIAL TEMPERATURE RANGE, IPI, IJI, LBI DEVICES (Continued)

o

T

= 25 C

-40 C TO 85 C

A

PARAMETER

TEST CONDITIONS

MIN

-

TYP

390

10

MAX

MIN

TYP

MAX

UNITS

Hz

Display Scan Rate, f

Per Digit

-

2

390

-

MUX

Inter-Digit Blanking Time, t

2

-

µs

IDB

Logical “1” Input Voltage, V

Three Level Input: Pin 9

4.2

-

4.2

V

INH

ICM7228C, ICM7228D Hexadecimal

V

= 5V

DD

Floating Input, V

Three Level Input: Pin 9

ICM7228C, ICM7228D Code B

2.0

-

3.0

0.8

2.0

-

3.0

0.8

V

INF

V

= 5V

DD

Logical “0” Input Voltage, V

Three Level Input: Pin 9

INL

ICM7228C, ICM7228D Shutdown

V

= 5V

DD

Three Level Input Impedance, Z

IN

V

= 5V

50

-

50

-

kΩ

CC

Pin 9 of ICM7228C and ICM7228D

Logical “1” Input Voltage, V

Logical “0” Input Voltage, V

All Inputs Except

Pin 9 of ICM7228C, ICM7228D

V

2.0

V

IH

IL

= 5V

DD

All Inputs Except

-

0.8

-

0.8

V

Pin 9 of ICM7228C, ICM7228D

V

= 5V

DD

SWITCHING SPECIFICATIONS V

= +5.0V ±10%, V = 0V, V = +0.4V, V = +2.4V

DD

SS

IL

IH

Write Pulsewidth (Low), t

WL

200

100

540

-65

150

160

-60

110

-60

-

250

1200

0

-

ns

Write Pulsewidth (High), t

850

0

WH

Mode Hold Time, t

MH

ICM7228A, ICM7228B

Mode Setup Time, t

250

0

250

0

MS

Data Setup Time, t

DS

Data Hold Time, t

DH

Digit Address Setup Time, t

ICM7228C, ICM7228D

250

0

250

0

AS

Digit Address Hold Time, t

AH

Electrical Speciﬁcations

V

= +5.0V ±10%, V = 0V, Unless Otherwise Speciﬁed

SS

DD

MILITARY TEMPERATURE RANGE, MJI, DEVICES

o

T

= 25 C

-55 C TO 125 C

A

PARAMETER

TEST CONDITIONS

MIN

TYP

-

MAX

6

MIN

TYP

-

MAX

UNITS

V

Supply Voltage Range, V

Operating

4

2

-

4

2

-

6

SUPPLY

Power Down Mode

-

V

Quiescent Supply Current, I

Shutdown, ICM7228A, IMC7228B

Shutdown, 7228C, 7228D

1

100

450

1

100

550

µA

Q

-

2.5

200

-

2.5

200

Operating Supply Current, I

Common Anode, ICM7228A/C

-

DD

Segments = ON; Outputs = OPEN

Common Anode, ICM7228A/C

Segments = OFF; Outputs = OPEN

-

100

250

175

450

-

100

250

175

450

550

450

µA

Common Cathode, ICM7228B/D

Segments = ON; Outputs = OPEN

Common Cathode, ICM7228B/D

Segments = OFF; Outputs = OPEN

9-21

ICM7228

Electrical Speciﬁcations

V

= +5.0V ±10%, V = 0V, Unless Otherwise Speciﬁed

DD

SS

MILITARY TEMPERATURE RANGE, MJI, DEVICES (Continued)

o

T

= 25 C

-55 C TO 125 C

A

PARAMETER

Digit Drive Current, I

TEST CONDITIONS

Common Anode, V = 5V

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

200

-

170

-

mA

DIG

DD

- 2.0V

V

= V

DD

OUT

Common Cathode, V

= 5V

50

-

1

-

100

-

35

-

1

-

mA

µA

mA

µA

DD

V

= V + 1.0V

SS

OUT

Digit Leakage Current, I

Shutdown Mode, V

OUT

Common Anode, ICM7228A/C

= 2.0V

100

-

DLK

Shutdown Mode, V = 5.0V

-

1

-

1

OUT

Common Cathode, 7228B/D

Peak Segment Drive Current, I

SEG

Common Anode, ICM7228A/C

20

10

-

25

12

1

20

10

-

25

12

1

V

= V + 1.0V, V

SS

= 5V

DD

OUT

Common Cathode, 7228B/D

= V - 2.0V, V = 5V

-

V

OUT

DD DD

Segment Leakage Current, I

Shutdown Mode, V

= V

DD

50

1

50

1

SLK

OUT

Common Anode, ICM7228A/C

Shutdown Mode, V = V

-

1

-

1

OUT

SS

Common Cathode, ICM7228B/D

Input Leakage Current, I

IL

All Inputs Except Pin 9

ICM7228C, ICM7228D V = V

IN

-

SS

All Inputs Except Pin 9

-

-1

-

-1

ICM7228C, ICM7228D V = 5.0V

IN

Display Scan Rate, f

MUX

Per Digit

-

2

390

10

-

2

390

10

-

Hz

µs

V

Inter-Digit Blanking Time, t

IDB

Logical “1” Input Voltage, V

Three Level Input: Pin 9

4.2

INH

ICM7228C, ICM7228D Hexadecimal

V

= 5V

DD

Floating Input, V

Three Level Input: Pin 9

ICM7228C, ICM7228D Code B

2.0

-

3.0

0.8

2.4

-

3.0

0.4

V

INF

V

= 5V

DD

Logical “0” Input Voltage, V

Three Level Input: Pin 9

INL

ICM7228C, ICM7228D Shutdown

V

= 5V

DD

Three Level Input Impedance, Z

IN

V

= 5V

50

-

50

-

kΩ

CC

Pin 9 of ICM7228C and ICM7228D

Logical “1” Input Voltage, V

Logical “0” Input Voltage, V

All Inputs Except

Pin 9 of ICM7228C, ICM7228D

V

2.0

V

IH

IL

= 5V

DD

All Inputs Except

-

0.8

-

0.8

V

Pin 9 of ICM7228C, ICM7228D

V

= 5V

DD

SWITCHING SPECIFICATIONS V

= +5.0V ±10%, V = 0V, V = +0.4V, V = +2.4V

DD

SS

IL

IH

Write Pulsewidth (Low), t

WL

200

100

540

-65

150

160

-60

110

-60

-

250

1200

0

115

840

-65

165

160

-60

100

-60

-

ns

Write Pulsewidth (High), t

850

0

WH

Mode Hold Time, t

MH

ICM7228A, ICM7228B

Mode Setup Time, t

250

0

250

0

MS

Data Setup Time, t

DS

Data Hold Time, t

DH

Digit Address Setup Time, t

ICM7228C, ICM7228D

250

0

250

0

AS

Digit Address Hold Time, t

AH

9-22

ICM7228

Timing Diagrams

MODE

t

MS

t

MH

WRITE

MODE

WRITE

t

DON’T CARE

t

WH

WRITE DATA

8 PULSES

WL

(D1)

CONTROL WORD

(D8)

CONTROL WORD

t

TYPE OF DECODER?ID6

DECODE/NO DECODE? ID5

SHUTDOWN?ID4

TYPE OF DECODER?ID6

DECODE/NO DECODE? ID5

SHUTDOWN? ID4

DH

t

DS

INPUT

DATA

VALID

DATA COMING ID7

FIGURE 1. ICM7228A/B WRITE CYCLE

FIGURE 2. ICM7228A/B SEQUENTIAL 8-DIGIT RAM UPDATE

DIGIT

ADDRESS

DAO-DAZ

VALID

t

AH

AS

t

WL

WRITE

t

WH

t

DH

t

DS

DATA

VALID DATA

FIGURE 3. ICM7228C/D WRITE CYCLE

10µs (TYP)

FREE RUNNING

320µs (TYP)

FREE RUNNING (PER DIGIT)

INTERDIGIT BLANKING

INTERNAL SIGNAL

D2

D5

INTERDIGIT BLANKING

D1

D7

D8

D6

D4

D3

TYPICAL DIGITS

OUTPUT PULSES

FIGURE 4. DISPLAY DIGITS MULTIPLEX (COMMON ANODE DISPLAY)

Typical Performance Curves

o

0

-55 C

o

25 C

o

100

200

300

400

500

125 C

o

-55 C

80

60

40

20

0

o

25 C

o

25 C

o

125 C

o

125 C

o

-55 C

5.0

4.0

V

3.0

-V

2.0

1.0

0

1.0

2.0

3.0

4.0

5.0

(V)

V

(V)

DD DIG

SEG

FIGURE 5. COMMON ANODE DIGIT DRIVER I

DIG

vs (V

DD

- V )

DIG

FIGURE 6. COMMON ANODE SEGMENT DRIVER I

vs V

SEG

9-23

ICM7228

Typical Performance Curves (Continued)

o

25 C

o

-55 C

0

10

20

30

40

50

o

125 C

300

o

-55 C

200

o

25 C

o

125 C

100

0

1.0

2.0

3.0

4.0

5.0

4.0

3.0

-V

2.0

1.0

0

V

(V)

V

(V)

DIG

DD SEG

FIGURE 7. COMMON CATHODE DIGIT DRIVER I

vs V

FIGURE 8. COMMON CATHODE SEGMENT DRIVER I

vs

SEG

DIG

(V

- V

)

SEG

DD

TABLE 1. ICM7228A PIN ASSIGNMENTS AND DESCRIPTIONS

PIN NO.

NAME

FUNCTION

DESCRIPTION

1

2

3

4

5

SEG c

SEG e

SEG b

DP

Output

LED Display Segments c, e, b and Decimal Point Drive Lines.

ID6,

Input

When “MODE” Low: Display Data Input, Bit 7.

(HEXA/CODE B)

When “MODE” High: Control Bit, Decoding Scheme Selection: High, Hexadecimal

Decoding; Low, Code B Decoding.

6

7

ID5, (DECODE)

Input

When “MODE” Low: Display Data Input, Bit 6.

When “MODE” High: Control Bit, Decode/No Decode Selection: High, No Decode; Low, Decode.

ID7,

When “MODE” Low: Display Data Input, Bit 8, Decimal Point Data.

When “MODE” High: Control Bit, Sequential Data Update Select: High, Data Coming; Low,

No Data Coming.

(DATA COMING)

8

9

WRITE

MODE

Input

Data Input Will Be Written to Control Register or Display RAM on Rising Edge of WRITE.

Selects Data to Be Loaded to Control Register or Display RAM: High, Loads Control

Register; Low, Loads Display RAM.

10

11

12

13

14

ID4,

(SHUTDOWN)

Input

When “MODE” Low: Display Data Input, Bit 5.

When “MODE” High: Control Bit, Low Power Mode Select: High, Normal Operation; Low,

Oscillator and Display Disabled.

ID1

ID0

ID2

ID3

When “MODE” Low: Display Data Input, Bit 2.

When “MODE” High and “ID7 (DATA COMING)” Low: Digit Address, Bit 2, Single Digit

Update Mode.

When “MODE” Low: Display Data Input, Bit 1.

When “MODE” High and “ID7 (DATA COMING)” Low: Digit Address, LSB, Single Digit

Update Mode.

When “MODE” Low: Display Data Input, Bit 3.

When “MODE” High and “ID7 (DATA COMING)” Low: Digit Address, MSB, Single Digit

Update Mode.

When “MODE” Low: Display Data Input, Bit 4.

When “MODE” High: RAM Bank Select (Decode Modes Only): High, RAM Bank A; Low,

RAM Bank B

9-24

ICM7228

TABLE 1. ICM7228A PIN ASSIGNMENTS AND DESCRIPTIONS (Continued)

PIN NO.

15

NAME

DIGIT 1

FUNCTION

DESCRIPTION

LED Display Digits 1, 2, 5 and 8 Drive Lines.

Output

16

DlGlT 2

DIGIT 5

DlGlT 8

17

18

19

V

Supply

Output

Device Positive Power Supply Rail.

DD

20

DIGIT 4

DlGlT 7

DlGlT 6

DIGlT 3

SEG f

LED Display Digits 4, 7, 6 and 3 Drive Lines.

21

22

23

24

Output

Supply

LED Display Segments f, d, g and a Drive Lines.

Device Ground or Negative Power Supply Rail.

25

SEG d

SEG g

SEG a

26

27

28

V

SS

TABLE 2. ICM7228B PIN ASSIGNMENTS AND DESCRIPTIONS

PIN NO.

NAME

FUNCTION

DESCRIPTION

LED Display Digits 4, 6, 3 and 1 Drive Lines.

1

2

3

4

5

DIGIT 4

DlGlT 6

DIGIT 3

DlGlT 1

Output

ID6,

Input

When “MODE” Low: Display Data Input, Bit 7.

(HEXA/CODE B)

When “MODE” High: Control Bit, Decoding Scheme Selection: High, Hexadecimal

Decoding; Low, Code B Decoding.

6

7

ID5, (DECODE)

Input

When “MODE” Low: Display Data Input, Bit 6.

When “MODE” High: Control Bit, Decode/No Decode Selection: High, No Decode; Low, Decode.

ID7,

When “MODE” Low: Display Data Input, Bit 8, Decimal Point Data.

When “MODE” High: Control Bit, Sequential Data Update Select: High, Data Coming; Low,

No Data Coming.

(DATA COMING)

8

9

WRITE

MODE

Input

Data Input Will Be Written to Control Register or Display RAM on Rising Edge of WRITE.

Selects Data to Be Loaded to Control Register or Display RAM: High, Loads Control Reg-

ister; Low, Loads Display RAM.

10

11

12

13

ID4,

(SHUTDOWN)

Input

When “MODE” Low: Display Data Input, Bit 5.

When “MODE” High: Control Bit, Low Power Mode Select: High, Normal Operation; Low,

Oscillator and Display Disabled.

ID1

ID0

ID2

When “MODE” Low: Display Data Input, Bit 2.

When “MODE” High and “ID7 (DATA COMING)” Low: Digit Address, Bit 2, Single Digit

Update Mode.

When “MODE” Low: Display Data Input, Bit 1.

When “MODE” High and “ID7 (DATA COMING)” Low: Digit Address, LSB, Single Digit

Update Mode.

When “MODE” Low: Display Data Input, Bit 3.

When “MODE” High and “ID7 (DATA COMING)” Low: Digit Address, MSB, Single Digit

Update Mode.

9-25

ICM7228

TABLE 2. ICM7228B PIN ASSIGNMENTS AND DESCRIPTIONS (Continued)

PIN NO.

NAME

FUNCTION

DESCRIPTION

14

ID3

Input

When “MODE” Low: Display Data Input, Bit 4.

When “MODE” High: RAM Bank Select (Decode Modes Only): High, RAM Bank A; Low,

RAM Bank B.

15

16

17

18

19

20

21

22

23

24

25

26

27

28

DP

Output

LED Display Decimal Point and Segments a, b, and d Drive Lines

SEG a

SEG b

SEG d

V

Supply

Output

Device Positive Power Supply Rail.

DD

SEG c

SEG e

SEG f

SEG g

LED Display Segments c, e, f and g Drive Lines.

DIGIT 8

DIGIT 2

DIGIT 5

DIGIT 7

Output

Supply

LED Display Digits 8, 2, 5 and 7 Drive Lines.

Device Ground or Negative Power Supply Rail.

V

SS

TABLE 3. ICM7228C PIN ASSIGNMENTS AND DESCRIPTIONS

PIN NO.

NAME

FUNCTION

DESCRIPTION

1

2

3

4

5

6

7

SEG c

SEG e

SEG b

DP

Output

LED Display Segments c, e, band Decimal Point Drive Lines.

DA0

Input

Digit Address Input, Bit 1 LSB.

DA1

Digit Address Input, Bit 2.

ID7,

Display Decimal Point Data Input, Negative True.

(INPUT DP)

8

9

WRITE

Input

Data Input Will Be Written to Display RAM on Rising Edge of WRITE.

HEXA/CODE

B/SHUTDOWN

Three Level Input. Display Function Control: High, Hexadecimal Decoding; Float, Code B

Decoding; Low, Oscillator, and Display Disabled.

10

11

12

13

14

15

16

17

18

19

DA2

Input

Digit Address Input, Bit 3, MSB.

Display Data Inputs.

ID1

ID0

ID2

ID3

DIGIT 1

DlGlT 2

DIGIT 5

DlGlT 8

Output

Supply

LED Display Digits 1, 2, 5 and 8 Drive Lines.

V

Device Positive Power Supply Rail.

DD

9-26

ICM7228

TABLE 3. ICM7228C PIN ASSIGNMENTS AND DESCRIPTIONS (Continued)

PIN NO.

20

NAME

DIGIT 4

FUNCTION

DESCRIPTION

LED Display Digits 4, 7, 6 and 3 Drive Lines.

Output

21

DlGlT 7

DlGlT 6

DIGlT 3

SEG f

22

23

24

Output

Supply

LED Display Segments f, d, g and a Drive Lines.

Device Ground or Negative Power Supply Rail.

25

SEG d

SEG g

SEG a

26

27

28

V

SS

TABLE 4. ICM7228D PIN ASSIGNMENTS AND DESCRIPTIONS

PIN NO.

NAME

FUNCTION

DESCRIPTION

LED Display Digits 4, 6, 3 and 1 Drive Lines.

1

2

3

4

5

6

7

8

9

DIGIT 4

DlGlT 6

DIGIT 3

DlGlT 1

DA0

Output

Input

Digit Address Input, Bit 1 LSB.

DA1

Digit Address Input, Bit 2.

ID7, (INPUT DP)

WRITE

Display Decimal Point Data Input, Negative True.

Data Input Will Be Written to Display RAM on Rising Edge of WRITE.

HEXA/CODE

B/SHUTDOWN

Three Level Input. Display Function Control: High, Hexadecimal Decoding; Float, Code B

Decoding; Low, Oscillator and Display Disabled.

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

DA2

ID1

Input

Digit Address Input, Bit 3, MSB.

Display Data Inputs.

ID0

ID2

ID3

DP

Output

LED Display Decimal Point and Segments a, b, and d Drive Lines.

SEG a

SEG b

SEG d

V

Supply

Output

Device Positive Power Supply Rail.

DD

SEG c

LED Display Segments c, e, f and g Drive Lines.

SEG e

SEG f

SEG g

DIGIT 8

DIGIT 2

DIGIT 5

DIGIT 7

Output

Supply

LED Display Digits 8, 2, 5 and 7 Drive Lines.

V

Device Ground or Negative Power Supply Rail.

SS

9-27

ICM7228

logic level (during Control Register update) selects which bank

of the internal RAM to be written to and/or displayed.

Detailed Description

System Interfacing and Data Entry Modes, ICM7228A

and ICM7228B

Control Register Update without RAM Update

The Control Register can be updated without changing the

display data by a single pulse on the WRITE input, with MODE

high and DATA COMING low. If the display is being decoded

(Hex/Code B), then the value of lD3 determines which RAM

bank will be selected and displayed for all eight digits.

The ICM7228A/B devices are compatible with the architec-

tures of most microprocessor systems. Their fast switching

characteristics makes it possible to access them as a memory

mapped I/O device with no wait state necessary in most

microcontroller systems. All the ICM7228A/B inputs, including

MODE, feature a 250ns minimum setup and 0ns hold time

with a 200ns minimum WRITE pulse. Input logic levels are

TTL and CMOS compatible. Figure 9 shows a generic method

of driving the ICM7228A/B from a microprocessor bus. To the

microprocessor, each device appears to be 2 separate I/O

locations; the Control Register and the Display RAM. Selec-

tion between the two is accomplished by the MODE input

driven by address line A0. Input data is placed on the lD0 - lD7

lines. The WRITE input acts as both a device select and write

cycle timing pulse. See Figure 1 and Switching Speciﬁcations

Table for write cycle timing parameters.

Sequential 8-Digit Update

The logic state of DATA COMING (lD7) is also latched during a

Control Register update. If the latched value of DATA COMING

(lD7) is high, the display becomes blanked and a sequential

8-digit update is initiated. Display data can now be written into

RAM with 8 successive WRITE pulses, starting with digit 1 and

ending with digit 8 (See Figure 2). After all 8 RAM locations

have been written to, the display turns on again and the new

data is displayed. Additional write pulses are ignored until a new

Control Register update is performed. All 8 digits are displayed

in the format (Hex/Code B or No Decode) speciﬁed by the con-

trol word that preceded the 8 digit update. If a decoding scheme

(Hex/Code B) is to be used, the value of lD3 during the control

word update determines which RAM bank will be written to.

The ICM7228A/B have three data entry modes: Control Reg-

ister update without RAM update, sequential 8-digit update

and single digit update. In all three modes a control word is

ﬁrst written by pulsing the WRITE input while the MODE input

is high, thereby latching data into the Control Register. The

logic level of individual bits in the Control Register select Shut-

down, Decode/No Decode, Hex/Code B, RAM bank A/B and

Display RAM digit address as shown in Tables 1 and 2.

Single Digit Update

In this mode each digit data in the display RAM can be updated

individually without changing the other display data. First, with

MODE input high, a control word is written to the Control Regis-

ter carrying the following information; DATA COMING (lD7) low,

the desired display format data on lD4 - lD6, the RAM bank

selected by lD3 (if decoding is selected) and the address of the

digit to be updated on data lines lD0 - lD2 (See Table 5). A sec-

ond write to the ICM7228A/B, this time with MODE input low,

transfers the data at the lD0 - lD7 inputs into the selected digit’s

RAM location. In single digit update mode, each individual

digit’s data can be speciﬁed independently for being displayed

in Decoded or No-Decode mode. For those digits which decod-

ing scheme (Hex/Code B) is selected, only one can be effective

at a time. Whenever a control word is written, the speciﬁed

decoding scheme will be applied to all those digits which

selected to be displayed in Decoded mode.

The ICM7228A/B Display RAM is divided into 2 banks, called

bank A and B. When using the Hexadecimal or code B display

modes, these RAM banks can be selected separately. This

allows two separate sets of display data to be stored and dis-

played alternately. Notice that the RAM bank selection is not

possible in No-Decode mode, this is because the display data

in the No-Decode mode has 8 bits, but in Decoded schemes

(Hex/Code B) is only 4 bits (lD0 - lD3 data). It should also be

mentioned that the decimal point is independent of selected

bank, a turned on decimal point will remain on for either bank.

Selection of the RAM banks is controlled by lD3 input. The lD3

DATA BUS D0-D7

ID0

D0 - D7

ID7

INTERSIL

I/O OR

ICM7228A/B

MEMORY

LED DISPLAY

WRITE PULSE

DECODER

ENABLE

DEVICE SELECT

AND

SEGMENTS

WRITE PULSE

DRIVE

WRITE

MODE

ADDRESS

DECODER

A0

A1-A15

DIGITS

DRIVE

ADDRESS BUS A0 - A15

FIGURE 9. ICM7228A/B MICROPROCESSOR SYSTEM INTERFACING

9-28

ICM7228

accordingly called HEXA/CODE B/SHUTDOWN. See Tables 3

and 4 for input and output deﬁnitions of the ICM7228C/D

devices.

TABLE 5. DIGITS ADDRESS, ICM7228A/B

INPUT DATA LINES

Display Formats

1D2

0

lD2

0

lD0

0

SELECTED DIGIT

DlGlT 1

The ICM7228A and ICM7228B have three possible display

formats; Hexadecimal, Code B and No Decode. Table 6

shows the character sets for the decode modes and their

corresponding input code.

0

1

DlGlT 2

0

1

0

DIGlT 3

The display formats of the ICM7228A/B are selected by

writing data to bits ID4, ID5 and ID6 of the Control Register

(See Table 1 and 2 for input Deﬁnitions). Hexadecimal and

Code B data is entered via ID0-lD3 and ID7 controls the

decimal point.

0

1

DlGlT 4

1

0

DIGIT 5

1

0

1

DlGlT 6

TABLE 6. DISPLAY CHARACTER SETS

1

0

DlGlT 7

INPUT DATA CODE

DISPLAY CHARACTERS

1

DlGlT 8

ID3

0

ID2

0

ID1

0

ID0

0

HEXADECIMAL

CODE B

System Interfacing, ICM7228C and ICM7228D

0

1

2

3

4

5

6

7

8

9

A

b

C

d

E

F

0

The ICM7228C/D devices are directly compatible with the

architecture of most microprocessor systems. Their fast

switching characteristics make it possible to access them as a

memory mapped I/O device with no wait state necessary in

most microcontroller systems. All the ICM7228C/D inputs,

excluding HEXA/CODE B/SHUTDOWN, feature a 250ns min-

imum setup and 0ns hold time with a 200ns minimum WRITE

pulse. Input logic levels are TTL and CMOS compatible. Fig-

ure 10 shows a generic method of driving the ICM7228C/D

from a microprocessor bus. To the microprocessor, the 8

bytes of the Display RAM appear to be 8 separate I/O loca-

tions. Loading the ICM7228C/D is quite similar to a standard

memory write cycle. The address of the digit to be updated is

placed on lines DA0 - DA2, the data to be written is placed on

lines ID0 - lD3 and ID7, then a low pulse on WRITE input will

transfer the data in. See Figure 3 and Switching Characteris-

tics Table for write cycle timing parameters.

0

1

0

1

0

2

0

1

3

0

1

0

4

0

1

0

1

5

0

1

0

6

0

1

7

1

0

8

1

0

1

9

1

0

1

0

-

1

0

1

E

1

0

H

1

0

1

L

P

The ICM7228C/D devices do not have any control register, and

also they do not provide the No Decode display format. Hexa-

decimal or Code B character selection and shutdown mode are

directly controlled through the three level input at Pin 9, which is

1

0

1

(Blank)

DATA BUS D0 - D7

5

ID0 - ID3

AND ID7

INTERSIL

ICM7228C/D

I/O OR

MEMORY

WRITE PULSE

LED DISPLAY

DECODER

ENABLE

DEVICE SELECT

AND

WRITE PULSE

SEGMENTS

DRIVE

WRITE

ADDRESS

DECODER

DIGITS

DRIVE

DA0 - DA2

A0 - A2

A3 - A15

ADDRESS BUS A0 - A15

FIGURE 10. ICM7228C/D MICROPROCESSOR SYSTEM INTERFACING

9-29

ICM7228

minimum of 200mA drive capability. The N-Channel segment

a

driver’s output impedance of 50Ω limits the segment current to

approximately 25mA peak current per segment. Both the seg-

ment and digit outputs can directly drive the display, current

limiting resistors are not required.

f

b

g

e

c

d

DP

Individual segment current is not signiﬁcantly affected by

whether other segments are on or off. This is because the seg-

ment driver output impedance is much higher than that of the

digit driver. This feature is important in bar graph applications

where each bar graph element should have the same bright-

ness, independent of the number of elements being turned on.

FIGURE 11. DIGITS SEGMENT ASSIGNMENTS

The No Decode mode of the ICM7228A and ICM7228B

allows the direct segment-by-segment control of all 64 seg-

ments driven by the device. In the No Decode mode, the

input data directly control the outputs as shown in Table 7.

Common Cathode Display Drivers, ICM7228B and

ICM7228D

TABLE 7. NO DECODE SEGMENT LOCATIONS

The common cathode digit and segment driver output

schematics are shown in Figure 13. The N-channel digit driv-

ers have an output impedance of approximately 15Ω. Each

digit has a minimum of 50mA drive capability. The segment

drivers have an output impedance of approximately 100Ω

with typically 10mA peak current drive for each segment.

DATA

INPUT

ID7

ID6 ID5 ID4 ID3 ID2 ID1 ID0

Controlled

Segment

Decimal

Point

a

b

c

e

g

f

d

The common cathode display driver output currents are only

/ of the common anode display driver currents. Therefore,

4

1

An input high level turns on the respective segment, except

for the decimal point, which is turned on by an input low level

on ID7.

the ICM7228A and ICM7228C common anode display

drivers are recommended for those applications where high

display brightness is desired. The ICM7228B and ICM7228D

common cathode display drivers are suitable for driving

bubble-lensed monolithic 7 segment displays. They can also

drive individual LED displays up to 0.3 inches in height when

high brightness is not required.

The No Decode mode can be used in different applications

such as bar graph or status panel driving where each

segment controls an individual LED.

The ICM7228C and ICM7228D have only the Hexadecimal

and Code

B

character sets. The HEXA/CODE

Display Multiplexing

B/SHUTDOWN input, pin 9, requires a three level input. Pin

9 selects the Hexadecimal format when pulled high, the

Code B format when ﬂoating or driven to mid-supply, and the

shutdown mode when pulled low (See Tables 3 and 4).

Table 6 also applies to the ICM7228C/D devices.

Each digit of the ICM7228 is on for approximately 320µs,

with a multiplexing frequency of approximately 390Hz. The

ICM7228 display drivers provide interdigit blanking. This

ensures that the segment information of the previous digit is

gone and the information of the next digit is stable before the

next digit is driven on. This is necessary to eliminate display

ghosting (a faint display of data from previous digit superim-

posed on the next digit). The interdigit blanking time is 10µs

typical with a guaranteed 2µs minimum. The ICM7228 turns

off both the digit drivers and the segment drivers during the

interdigit blanking period. The digit multiplexing sequence is:

D2, D5, D1, D7, D8, D6, D4 and D3. A typical digit’s drive

pulses are shown on Figure 4.

Shutdown and Display Banking

When shutdown, the ICM7228 enters a low power standby

mode typically consuming only 1µA of supply current for the

ICM7228A/B and 2.5µA for the ICM7228C/D. In this mode

the ICM7228 turns off the multiplex scan oscillator as well as

the digit and segment drivers. However, input data can still

be entered when in the shutdown mode. Data is retained in

memory even with the supply voltage as low as 2V.

The ICM7228A/B is shutdown by writing a control word with

Shutdown (lD4) low. The ICM7228C/D is put into shutdown

mode by driving pin 9, HEXA/CODE B/SHUTDOWN, low.

Due to the display multiplexing, the driving duty cycle for

1

each digit is 12% (100 x / ) This means the average current

8

1

for each segment is / of its peak current. This must be con-

8

sidered while designing and selecting the displays.

The ICM7228 operating current with the display blanked is

within 100µA - 200µA for all versions. All versions of the

ICM7228 can be blanked by writing Hex FF to all digits and

selecting Code B format. The ICM7228A and ICM7228B can

also be blanked by selecting No Decode mode and writing

Hex 80 to all digits (See Tables 6 and 7).

Driving Larger Displays

If very high display brightness is desired, the ICM7228

display driver outputs can be externally buffered. Figures 14

thru 16 show how to drive either common anode or common

cathode displays using the ICM7228 and external driver

circuit for higher current displays.

Common Anode Display Drivers, ICM7228A and

ICM7228C

Another method of increasing display currents is to connect

two digit outputs together and load the same data into both

digits. This drives the display with the same peak current, but

the average current doubles because each digit of the

The common anode digit and segment driver output schemat-

ics are shown in Figure 12. The common anode digit driver

output impedance is approximately 4Ω. This provides a nearly

constant voltage to the display digits. Each digit has a

1

display is on for twice as long, i.e., / duty cycle versus / .

4

8

9-30

ICM7228

V

DD

SEGMENT

DIGIT

DATA

STROBE

≈200mA

P

≈200mA

INTERDIGIT

BLANKING

INTERDIGIT

BLANKING

COMMON

100Ω

CATHODE

SEGMENT

OUTPUT

≈^N2kΩ

N

COMMON

ANODE

DIGIT

OUTPUT

N

≈2kΩ

V

SS

SHUTDOWN

≈^N2kΩ

V

SS

N

≈2kΩ

V

SS

SHUTDOWN

NOTE: When SHUTDOWN goes low INTERDIGIT BLANKING also

stays low.

V

SS

NOTE: When SHUTDOWN goes low INTERDIGIT BLANKING also

stays low.

FIGURE 13B. SEGMENT DRIVER

FIGURE 13. COMMON CATHODE DISPLAY DRIVERS

FIGURE 12A. DIGIT DRIVER

V

DD

UP TO

4A

V

DD

DIGIT

P

OUTPUT

≈2kΩ

SEGMENT

DATA

COMMON

ANODE

SEGMENT

OUTPUT

ICM7228A/B

INTERDIGIT

BLANKING

V

DD

V

N

DD

≈75Ω

SEGMENT

OUTPUT

10K

SHUTDOWN

V

SS

FIGURE 12B. SEGMENT DRIVER

FIGURE 12. COMMON ANODE DISPLAY DRIVERS

V

SS

FIGURE 14. DRIVING HIGH CURRENT DISPLAY, COMMON

ANODE ICM7228A/C TO COMMON ANODE DISPLAY

V

DD

P

V

DD

≈2kΩ

DIGIT

STROBE

COMMON

CATHODE

DIGIT

INTERDIGIT

BLANKING

SEGMENT

OUTPUT

N

100Ω

OUTPUT

≈15Ω

2N2219

SHUTDOWN

ICM7228C/D

V

SS

14Ω (100mA

)

PEAK

DD

DIGIT

OUTPUT

FIGURE 13A. DIGIT DRIVER

14mA

2N6034

N

≈15Ω

1.4A

PEAK

V

SS

FIGURE 15. DRIVING HIGH CURRENT DISPLAY, COMMON

CATHODE ICM7228B/D TO COMMON CATHODE

DISPLAY

9-31

ICM7228

V

DD

1.4A

74C126 THREE-STATE BUFFER

PIN 9

HIGH = HEX

PEAK

1K

LOW = SHUTDOWN

2N6034

HIGH = HEX OR SHUTDOWN

LOW = CODE B

CD4016

CD4066

HIGH = HEX

SEGMENT

OUTPUT

PIN 9

100Ω

LOW = SHUTDOWN

CONTROL

ICM7228C/D

HIGH = HEX OR SHUTDOWN

LOW = CODE B

V

DD

1K

300Ω

25Ω

1N4148

DIGIT

OUTPUT

CD4069

HIGH = CODE B

LOW = HEX

(100mA

2N2219

)

PEAK

N

≈15Ω

1N4148

CD4069

HIGH = SHUTDOWN

LOW = CODE B

PIN 9

V

SS

V

HIGH = SHUTDOWN

LOW = HEX

SS

FIGURE 16. DRIVING HIGH CURRENT DISPLAY, COMMON

OPEN DRAIN OR OPEN

COLLECTOR OUTPUT

CATHODE ICM7228B/D TO COMMON CATHODE

DISPLAY

HIGH = SHUTDOWN

LOW = CODE B

PIN 9

FIGURE 17. ICM7228C/D PIN 9 DRIVE CIRCUITS

Three Level Input, ICM7228C and ICM7228D

As mentioned before, pin 9 is a three level input and controls

three functions: Hexadecimal display decoding, Code B dis-

play decoding and shutdown mode. In many applications, pin

9 will be left open or permanently wired to one state. When

pin 9 can not be permanently left in one state, the circuits illus-

trated in Figure 17 can be used to drive this three level input.

Power Supply Bypassing

Connect a minimum of 47µF in parallel with 0.1µF capacitors

between V and V of ICM7228. These capacitors

should be placed in close proximity to the device to reduce

the power supply ripple caused by the multiplexed LED dis-

play drive current pulses.

DD

SS

Test Circuits

1

2

3

28

27

26

25

24

23

22

21

20

19

18

17

16

15

4

ID6 (HEXA/CODE B)

5

ID5 (DECODE)

6

ID7 (DATA COMING)

7

WRITE

ICM7228A

8

MODE

9

ID4 (SHUTDOWN)

10

ID1

11

ID0

12

ID2

13

ID3

14

V

+

DD

f

d

g

a

c

V

DD

47µF

5V

-

+0.1µF

V

SS

V

SS

D8

D7

D6

D5

D4

D3

D2

D1

e

b

COMMON ANODE DISPLAY

DP

FIGURE 18. FUNCTIONAL TEST CIRCUIT #1

9-32

ICM7228

Test Circuits (Continued)

1

2

28

27

26

25

24

23

22

3

4

DIGIT ADDRESS 0

DIGIT ADDRESS 1

ID7 (D.P.)

5

6

7

WRITE

ICM7228D

8

21

20

19

18

17

16

15

HEXA/CODE B/SHUTDOWN

9

DIGIT ADDRESS 2

10

11

12

13

14

ID1

ID0

ID2

ID3

V

+

DD

V

DD

47µF

+0.1µF

5V

-

V

SS

g

f

e

D8

D7

D6

D5

D4

D3

D2

D1

c

d

b

a

COMMON ANODE DISPLAY

DP

FIGURE 19. FUNCTIONAL TEST CIRCUIT #2

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or speciﬁcations at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate

and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which

may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

9-33


型号：	ICM7228AIBI
厂家：	Intersil
描述：	8-Digit, Microprocessor- Compatible, LED Display Decoder Driver 8位，微处理器兼容， LED显示译码器驱动器驱动器接口集成电路微处理器光电二极管
文件：	总17页 (文件大小：102K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ICM7228AIBI [INTERSIL]

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