IS-2981EH [INTERSIL]

Radiation Hardened 8-Channel Source Driver; 抗辐射8通道源驱动器


型号：	IS-2981EH
厂家：	Intersil
描述：	Radiation Hardened 8-Channel Source Driver 抗辐射8通道源驱动器驱动器
文件：	总4页 (文件大小：170K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Radiation Hardened 8-Channel Source Driver

IS-2981RH, IS-2981EH

Features

• Electrically screened to SMD # 5962-00520

The Star*Power Radiation Hardened

IS-2981RH, IS-2981EH are monolithic

devices designed for use in high-side

switching applications that benefit

from separate grounds for the logic

• QML qualified per MIL-PRF-38535 requirements

• Radiation environment

- Single event latch-up immune DI process

- High dose rate . . . . . . . . . . . . . . . . . . . . . . . . . . 100krad(Si)

and loads. The devices have a 5V to 80V operating supply

voltage range and is capable of sourcing -200mA continuously

from each output. The outputs are controlled by active-high

inputs and may be paralleled to increase the drive current. The

output clamp diodes prevent device damage, when switching

inductive loads.

- Low dose rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50krad(Si)

• Input voltage range . . . . . . . . . . . . . . . 0.0V to V (20V max)

• Supply voltage range . . . . . . . . . . . . . . . . . . . . . . . . . 5V to 80V

• Turn-on delay time . . . . . . . . . . . . . . . . . . . . . . . . . . . 2µs (max)

• Turn-off delay time. . . . . . . . . . . . . . . . . . . . . . . . . . 11µs (max)

Constructed with the Intersil bonded wafer, dielectrically

isolated HVTDLM process, these single event latch-up immune

devices have been specifically designed to provide highly

reliable performance in harsh radiation environments. They

are fully guaranteed for 100krad(Si) high dose rate and

50krad(Si) low dose rate total dose performance through

wafer-by-wafer radiation testing, and are production tested

over the full military temperature range.

• Output clamp diode, V . . . . . . . . . . . . . . . . . . . . .-1.75V (max)

Applications

• Drivers for various loads

- Relays, solenoids and motors

• Reliable replacement of discrete solutions

Specifications for Rad Hard QML devices are controlled by the

Defense Logistics Agency Land and Maritime (DLA). The SMD

numbers listed below must be used when ordering.

• Interfacing between low-level logic and high-current loads

Detailed Electrical Specifications for these devices are

contained in SMD 5962-00520. A “hot-link” is provided on our

homepage for downloading

Pin Configuration

IS1-2981RH-Q, IS1-2981EH-Q

(CDIP2-T18)

TOP VIEW

IN 1

IN 2

IN 3

IN 4

IN 5

IN 6

IN 7

IN 8

OUT 1

OUT 2

16 OUT 3

15 OUT 4

14 OUT 5

13 OUT 6

OUT 7

OUT 8

GND

June 24, 2013

FN4869.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

IS-2981RH, IS-2981EH

Ordering Information

ORDERING

NUMBER

(Note 3)

INTERNAL

MKT.NUMBER

(Notes 1, 2)

PART

MARKING

TEMP. RANGE

PACKAGE

(RoHS Compliant)

PKG.

DWG. #

( C)

5962R0052001VVC

5962R0052002VVC

5962R0052001QVC

5962R0052001V9A

5962R0052002V9A

IS1-2981RH/PROTO

NOTE:

IS1-2981RH-Q

Q 5962R00 52001VVC

Q 5962R00 52002VVC

Q 5962R00 52001QVC

-55 to +125

18 Ld SBDIP

Die

D18.3

IS1-2981EH-Q

IS1-2981RH-8

IS0-2981RH-Q

IS0-2981EH-Q

IS1-2981RH/PROTO

Die

D18.3

IS1-2981RH/PROTO

18 Ld SBDIP

1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both

SnPb and Pb-free soldering operations.

2. For Moisture Sensitivity Level (MSL), please see device information page for IS-2981RH, IS-2981EH. For more information on MSL, please see tech

brief TB363.

3. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed in the

“Ordering Information” table on page 2 must be used when ordering.

FN4869.1

June 24, 2013

IS-2981RH, IS-2981EH

Die Characteristics

DIE DIMENSIONS:

Substrate

2667µm x 5131µm (105 mils x 202 mils)

HVTDLM, Bonded Wafer, Dielectric Isolation

Thickness: 483µm ±25.4µm (19 mils ±1 mil)

Backside Finish

INTERFACE MATERIALS

Glassivation

Silicon

ASSEMBLY RELATED INFORMATION

Type: Nitride (Si N ) over Silox (SiO )

Nitride Thickness: 4.0kÅ ± 1.0kÅ

Silox Thickness: 12.0kÅ ± 4.0kÅ

Substrate Potential

Must be tied to GND.

ADDITIONAL INFORMATION

Worst Case Current Density

Metallization

Top Metal 2: Ti/AlCu

Thickness: 1.6µm ± 0.02µm

Metal 1: Ti/AlCu

<1.0 x 10 A/cm

Transistor Count

Thickness: 0.8µm ± 0.01µm

Metallization Mask Layout

IS-2981RH, IS-2981EH

10A

NOTES:

4. Pad numbers correspond to package pin functions.

5. Bond to all four pad 9 locations for V current sharing purposes.

6. Bond to both pad 10 locations for GND current sharing purposes.

7. Pad 10A is not used in die applications.

8. Die backside must be connected to GND.

FN4869.1

June 24, 2013

IS-2981RH, IS-2981EH

Ceramic Dual-In-Line Metal Seal Packages (SBDIP)

c1 LEAD FINISH

D18.3 MIL-STD-1835 CDIP2-T18 (D-6, CONFIGURATION C)

18 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE

-A-

-D-

INCHES

MIN

MILLIMETERS

BASE

METAL

(c)

SYMBOL

MAX

0.200

0.026

0.023

0.065

0.045

0.018

0.015

0.960

0.310

MIN

MAX

5.08

0.66

0.58

1.65

1.14

0.46

0.38

24.38

7.87

NOTES

(b)

0.014

0.045

0.023

0.008

0.36

1.14

0.58

0.20

-B-

SECTION A-A

bbb

A - B

BASE

PLANE

-C-

SEATING

PLANE

A A

0.220

5.59

eA/2

aaa M C A - B S D S

0.100 BSC

2.54 BSC

eA/2

0.300 BSC

0.150 BSC

7.62 BSC

3.81 BSC

ccc

C A - B S D S

NOTES:

0.125

0.200

3.18

5.08

1. Index area: A notch or a pin one identification mark shall be locat-

ed adjacent to pin one and shall be located within the shaded

area shown. The manufacturer’s identification shall not be used

as a pin one identification mark.

0.015

0.005

0.070

0.38

0.13

1.78

2. The maximum limits of lead dimensions b and c or M shall be

measured at the centroid of the finished lead surfaces, when

solder dip or tin plate lead finish is applied.

105

aaa

bbb

ccc

0.015

0.030

0.010

0.0015

0.38

0.76

0.25

0.038

3. Dimensions b1 and c1 apply to lead base metal only. Dimension

M applies to lead plating and finish thickness.

4. Corner leads (1, N, N/2, and N/2+1) may be configured with a

partial lead paddle. For this configuration dimension b3 replaces

dimension b2.

5. Dimension Q shall be measured from the seating plane to the

base plane.

Rev. 0 5/18/94

6. Measure dimension S1 at all four corners.

7. Measure dimension S2 from the top of the ceramic body to the

nearest metallization or lead.

8. N is the maximum number of terminal positions.

9. Braze fillets shall be concave.

10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.

11. Controlling dimension: INCH.

For additional products, see www.intersil.com/product_tree

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time

without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be

accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN4869.1

June 24, 2013

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