ISL1539AIRZ-T13 [INTERSIL]
Dual Port VDSL2 Line Driver;
| 型号： | ISL1539AIRZ-T13 |
| 厂家： | 
Intersil |
| 描述： | Dual Port VDSL2 Line Driver |
| 文件： | 总23页 (文件大小：1654K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual Port VDSL2 Line Driver
ISL1539A
Features
• 360mA Output Drive Capability
The ISL1539A provides 4 internal wideband op amps
intended to be used as two pairs of differential line
drivers. The ISL1539A’s high bandwidth, 240MHz, and
• 41.8V Differential Output Drive into 100Ω
P-P
• -89dBc THD @ 1MHz 2V
P-P
ultra low distortion, -89dBc @ 1MHz, 2V , support the
P-P
• -65dBc MTPR (VDSL 8b Profile)
demanding MTPR requirements of emerging VDSL2 line
driver designs. Less demanding requirements can be met
at very low quiescent powers using the supply current
adjustment features.
• High Slew Rate of 3000V/µs Differential
• Bandwidth (240MHz @ A
V-DIFF
• Supply Current Control Pins
• Port Separation
- 78dB @ 500kHz
- 70dB @ 1MHz
- 60dB @ 4MHz
= 10)
Each of the 4 internal op amps is a wideband current
feedback amplifier offering very high slew rate intrinsic to
that design using low quiescent current levels. Each of
the two pair of amplifiers (ports) can also be power
optimized to the application using two external quiescent
control logic pins. Full power is nominally 27.2mA/port
with options of medium power cutback to 23mA/port, a
low power condition at 13.5mA/port, and an off state at
<0.5mA/port. Added quiescent power flexibility is
• Pb-Free (RoHS Compliant)
Applications*(see page 21)
• 8MHz and 17MHz VDSL2 Profiles
• ADSL2+
provided through an external I
pin. Grounding the pin
ADJ
gives the nominal currents listed above while inserting a
resistor from this pin to ground can be used to scale each
of the settings downward.
Related Literature (see Device Info page)
• AN1325 “Choosing and Using Bypass Capacitors”
High power push/pull line driver applications as
illustrated in the example below are best supported using
a low headroom, high output current device. On ±12V
supplies, the ISL1539A offers a 1.1V headroom with
>360mA peak output current. Driving differentially this
• TB426 “Characterization of the Output Protection
Circuitry of the EL1528 DSL Driver for Lightning
Surges”
TABLE 1. ALTERNATE SOLUTIONS
gives >41.8V
swing to as low as 58Ω differential load.
P-P
High SFDR operation is also supported for supplies as low
as ±7.5V. Intended to be used as differential pairs, this
two port device includes special circuitry to minimize
common mode loop peaking while also reducing the
common mode output noise spectrum. That circuitry
links the two sides of each port, precluding their
application as individual amplifiers.
NOMINAL ±V
(V)
BANDWIDTH
(MHz)
CC
PART #
ISL1557
ISL1534
ISL1536
APPLICATIONS
VDSL
±6
200
40
±12
±12
ADSL2+
50
ADSL2+
Typical Application
4MHz Harmonic Distortion
+12V
V
= ±12V
S
+
AV = +10
¼
Ro
Rb
ISL1539A
R
R
= 3.2kΩ
F
L
-
= 100Ω DIFF
Rf
1:n
Ω
3.2k
Ω
VI
VO
Rg711
LOAD
SOURCE
3rd HD
THD
Rf
2nd HD
3.2kΩ
-
¼
ISL1539A
+
Ro
AV-DIFF = VO/VI = 10V/V
Rb
-12V
TYPICAL DIFFERENTIAL I/O LINE DRIVER
(1 OF 2 PORTS)
September 23, 2009
FN6916.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2009. All Rights Reserved.
1
All other trademarks mentioned are the property of their respective owners.
ISL1539A
Pin Configurations
ISL1539A
(24 LD HTSSOP)
TOP VIEW
ISL1539A
(24 LD QFN)
TOP VIEW
VS- 1
C0AB 2
C1AB 3
VINA+ 4
VINB+ 5
GND 6
24 VS+
+
-
23 VOUTA
22 VINA-
21 VINB-
20 VOUTB
19 NC
VINA+ 1
VINB+ 2
GND 3
19 VINA-
+
-
18 VINB-
-
+
17 VOUTB
16 NC/SHIELD
15 VOUTC
14 VINC-
-
+
IADJ 4
IADJ 7
18 NC
+
-
NC 5
+
-
VINC+ 8
VIND+ 9
C1CD 10
C0CD 11
VS- 12
17 VOUTC
16 VINC-
15 VIND-
14 VOUTD
13 VS+
VINC+ 6
VIND+ 7
-
+
13 VIND-
-
+
VS- 1
C0AB 2
C1AB 3
VINA+ 4
VINB+ 5
GND 6
24 VS+
23 VOUTA
22 VINA-
21 VINB-
20 VOUTB
19 NC
VINA+ 1
VINB+ 2
GND 3
19 VINA-
18 VINB-
17 VOUTB
16 NC/SHIELD
15 VOUTC
14 VINC-
THERMAL
PAD
THERMAL
PAD
IADJ 4
IADJ 7
18 NC
NC 5
VINC+ 8
VIND+ 9
C1CD 10
C0CD 11
VS- 12
17 VOUTC
16 VINC-
15 VIND-
14 VOUTD
13 VS+
VINC+ 6
VIND+ 7
13 VIND-
THERMAL PAD CONNECTS TO GND OR -V
THERMAL PAD CONNECTS TO GND OR -V
S
S
Pin Descriptions
ISL1539AIR
ISL1539AIV
(24 Ld QFN) (24 Ld HTSSOP)
PIN NAME
VINA+
VINB+
GND
FUNCTION
CIRCUIT
1
2
3
4
4
5
6
7
Amplifier A non-inverting input (Refer to Circuit 1)
Amplifier B non-inverting input (Refer to Circuit 1)
Ground connection
IADJ
Supply current control pin for
both DSL Port #1 and #2
(Refer to Figure 46)
5
18, 19
8
NC
Not connected
6
VINC+
VIND+
C1CD
C0CD
VS-
Amplifier C non-inverting input (Refer to Circuit 1)
Amplifier D non-inverting input (Refer to Circuit 1)
DSL Port #2 current control pin (Refer to Figure 46)
DSL Port #2 current control pin (Refer to Figure 46)
Negative supply
7
8
9
10
9
11
10, 22
11, 21
12
1, 12
13, 24
14
VS+
Positive supply
VOUTD
Amplifier D output
(Refer to Circuit 2)
FN6916.0
September 23, 2009
2
ISL1539A
Pin Descriptions(Continued)
ISL1539AIR
ISL1539AIV
(24 Ld QFN) (24 Ld HTSSOP)
PIN NAME
VIND-
FUNCTION
CIRCUIT
(Refer to Circuit 3)
(Refer to Circuit 3)
(Refer to Circuit 2)
13
14
15
16
17
18
19
20
23
24
-
15
16
17
18, 19
20
21
22
23
2
Amplifier D Inverting Input
Amplifier C Inverting Input
Amplifier C output
VINC-
VOUTC
NC/SHIELD
VOUTB
Not Connected
Amplifier B output
(Refer to Circuit 2)
(Refer to Circuit 3)
(Refer to Circuit 3)
(Refer to Circuit 2)
VINB-
Amplifier B Inverting Input
Amplifier A Inverting Input
Amplifier A output
VINA-
VOUTA
C0AB
DSL Port #1 current control pin (Refer to Figure 46)
DSL Port #1 current control pin (Refer to Figure 46)
3
C1AB
-
THERMAL PAD
Connects to GND or -V
S
V +
V +
S
S
V +
S
V +
S
V -
S
V -
V -
S
S
CIRCUIT 1
CIRCUIT 2
V -
S
CIRCUIT 3
Ordering Information
OPERATING AMBIENT
TEMP RANGE
(°C)
PART
NUMBER
PART
MARKING
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL1539AIRZ (Note 2)
1539A IRZ
-40 to +85
-40 to +85
24 Ld QFN
24 Ld QFN
L24.4x5B
ISL1539AIRZ-T13 (Notes 1, 2) 1539A IRZ
L24.4x5B
MDP0048
MDP0048
COMING SOON
ISL1539AIVEZ (Note 2)
1539A IVEZ
-40 to +85
-40 to +85
24 Ld HTSSOP
24 Ld HTSSOP
COMING SOON
ISL1539AIVEZ-T13 (Notes 1, 2) 1539A IVEZ
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL1539A. For more information on MSL please
see techbrief TB363.
FN6916.0
September 23, 2009
3
ISL1539A
Absolute Maximum Ratings (T = +25°C)
Thermal Information
A
V + to V - Supply Voltage . . . . . . . . . . . . -0.3V to +26.4V
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
S
S
V + Voltage to GND . . . . . . . . . . . . . . . . . -0.3V to +26.4V
S
24 Ld QFN Package (Notes 4, 5) . .
24 Ld HTSSOP Package (Notes 4, 5)
39
4.5
V - Voltage to GND . . . . . . . . . . . . . . . . . -26.4V to +0.3V
S
TBD
TBD
Driver V + Voltage . . . . . . . . . . . . . . . . . . . . . V - to V +
IN
S
S
Maximum Junction Temperature (Plastic Package). . . +150°C
Current into any Input. . . . . . . . . . . . . . . . . . . . . . . . 8mA
Continuous Output Current for Long Term Reliability . . . . 50mA
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . See Figure 42
Storage Temperature Range. . . . . . . . . . . -40°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
C , C Voltage to GND . . . . . . . . . . . . . . . . . .-0.3V to +6V
0
1
I
Voltage to GND . . . . . . . . . . . . . . . . . . . . . -1V to +4V
ESD Rating
ADJ
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 200V
Human Body Model (Per MIL-STD-883 Method 3015.7). . 3kV
Charge Device Model . . . . . . . . . . . . . . . . . . . . . . 1.5kV
Operating Conditions
Ambient Temperature Range . . . . . . . . . . . .-40°C to +85°C
Junction Temperature Range . . . . . . . . . . . -40°C to +150°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. QFN and HTSSOP
JA
exposed pad soldered to PCB per JESD51-5. See Tech Brief TB379 for details.
5. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise
noted, all tests are at the specified temperature and are pulsed tests, therefore: T = T = T
J
C
A
Electrical Specifications V = ±12V, R = 100Ω differential, I
= C = C = 0V, A = 10V/V, R = 3.2kΩ,
0 1 V F
S
L
ADJ
T = +25°C. Amplifier pairs tested separately unless otherwise indicated.
A
PARAMETER
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
BW
-3dB Small Signal Bandwidth V < 2V
A = 10
V
240
120
100
3000
-93
-90
-88
-91
-109
-91
-87
-95
-86
-70
MHz
MHz
MHz
V/µs
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
O
P-P-DIFF,
P-P-DIFF
V
< 2V
(Note 6)
O
-3dB Large Signal Bandwidth V = 10V
O
P-P-DIFF
SR
20% to 80%
V
V
V
V
V
V
V
V
V
V
= 32V
2000
O
P-P-DIFF
200kHzHarmonic 2nd Harmonic
Distortion
= 10V
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
P-P-DIFF
P-P-DIFF
P-P-DIFF
P-P-DIFF
P-P-DIFF
P-P-DIFF
P-P-DIFF
P-P-DIFF
P-P-DIFF
3rd Harmonic
= 10V
= 10V
THD
1MHz Harmonic
Distortion
2nd Harmonic
3rd Harmonic
THD
= 2V
= 2V
= 2V
= 2V
= 2V
= 2V
8MHz Harmonic
Distortion
2nd Harmonic
3rd Harmonic
THD
MTPR
Multi-Tone Power Ratio
26kHz to 8MHz, 4kHz Tone Spacing,
= 19dBm, VDSL2+ 8b (Note 6)
P
LINE
200kHzHarmonic 2nd Harmonic
V
V
V
= 10V
= 10V
= 10V
(Note 6)
(Note 6)
(Note 6)
-93
-90
-88
dBc
dBc
dBc
OUT
OUT
OUT
P-P-DIFF
P-P-DIFF
P-P-DIFF
Distortion
3rd Harmonic
THD
FN6916.0
September 23, 2009
4
ISL1539A
Electrical Specifications V = ±12V, R = 100Ω differential, I
= C = C = 0V, A = 10V/V, R = 3.2kΩ,
0 1 V F
S
L
ADJ
T = +25°C. Amplifier pairs tested separately unless otherwise indicated. (Continued)
A
PARAMETER
DESCRIPTION
2nd Harmonic
CONDITIONS
MIN
TYP
MAX
UNIT
4MHz Harmonic
Distortion
V
= 10V
-72
dBc
OUT
(Note 6)
P-P-DIFF
P-P-DIFF
P-P-DIFF
3rd Harmonic
THD
V
= 10V
-70
-68
dBc
dBc
OUT
(Note 6)
V
= 10V
OUT
(Note 6)
8MHz Harmonic
Distortion
2nd Harmonic
3rd Harmonic
THD
V
V
V
= 2V
= 2V
= 2V
(Note 6)
-83
-78
-76
4.0
dBc
dBc
OUT
OUT
OUT
P-P-DIFF
P-P-DIFF
P-P-DIFF
(Note 6)
(Note 6)
dBc
e
Non-Inverting Input Voltage f = 1MHZ
Noise at each of the 4 Inputs
nV/√Hz
N
+i
Non-Inverting Input Current f = 1MHZ
Noise at each of the 4 Inputs
2.7
23
90
pA/√Hz
pA/√Hz
nV/√Hz
N
-i
Inverting Input Current Noise f = 1MHZ
at each of the 4 Inputs
N
e
Common Mode Output Noise f = 1MHZ
at each Port Pair
N-CM
POWER CONTROL FEATURES
V
V
Logic High Voltage
Logic Low Voltage
C and C inputs
2.0
V
V
IH
IL
0
1
C and C inputs
0.8
+5
0
1
I
I
I
I
Logic High Current for C
C
C = 3.3V, C = 3.3V
-5
1
µA
µA
Ω
IH0 , IH1
0,
1
0
1
I
Logic Low Current for C or C C = 0V, C = 0V
-17
-13
500
-10
IL0, IL1
0
1
0
1
Input Resistance
ADJ
SUPPLY CHARACTERISTICS
Maximum Operating Supply
Voltage
±12.6
±7.5
V
V
Minimum Operating Supply
Voltage
I
GND Pin Current per Port
All outputs at 0V (Note 7)
All outputs at 0V, C = C = 0V, No
0.2
21
0.4
0.5
mA
mA
GND
I + (Full Power) Positive Supply Current per
S
27.2
31.5
0
1
Port
Load
I + (Medium)
Positive Supply Current per
Port
All outputs at 0V, C = 3.3V, C = 0V,
No Load
17.8
10.4
0.2
23
13.5
0.4
26.7
15.6
0.5
mA
mA
mA
S
0
1
I + (Low)
Positive Supply Current per
Port
All outputs at 0V, C = 0V, C = 3.3V,
S
0
1
No Load
I + (Power-down) Positive Supply Current per
S
All outputs at 0V, C = C = 3.3V, No
0
1
Port
Load
OUTPUT CHARACTERISTICS
V
Output Swing
R
R
R
R
R
= No Load
= 100Ω
= 100Ω
= 60Ω
±10.7
+10.3
±10.9
+10.5
-10.4
+9.8
-9.7
V
V
OUT
L-DIFF
L-DIFF
L-DIFF
L-DIFF
L-DIFF
Lightly Loaded Positive Swing
Lightly Loaded Negative Swing
Heavy Loaded Positive Swing
Heavy Loaded Negative Swing
Linear Output Current
-10.2
-9.3
V
+9.4
V
= 60Ω
V
I
R = 25Ω, f = 100kHz, THD = -60dBc
±360
mA
OL
L
FN6916.0
September 23, 2009
5
ISL1539A
Electrical Specifications V = ±12V, R = 100Ω differential, I
= C = C = 0V, A = 10V/V, R = 3.2kΩ,
0 1 V F
S
L
ADJ
T = +25°C. Amplifier pairs tested separately unless otherwise indicated. (Continued)
A
PARAMETER
DESCRIPTION
CONDITIONS
= ±1V, R = 1Ω
MIN
TYP
MAX
UNIT
I
Peak Output Current
V
±600
mA
OUT
OUT
L
INPUT CHARACTERISTICS
Input Offset Voltage
Input V Mismatch
V
-8
-2
+3.5
0
+8
+2
mV
mV
OS
ΔV
OS
OS
Between Amplifiers for Each
Port
V
Input V
OS
Drift
-25°C to +125°C T
±15
µV/°C
µA
OS, DRIFT
J
I +
Non-Inverting Input Bias
Current
-8
-2
+8
+2
B
ΔI +
Non-Inverting I + Mismatch
B
µA
B
Between Amplifiers for Each
Port
I +
Non-Inverting I + Drift
B
-25°C to +125°C T
-25°C to +125°C T
±12
nA/°C
µA
B
, DRIFT
J
I -
Inverting Input Bias Current
-75
-35
+75
+35
B
ΔI -
Inverting I - Mismatch
B
Between Amplifiers for Each
Port
µA
B
I -
B , DRIFT
Inverting I - Drift
B
±25
nA/°C
V
J
CMIR
Common Mode Input Range
at each of the 4
±7.5
Non-Inverting Input Pins
CMRR
Common Mode Rejections for
V
to Differential Mode Output
80
43
dB
dB
CM
each Port. V
= -5V to +5V (Input Referred)
CM
V
to Commonl Mode Output
CM
(Output Referred)
PSRR
Power Supply Rejections for +V = +7.5V to +12V, -V = -12V
97
92
dB
dB
S
S
each Port to Differential
Output (Input Referred)
-V = -7.5V to -12V, +V = +12V
S
S
Power Supply Rejections for +V = +7.5V to +12V, -V = -12V
51
45
dB
dB
S
S
each Port to Common Mode
Output (Output Referred)
-V = -7.5V to -12V, +V = +12V
S
S
NOTES:
6. Active Termination Test Circuit. Low Power Mode (see Figure 45).
7. The -V supply current is the +V supply current minus the ground current, except power down condition.
S
S
FN6916.0
September 23, 2009
6
ISL1539A
Typical Performance Curves
V
= ±12V, R = 3.2kΩ, G = 10V/V (differential), R
LOAD
= 100Ω, T ≈ +25°C, C0 = C1 = I
= 0V (full power),
CC
F
D
A
ADJ
unless otherwise noted.
9
V
= 0.5V
2V
O
P-P
P-P
6
3
5V
AV = 10, R = 3.2kΩ
P-P
F
AV = 20, R = 2.5kΩ
F
A
= 10
V
0.5V
P-P
10V
20V
P-P
AV = 40, R = 2.4kΩ
F
0
-3
-6
-9
-12
P-P
A
= 40
V
A
= 20
V
1M
10M
100M
1G
FREQUENCY (Hz)
FIGURE 1. SMALL SIGNAL FREQUENCY RESPONSE vs
GAIN
FIGURE 2. LARGE SIGNAL FREQUENCY RESPONSE
3rd HD
2nd HD
2nd HD
THD
THD
3rd HD
FIGURE 3. 1MHz HARMONIC DISTORTION vs
OUTPUT SWING
FIGURE 4. 4MHz HARMONIC DISTORTION vs
OUTPUT SWING
20
PAR = 5.4
14.5dBm ON LINE
10
THD
0
-10
-20
-30
-40
-50
-60
-70
-80
FIGURE 45 CIRCUIT
-64dBc
2nd HD
3rd HD
7.995M
8.000M
8.005M
FREQUENCY (Hz)
FIGURE 6. 4MHz HARMONIC DISTORTION vs LOAD
FIGURE 5. 17MHz DMT PROFILE
FN6916.0
September 23, 2009
7
ISL1539A
Typical Performance Curves
V
= ±12V, R = 3.2kΩ, G = 10V/V (differential), R
LOAD
= 100Ω, T ≈ +25°C, C0 = 3.3V, C1 = I
= 0V
ADJ
CC
F
D
A
(medium power), unless otherwise noted.
9
V
= 0.5V
O
P-P
2V
P-P
6
3
AV = 10, R = 3.2kΩ
5V
P-P
F
AV = 20, R = 2.8kΩ
F
A
= 10
V
0.5V
P-P
10V
AV = 40, R = 2.4kΩ
P-P
F
0
20V
P-P
-3
-6
-9
-12
A
= 40
V
A
= 20
V
1M
10M
100M
1G
FREQUENCY (Hz)
FIGURE 8. LARGE SIGNAL FREQUENCY RESPONSE
FIGURE 7. SMALL SIGNAL FREQUENCY RESPONSE vs
GAIN
3rd HD
2nd HD
3rd HD
2nd HD
THD
THD
FIGURE 10. 4MHz HARMONIC DISTORTION vs
OUTPUT SWING
FIGURE 9. 1MHz HARMONIC DISTORTION vs
OUTPUT SWING
20
PAR = 5.4
19dBm ON LINE
FIGURE 45 CIRCUIT
0
-20
-65dBc
-40
-60
2nd HD
3rd HD
THD
-80
-100
8.395M
8.400M
8.405M
FREQUENCY (Hz)
FIGURE 12. 4MHz HARMONIC DISTORTION vs LOAD
FIGURE 11. VDSL2+ 8MHz DMT PROFILE
FN6916.0
September 23, 2009
8
ISL1539A
Typical Performance Curves
V
= ±12V, R = 3.2kΩ, G = 10V/V (differential), R
LOAD
= 100Ω, T ≈ +25°C, C1 = 3.3V, C0 = I
ADJ
= 0V (low
CC
F
D
A
power), unless otherwise noted.
9
V
= 0.5V
O
P-P
6
3
AV = 10, R = 3.2kΩ
F
AV = 20, R = 2.8kΩ
F
0.5V
P-P
A
= 10
V
AV = 40, R = 2.4kΩ
10V
P-P
F
2V
P-P
0
-3
-6
-9
-12
20V
P-P
5V
A
= 40
V
P-P
A
= 20
V
1M
10M
100M
1G
FREQUENCY (Hz)
FIGURE 13. SMALL SIGNAL FREQUENCY RESPONSE
vs GAIN
FIGURE 14. LARGE SIGNAL FREQUENCY RESPONSE
THD
THD
3rd HD
2nd HD
2nd HD
3rd HD
FIGURE 15. 1MHz HARMONIC DISTORTION vs
OUTPUT SWING
FIGURE 16. 4MHz HARMONIC DISTORTION vs
OUTPUT SWING
20
PAR = 5.4
19dBm ON LINE
FIGURE 45 CIRCUIT
THD
0
-20
-60dBc
-40
2nd HD
3rd HD
-60
-80
-100
1.995M
2.000M
2.005M
FREQUENCY (Hz)
FIGURE 18. 4MHz HARMONIC DISTORTION vs LOAD
FIGURE 17. ADSL2+ DMT
FN6916.0
September 23, 2009
9
ISL1539A
Typical Performance Curves
V
= ±12V, R = 3.2kΩ, G = 10V/V (differential), R
LOAD
= 100Ω, T ≈ +25°C, C0 = C1= I
= 0V (full power),
CC
F
D
A
ADJ
unless otherwise noted.
2.2kΩ
22pF
2.6kΩ
15pF
3.2kΩ
3.8kΩ
4.7pF
0pF
4.6kΩ
FIGURE 19. SMALL SIGNAL FREQUENCY RESPONSE
vs RF
FIGURE 20. SMALL SIGNAL FREQUENCY RESPONSE
vs C
LOAD
-40
-50
5V
P-P-DIFF
THD
Rs = 26.7Ω
= 22pF
Rs = 84.5Ω
= 4.7pF
C
L
C
L
-60
-70
2nd HD
-80
Rs = 50Ω
C
= 10pF
L
-90
Rs = 38.4Ω
3rd HD
10M
C
= 15pF
L
-100
100k
1M
100M
FREQUENCY (Hz)
FIGURE 21. SMALL SIGNAL FREQUENCY RESPONSE
vs C WITH Rs
FIGURE 22. DISTORTION vs FREQUENCY
LOAD
100
10
1
INVERTING CURRENT NOISE
VOLTAGE NOISE
NON-INVERTING CURRENT NOISE
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 23. INPUT VOLTAGE AND CURRENT NOISE DENSITY
FN6916.0
September 23, 2009
10
ISL1539A
Typical Performance Curves
V
= ±12V, R = 3.2kΩ, G = 10V/V (differential), R
LOAD
= 100Ω, T ≈ +25°C, C0 = 3.3V, C1 = I = 0V
ADJ
CC
F
D
A
(medium power), unless otherwise noted.
2.2kΩ
22pF
2.6kΩ
15pF
4.7pF
3.2kΩ
3.8kΩ
0pF
4.6kΩ
FIGURE 24. SMALL SIGNAL FREQUENCY RESPONSE
vs RF
FIGURE 25. SMALL SIGNAL FREQUENCY RESPONSE
vs C
LOAD
-40
-50
5V
P-P-DIFF
Rs = 26.7Ω
CL = 22pF
THD
Rs = 84.5Ω
-60
CL = 4.7pF
-70
Rs = 50Ω
CL = 10pF
-80
2nd HD
-90
Rs = 38.4Ω
3rd HD
CL = 15pF
-100
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 26. SMALL SIGNAL FREQUENCY RESPONSE
vs CLOAD WITH Rs
FIGURE 27. DISTORTION vs FREQUENCY
100
INVERTING CURRENT NOISE
10
VOLTAGE NOISE
NON-INVERTING CURRENT NOISE
1
100
1k
10k
FREQUENCY (Hz)
FIGURE 28. INPUT VOLTAGE AND CURRENT NOISE DENSITY
100k
1M
10M
FN6916.0
September 23, 2009
11
ISL1539A
Typical Performance Curves
V
= ±12V, R = 3.2kΩ, G = 10V/V (differential), R
LOAD
= 100Ω, T ≈ +25°C, C1= 3.3V, C0 = I
= 0V (low
CC
F
D
A
ADJ
power), unless otherwise noted.
22pF
2.2kΩ
2.6kΩ
15pF
3.2kΩ
0pF
3.8kΩ
4.7pF
4.6kΩ
FIGURE 29. SMALL SIGNAL FREQUENCY RESPONSE
vs RF
FIGURE 30. SMALL SIGNAL FREQUENCY RESPONSE
vs CLOAD
-40
5V
P-P-DIFF
-50
-60
Rs = 26.7Ω
CL = 22pF
Rs = 84.5Ω
CL = 4.7pF
THD
-70
Rs = 38.4Ω
CL = 15pF
2nd HD
Rs = 50Ω
CL = 10pF
-80
-90
3rd HD
-100
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 32. DISTORTION vs FREQUENCY
FIGURE 31. SMALL SIGNAL FREQUENCY RESPONSE
vs CLOAD WITH Rs
100
INVERTING CURRENT NOISE
10
VOLTAGE NOISE
NON-INVERTING CURRENT NOISE
1
100
1k
10k
FREQUENCY (Hz)
FIGURE 33. INPUT VOLTAGE AND CURRENT NOISE DENSITY
100k
1M
10M
FN6916.0
September 23, 2009
12
ISL1539A
Typical Performance Curves
V
= ±12V, R = 3.2kΩ, G = 10V/V (differential), R = 100Ω, T ≈ +25°C, C0 and C1 Parametric, unless
LOAD A
CC
F
D
otherwise noted.
-20
-30
-40
-50
-60
-70
-80
-90
-100
OUTPUT -> OUTPUT REFERRED
FULL POWER
PortCD=>PortAB
MEDIUM POWER
LOW POWER
PortAB=>PortCD
100k
1M
10M
FREQUENCY (Hz)
100M
FIGURE 35. CHANNEL TO CHANNEL X-TALK
FIGURE 34. COMMON MODE SMALL SIGNAL
FREQUENCY RESPONSE
-20
26
23
20
INPUT REFERRED
-30
-40
±12V
-50
17
-60
±10V
-70
14
±7.5
-PSRR
-80
11
8
-90
-100
-110
-120
+PSRR
5
2
100k
1M
10M
100M
1M
10M
100M
1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 36. SMALL SIGNAL BANDWIDTH vs SUPPLY
VOLTAGE
FIGURE 37. +PSRR TO DIFFERENTIAL OUTPUT
1 PORT
FULL POWER
MEDIUM LOW POWER
NEGATIVE
LOW POWER
POSITIVE
FIGURE 38. SUPPLY CURRENT vs R
ADJ
FN6916.0
September 23, 2009
13
ISL1539A
Typical Performance Curves
V
= ±12V, R = 3.2kΩ, G = 10V/V (differential), R
LOAD
= 100Ω, T ≈ +25°C, I
= 0V, C0, C1 varied, unless
CC
F
D
A
ADJ
otherwise noted.
C0, C1
1V/Div
1V/Div
C0, C1
VOUT
VOUT
2V/Div
2V/Div
40ns/DIV
2µs/DIV
FIGURE 39. POWER-UP TIME
FIGURE 40. POWER-DOWN TIME
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
EXPOSED DIEPAD SOLDER TO PCB PER JESD51-5
0
-20
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
HTSSOP24 = +36°C/W
QFN24 = +39°C/W
-40
-60
-80
-100
-120
85
1M
10M
100M
0
25
50
75
100
125
150
FREQUENCY (Hz)
AMBIENT TEMPERATURE (°C)
FIGURE 41. OFF-ISOLATION
FIGURE 42. PACKAGE POWER DISSIPATION vs
AMBIENT TEMPERATURE
FN6916.0
September 23, 2009
14
ISL1539A
Test Circuit
A
R
NETWORK
ANALYZER
+12
DC
SPLITTER
S
50Ω
50Ω
LOAD
1:1
487Ω
53Ω
DUT
180°
SPLITTER
R
L
487Ω
50Ω
-12
FIGURE 43. FREQUENCY RESPONSE CHARACTERIZATION CIRCUIT
FN6916.0
September 23, 2009
15
ISL1539A
power for Channels A and B together and then the other
pair controls Channels C and D together.
Applications Information
Applying Wideband Current Feedback Op
Amps as Differential Drivers
Very low output distortion at low power can be provided
by the differential configuration. The high slew rate
intrinsic to the CFA topology also contributes to the
exceptional performance shown in Figures 22, 27 and 32.
These swept frequency distortion plots show extremely
low distortion at 200kHz holding to very low levels up
through 20MHz. At the lowest operating power
A current feedback amplifier (CFA) like the ISL1539A is
particularly suited to the requirements of high output
power, high full power bandwidth, differential drivers.
This topology offers a very high slew rate on low
quiescent power and the ability to hold relatively
constant AC characteristics over a wide range of gains.
The AC characteristics are principally set by the feedback
resistor value in simple differential gain circuits as shown
in Figure 44.
(Figure 32, which is at low power, or 6.75mA per
amplifier or 13.5mA/port) we still see < -70dBc through
5MHz for a 5V
differential output swing.
P-P
Advanced Configurations - Active
Termination
+12V
Where the best power efficiency is required in a full
duplex DSL line interface application, it is common to
apply the circuit shown below to reduce the power loss in
the matching element while retaining a higher
impedance for the upstream signal coming into this
output stage. This circuit acts to provide a higher
apparent output impedance (through its cross-coupled
positive feedback through the Rp resistors) while
physically taking a smaller IR drop through the Rm
resistors for the output signal..
+
¼
Ro
Rb
ISL1539A
-
Rf
1:n
3.2k
VI
VO
Rg711
Rf
LOAD
SOURCE
3.2k
-
¼
ISL1539A
+
+12V
Ro
1 PORT OF 2
DRAWN
I = 13.5mA
AV-DIFF = VO/VI = 10V/V
+
Rb
50Ω
-12V
¼
ISL1539A
0V
C0
TYPICAL DIFFERENTIAL I/O LINE DRIVER
(1 OF 2 PORTS)
3.3V
-
C1
FIGURE 44. PASSIVE TERMINATION CIRCUIT
Rf
Rp
Rp
Rf
Rm
RL
Vdiff
POWER
SPLITTER
In this differential gain of 10 V/V circuit, the 3.2k
feedback resistors are setting the bandwidth while the
711 gain resistor controls the gain. The Vo/Vi gain for
this circuit is set by Equation 1:
Vi
Rg
Ω
82.6
Vo
Rm
2
Ω
RL = 100 /(1.1) = 82.6
Vo/Vdiff = 9.77 V/V (19.8dB)
-
Rf
Rg
Vo
Vi
3.2kΩ
711Ω
¼
(EQ. 1)
=1+ 2
=1+ 2
=10
ISL1539A
Radj
+
Ω
0
Ω
50
The effect of increasing or decreasing the feedback
-12V
resistor value is shown in Figures 19, 24 and 29 (at the 3
power settings). Increasing R will tend to roll off the
response while decreasing it will peak the frequency
F
FIGURE 45. ACTIVE TERMINATION TEST CIRCUIT
response up extending the bandwidth. R was adjusted
G
This circuit is showing one of two ports configured in an
active termination circuit used for some of the
specification and characterization tests. This is showing
the device operating in the low power mode, but data
has been shown at the other power settings as well.
in each of these plots to hold a constant gain of 10 (or
20dB). This shows the flexibility offered by the CFA
topology - the frequency response can be controlled with
the value of the feedback resistor with the R resistor
G
then setting the desired gain.
The 82.6Ω differential load is intended to emulate a 100Ω
The ISL1539A provides 4 very power efficient, high
output current, CFA's. These are intended to be
connected as two pairs of differential drivers. The pinout
diagrams of page two show that Channels A and B are
intended to operate as a pair while Channels C and D
comprise the other pair. Power control is also provided
through two pairs of control pins which separately set the
line load reflected through a 1:1.1 turns ratio
2
transformer (100Ω/(1.1 ) = 82.6Ω load). The gain and
output impedance for this circuit can be described by the
following equations.
The ideal transfer function is set by the open circuit gain
(RL = infinite) and an equivalent output impedance Z .
O
FN6916.0
September 23, 2009
16
ISL1539A
produce a 40V
P-P
differential swing which will drop to the
load divided by 1.36 - or a 29.41V differential swing.
Vo
Vi
RL
P-P
(EQ. 2)
= Aoc
Distortion and MTPR
RL + Zo
The ISL1539A is intended to provide very low distortion
levels under the demanding conditions required by the
discrete multi-tone (DMT) characteristic of modern DSL
modulations. The standard test for linearity is the Multi-
Tone Power Ratio (MTPR) test where a specified standard
is loaded up with discrete carriers over the specified
frequencies in such a way as to produce the maximum
rated line power and Peak to Average Ratio (PAR) with
some tones missing. The measure of linearity is the
separation from the active tones vs. a missing tone. To
the extent that the amplifier is slightly non-linear, it will
fold a small amount of power into the missing tones
through intermodulation products for the active tones.
Figure 17 shows the circuit operating at the low power
setting used to test ADSL2+ frequency plan and power.
For this test the carriers are spaced at 5kHz.
The goal of the positive feedback resistor, R , is to
provide some “gain” in the apparent output impedance
over just the 2*R . It also will act to increase the A
over the simple differential gain equation if a synthesis
factor (SF) is defined as shown in Equation 3:
P
M
OC
1
SF =
(EQ. 3)
Rf − Rm
1−
Rp
We can see this "gain" is achieved by letting R be > R
The closer R is to R -R , the more "gain" is achieved
but at the risk of instability. With this SF defined as
shown above, the exact A
Equations 4 and 5:
P
F
P
F
M
and Z will be as shown in
OC
O
This -60dBc MTPR is exceptional for the very low 13.5mA
total quiescent current used in this configuration.
Operating at reduced power targets on the line will
improve MTPR as will operating the amplifiers at higher
quiescent current.
Rf Rf − Rm
(EQ. 4)
Aoc = SF(1+ 2
+
)
Rg
Rp
The characteristic curves show the exceptional single
tone performance available using the ISL1539A. At the
highest quiescent power, operating at a simple
(EQ. 5)
Zo = SF(2Rm )
For test purposes, the circuit shown in Figure 45 was
configured to achieve the following results.
differential gain of 10V/V, Figure 22 shows the 5V
distortion plot.
P-P
SF = 2.19
Figure 22 shows a better than -80dBc through 8MHz for
the 2nd and 3rd harmonics. The rapid rise in the spurious
above 10MHz is coming from the onset of fine scale slew
limiting effects. By 20MHz, the output signal is requiring
a differential slew rate of 300V/µs - a significant portion
of the available 3000V/µs slew rate available at full
power.
A
= 17.7V/V
OC
Z = 66Ω
O
Putting these together into the gain to an 82.6Ω load
gives the following test condition as shown by
Equation 6.
Vo
Vi
RL
82.6Ω
82.6Ω + 66Ω
V
⎛ ⎞
Power Control Function
= Aoc
=17.7
= 9.84
⎜ ⎟
RL + Zo
V
⎝ ⎠
Figure 46 shows a simplified schematic for the power
control features included in the ISL1539A. Each of the 4
differential pairs shown in the drawing are used to steer
(EQ. 6)
The advantage offered by this technique is that for
whatever swing we desire at the load, there is less rise
through the physical output matching resistor than if we
simply inserted two 33Ω R resistors to achieve the 66Ω
output impedance achieved in this test circuit. Whatever
load current is required in R will rise to the output pins
through 2*R . The rise from the load swing to the output
pin swing is given by Equation 7:
control currents (I
mirrors (not shown) that control the quiescent bias
terms) into additional current
BIAS
current for each of the two ports. This bias control shares
M
the I
pin. When I is grounded, the typical supply
ADJ
ADJ
current levels shown in the “Electrical Specifications”
tables on page 5 are produced. Inserting an external
L
M
resistor to ground in the I
currents down, as shown in Figure 38.
pin will scale the quiescent
ADJ
RL + 2Rm
It is also possible to scale the I currents up by tying
the I
ADJ
long as the resulting voltage divider between this
external negative voltage and the internal +0.4V on the
other side of the 500Ω resistor stays above the
ADJ
pin through a resistor to a negative supply. As
(EQ. 7)
RL
This was only 1.36 for the test circuit shown above. In
differential circuits the ±V at the output pins produces a
P
maximum rated negative voltage on the I
pin (-1V).
ADJ
4V for the differential peak-to-peak voltage. Hence a
P
For instance, to double the typical quiescent current
levels, the current in the I pin must be doubled from
±10V swing at each output in the above circuit will
ADJ
its nominal 800µA level. Using a -5V supply through an
FN6916.0
September 23, 2009
17
ISL1539A
external 2.88kΩ resistor will double the current while
leaving the I pin voltage at approximately -0.4V,
with the output to isolate the phase margin effects of the
capacitor. Figure 20 on page 10 shows the effect of
capacitive load on the differential gain of 10 circuit. With
15pF on each output, we see about 5dB peaking. This will
ADJ
which is well within rated minimum. This approach
should be used with great caution as very high internal
power dissipations can easily be produced. However, it
can be a useful approach to extend operation,
particularly when operating on lower total supply
voltages than the rated typical of ±12V.
increase quickly at higher C
peaking is unacceptable, a small series resistor can be
. If this degree of
loads
used to improve the flatness as shown in Figure 21.
Output DC Error Model
+VCC
+VCC
+VCC
+VCC
IBIAS IBIAS
IBIAS IBIAS
Often, non-inverting bias current (ibn), inverting bias
current (ibi), and input offset voltage (Vio) are quite low
for typical op amps.
+3.3V
50k
+3.3V
+3.3V
+3.3V
50k
50k 50k
Vio, ibn, ibi can be mapped to output offset both
common and differential mode. Consider the circuit in
Figure 47.
+1.4
V
+1.4V
COAB
C1CD
C1AB
COCD
+1V
+Vcc
± Vio
500
RO
+
IADJ
±ibn
FIGURE 46. BIAS CONTROL CIRCUIT
Rb
-
The current in RO divides in 1/4 levels to form the bias
current for the 4 pairs of differential switches. Each pair
of switches controls the quiescent current for one port.
Rf
Vcm ± Vocm ± Vodm
±ibi
±ibi
Vcm
Rcm
Zg
For instance, C0 and C1
control the quiescent
AB AB
+Vcc
current for the port constructed from amplifiers A and B.
If both control lines are unconnected externally, the
internal 50kΩ pull-up will switch the differential pairs to
divert the 100µA tail currents into the supply turning off
the amplifiers. Taking both control pins low will pass both
Rf
-
Rb
±Vio
+
I
lines on into scaling current sources. With I
BIAS
grounded, this will give the typical 27.2mA total
REF
± ibn
quiescent current for a port shown in the “Electrical
Specification” tables on page 5. Taking C high (>2V)
FIGURE 47. DC ERROR MODEL
0
while leaving C low (<0.8V) will reduce the current into
1
The output common mode offset voltage (Vo-cm) is
derived from the input common mode voltage (Vi-cm),
as expressed in Equations 8 and 9:
a port to a typical 23mA. Taking C high, while leaving C
1
0
low will reduce the current in a port to a typical 13.5mA
supply current. Table 2 summarizes the operation modes
for ISL1539A for each port.
(EQ. 8)
Vicm = ±2 × ibn × Rcm ± ibn × Rb ± Vio
TABLE 2. POWER MODES OF THE ISL1539A
(EQ. 9)
Vocm = ± Vicm ± Rf × ibi
C
C
OPERATION
I Full Power Mode
1
0
0
0
1
1
0
1
0
1
S
The output differential mode offset voltage (Vo-dm) is
derived from the input differential mode voltage (Vi-dm),
as expressed in Equations 10 and 11:
I Medium Power Mode
S
I Low Power Mode
S
Vidm = ±Δibn × Rb ± ΔVio
(EQ. 10)
Power-Down
2Rf
Rg
⎛
⎞
⎠
---------
Vodm = ±Vidm × 1 +
± Δibi × Rf
Performance Considerations
(EQ. 11)
⎝
Driving Capacitive Loads
Example:
All closed loop op amps are susceptible to reduced phase
margin when driving capacitive loads. This shows up as
peaking in the frequency response that can, in extreme
situations, lead to oscillations. The ISL1539A is designed
to operate successfully with small capacitive loads such
as layout parasitics. As the parasitic capacitance
Referring to the “Electrical Specification” tables on
page 6:
ibn = 8µA, Δibn = 2µA
ibi = 75µA, Δibi = 35µA
Vio = 8mV, ΔVio = 2mV
increases, it is best consider a small resistor in series
FN6916.0
September 23, 2009
18
ISL1539A
Assuming Rf = 3kΩ, Rg = 333Ω, Rb = 7.5kΩ Rcm = 5kΩ,
the total output offset voltage derived is expressed in
Equation 12:
+VS
-
+
(EQ. 12)
Vcm = Vocm + 0.5 × Vodm = 434mV
Given the worst case DC errors, 434mV of DC shift will
be at the output reducing the available output swing
slightly. Actual operation should never see this much
shift as the error terms are not completely
independent.
RL
VP
-
+
-VS
Output Headroom Model
FIGURE 49. HEADROOM MODEL
Driving high voltages into heavy loads will require a
careful consideration of the available output swing vs.
load. Figure 48 shows a useful model for predicting the
available output swing. If the output is modeled as ideal
NPN and PNP transistors, the output swing limits can be
described as no load headrooms (V and V ) and an
For equal bipolar supplies, the available peak output
swing will be given by Equation 13:
2(Vs −Vp −Vn )
Vp =
P
N
(EQ. 13)
Rp + Rn
equivalent impedance to the supplies (R and R )
P
N
1+
RL
+VS
For example, to worst case the typical gain of 10 design
using ±12V supplies with ±5% supply tolerance and a
RP
+
–
minimum expected load of 90Ω, a maximum V can be
VP
P
calculated as shown in Equation 14:
+/-VO
RL
2(Vs −Vp −Vn )
2(11.4 − 2.2)
6.7Ω + 7.4Ω
Vp =
=
=15.9Vp
Rp + Rn
1+
1+
90Ω
RL
+
–
VN
(EQ. 14)
RN
The minimum V
P-P
would be twice this, or 31.8V .
P-P
-VS
While this extreme condition would normally not be
encountered, it does show the importance of knowing
your minimum expected load for high output swing
conditions.
FIGURE 48. HEADROOM MODEL
The no load headrooms can be found in the “Electrical
Specifications” table on page 5 as 12V - 10.9V = 1.1V
and they are equal to each supply.
Output Noise Model
The full differential output noise model for the ISL1539A
should include the 3 input noise terms for each device as
well as the noise contributions due to the external
resistors.
The equivalent impedances for this model can be
extracted from the reduced swings shown in the
specification table for the heavier loads. Looking at the
typical 60Ω load swings, we see a +9.8V and -9.7V
swing. Solving for the two resistors in the Headroom
model shown in Figure 48 gives:
This necessarily becomes an involved model due to the
number of terms, but if the terms that are the same on
each side of the differential circuit can be assumed to be
equal, it will simplify considerably. The noise model
shown in Figure 50 includes all of the op amp terms and
resistor terms. This model is directed at calculating the
differential output spot noise for different values of the
resistors in the simple differential gain circuit. It is
assuming each amplifier term is independent and
uncorrelated to the other terms.
Rp = 6.7Ω and Rn = 7.4Ω.
For the differential configuration, Figure 49 shows the
Headroom model that can be used to predict the
maximum available swing for a given supply voltage and
load resistor, R .
L
FN6916.0
September 23, 2009
19
ISL1539A
Board Design Recommendations
RS
iN
eN
+
-
The feedback resistors need to be placed as close as
possible to the output and inverting input pins to
minimize parasitic capacitance in the feedback loop. This
includes the R and R resistors in the active termination
4kTRS
RF
ii
4kTRF
4kTRF
(nV Hz)
eO
F
P
4kT
RG
RG
RF
configuration. Keep the gain resistor also very close to
the inverting inputs for its port and minimize parasitic
capacitances to ground or power planes as well.
ii
-
+
RS
iN
Close placement of the supply decoupling capacitors
will minimize parasitic inductance in the supply path.
High frequency load currents are typically pulled
through these capacitors so close placement of 0.01µF
capacitors on each of the supply pins will improve
dynamic performance. Higher valued capacitors, 6.8µF
typically, can be placed further from the package as
they are providing more of the low frequency
decoupling.
eN
4kTRS
FIGURE 50. OUTPUT NOISE MODEL
In Figure 50, the circle sources are noise voltages while
the diamonds are noise currents and 4kT is 1.6E - 20J.
If the op amp terms are assumed to be equal for the two
sides of the circuit and two R and R resistors are also
F
S
equal, and the differential gain is defined as
Ad = 1+2R /R , the differential output noise expression
The thermal pad for the ISL1539A should be connected
F
G
to either ground or the -V power plane. The choice of
becomes Equation 15.
S
which plane depends on which one would have the
more accessible thermal area.
eo = 2
(
Ad2
)(
en2 +
(
inRs
)
2 + 4kTRs
)
+ 2
(
iiRf
)
2 + 2Ad
4kTRf
)
While the ISL1539A is relatively robust in driving
parasitic capacitive loads, it is always preferred to get
into any series output resistor needed in the design as
physically close as possible to the output pins. Then
trace capacitance on the other side of that resistor will
have a much smaller effect on loop phase margin.
(EQ. 15)
Putting in numbers for the gain of 10 characterization
circuit (with R = 50Ω) gives a differential output noise of
e = 69nV/√Hz. Dividing this by the differential gain of 10
S
o
gives an input noise of e = 6.9nV/√Hz which is only
i
slightly more than the RMS sum of the two 4nV input
voltage noise terms for the op amps themselves
(5.7nV/√Hz).
Protection devices that are intended to steer large load
transients away from the ISL1539A output stage and
into the power supplies or ground should have a short
trace from their supply connections into the nearest
supply capacitor - or should include their own supply
capacitors to provide a low impedance path under fast
transient conditions.
FN6916.0
September 23, 2009
20
ISL1539A
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
CHANGE
9/23/09
FN6916.0
Initial Release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The
Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
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*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISL1539A
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
FN6916.0
September 23, 2009
21
ISL1539A
Package Outline Drawing
L24.4x5B
24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 10/06
4.00
2.50
A
PIN 1
PIN #1 INDEX AREA
24X0.40
INDEX AREA
CHAMFER 0.40×0 X 45°
B
20
24
6
6
1
19
3.50
0.5x6=3.00 REF
7
13
12
8
0.10
0.25±0.05
0.10
4X
0.50
M
C A B
TOP VIEW
0.5x4=2.00 REF
BOTTOM VIEW
SEE DETAIL X''
0.10
C
C
SEATING PLANE
0.08
0.90±0.10
C
(24x0.25)
(20x0.50)
SIDE VIEW
(3.50)
(4.80 TYP)
5
0 . 20 REF
C
(24x0.60)
(2.50)
(3.80 TYP)
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.20mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
FN6916.0
September 23, 2009
22
ISL1539A
HTSSOP (Heat-Sink TSSOP) Family
0.25 M C A B
MDP0048
D
A
HTSSOP (HEAT-SINK TSSOP) FAMILY
(N/2)+1
N
MILLIMETERS
TOLER-
ANCE
SYMBOL 14 LD 20 LD 24 LD 28 LD 38 LD
PIN #1 I.D.
A
A1
A2
b
1.20
1.20
1.20
1.20
1.20
Max
±0.075
E
E1
0.075 0.075 0.075 0.075 0.075
0.90
0.25
0.15
5.00
3.2
0.90
0.25
0.15
6.50
4.2
0.90
0.25
0.15
7.80
4.3
0.90
0.25
0.15
9.70
5.0
0.90
0.22
0.15
9.70
7.25
6.40
4.40
3.0
+0.15/-0.10
+0.05/-0.06
+0.05/-0.06
±0.10
0.20 C B A
2X
1
(N/2)
N/2 LEAD TIPS
c
TOP VIEW
B
D
D1
E
Reference
Basic
D1
EXPOSED
THERMAL PAD
6.40
4.40
3.0
6.40
4.40
3.0
6.40
4.40
3.0
6.40
4.40
3.0
E1
E2
e
±0.10
Reference
Basic
0.65
0.60
1.00
14
0.65
0.60
1.00
20
0.65
0.60
1.00
24
0.65
0.60
1.00
28
0.50
0.60
1.00
38
E2
L
±0.15
L1
N
Reference
Reference
Rev. 3 2/07
BOTTOM VIEW
NOTES:
1. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15mm per
side.
0.05
H
e
C
2. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm per side.
SEATING
PLANE
3. Dimensions “D” and “E1” are measured at Datum Plane H.
0.10 M C A B
b
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
0.10 C
N LEADS
SIDE VIEW
SEE DETAIL ‚Äö
c
END VIEW
L1
A2
A
GAUGE
PLANE
0.25
L
A1
0¬¨¬
DETAIL X
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in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
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FN6916.0
September 23, 2009
23
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