ISL22346UFV20Z_技术文档

ISL22346

®

Quad Digitally Controlled Potentiometers (XDCP™)

Data Sheet

July 28, 2006

FN6177.0

2

Low Noise, Low Power I C^®Bus, 128 Taps

Features

The ISL22346 integrates four digitally controlled

potentiometers (DCP) and non-volatile memory on a

monolithic CMOS integrated circuit.

• Four potentiometers in one package

• 128 resistor taps

2

• I C serial interface

The digitally controlled potentiometers are implemented with

a combination of resistor elements and CMOS switches. The

position of the wipers are controlled by the user through the

- Three address pins, up to eight devices/bus

• Non-volatile storage of wiper position

• Wiper resistance: 70Ω typical @ 3.3V

• Shutdown mode

2

I C bus interface. Each potentiometer has an associated

volatile Wiper Register (WR) and a non-volatile Initial Value

Register (IVR) that can be directly written to and read by the

user. The contents of the WR controls the position of the

wiper. At power-up the device recalls the contents of the two

DCP’s IVR to the corresponding WRs.

• Shutdown current 5µA max

• Power supply: 2.7V to 5.5V

• 50kΩ or 10kΩ total resistance

The DCPs can be used as a three-terminal potentiometers

or as a two-terminal variable resistors in a wide variety of

applications including control, parameter adjustments, and

signal processing.

• High reliability

- Endurance: 1,000,000 data changes per bit per register

- Register data retention: 50 years @ T <55°C

• 20 Ld TSSOP

Pinout

• Pb-free plus anneal product (RoHS compliant)

ISL22346

(20 LD TSSOP)

TOP VIEW

RH3

RL3

RW3

A2

1

20

19

18

17

16

15

14

13

12

11

RW0

RL0

RH0

SHDN

VCC

A1

2

3

4

SCL

SDA

GND

RW2

RL2

RH2

5

6

7

A0

8

RH1

RL1

RW1

9

10

Ordering Information

RESISTANCE OPTION

TEMP. RANGE

PART NUMBER

PART MARKING

(kΩ)

(°C)

PACKAGE

20 Ld TSSOP

PKG. DWG. #

ISL22346UFV20Z

(Notes 1, 2)

22346 UFVZ

50

-40 to +125

M20.173

(Pb-Free)

ISL22346WFV20Z

(Notes 1, 2)

22346 WFVZ

10

-40 to +125

20 Ld TSSOP

(Pb-Free)

M20.173

NOTES:

1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are

MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

2. Add “-TK” suffix for 1,000 Tape and Reel option

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL22346

Block Diagram

V

CC

RH3

RW3

WR3

WR2

SCL

SDA

A0

POWER-UP

RL3

RH2

INTERFACE,

CONTROL

AND STATUS

LOGIC

2

I C

INTERFACE

RW2

A1

RL2

RH1

A2

RW1

WR1

WR0

RL1

RH0

NON-

VOLATILE

REGISTERS

SHDN

RW0

RL0

GND

Pin Descriptions

TSSOP PIN

SYMBOL

DESCRIPTION

1

2

RH3

RL3

RW3

A2

“High” terminal of DCP3

“Low” terminal of DCP3

“Wiper” terminal of DCP3

3

2

4

Device address input for the I C interface

2

5

SCL

SDA

GND

RW2

RL2

RH2

RW1

RL1

RH1

A0

Open drain I C interface clock input

2

6

Open drain Serial data I/O for the I C interface

7

Device ground pin

8

“Wiper” terminal of DCP2

“Low” terminal of DCP2

“High” terminal of DCP2

“Wiper” terminal of DCP1

“Low” terminal of DCP1

“High” terminal of DCP1

9

10

11

12

13

14

15

16

17

18

19

20

2

Device address input for the I C interface

2

A1

Device address input for the I C interface

VCC

SHDN

RH0

RL0

RW0

Power supply pin

Shutdown active low input

“High” terminal of DCP0

“Low” terminal of DCP0

“Wiper” terminal of DCP0

FN6177.0

July 28, 2006

2

ISL22346

Absolute Maximum Ratings

Thermal Information

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage at any Digital Interface Pin

Thermal Resistance (Typical, Note 3)

θ_JA(°C/W)

20 Lead TSSOP package . . . . . . . . . . . . . . . . . . . .

90

with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to V +0.3

CC

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V

CC

Recommended Operating Conditions

Voltage at any DCP Pin with Respect to GND. . . . . . . -0.3V to V

CC

Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . .300°C

(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

Temperature Range (Extended Industrial). . . . . . . .-40°C to +125°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

V

I

CC

W

Power Rating of each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW

Wiper Current of each DCP. . . . . . . . . . . . . . . . . . . . . . . . . .±3.0mA

Latchup (Note 4) . . . . . . . . . . . . . . . . . . Class II, Level B @ +125°C

ESD (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5kV

(CDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1kV

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

3. θ_JAis measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

4. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: using a max positive pulse of 6.5V on the SHDN pin, and using

a max negative pulse of -0.8V for all pins.

Analog Specifications Over recommended operating conditions unless otherwise stated.

TYP

SYMBOL

PARAMETER

to R Resistance

TEST CONDITIONS

MIN

(NOTE 5)

MAX

UNIT

kΩ

R

W option

U option

10

50

TOTAL

H

L

kΩ

to R Resistance Tolerance

W and U option

W option

-20

+20

%

H

L

End-to-End Temperature Coefficient

±50

±80

ppm/°C

(Note 19)

U option

ppm/°C

(Note 19)

V

, V

RH RL

V

and V Terminal Voltages

RL

V

and V to GND

RL

0

V

RH

CC

R

Wiper Resistance

V

= 3.3V @ +25°C, wiper current =

70

10/10/25

0.1

200

Ω

W

/R

CC TOTAL

C /C /C

W

Potentiometer Capacitance

Leakage on DCP Pins

pF

µA

H

L

(Note 19)

I

Voltage at pin from GND to V

1

LkgDCP

CC

VOLTAGE DIVIDER MODE (0V @ R i; V

@ R i; measured at R i, unloaded; i = 0, 1, 2, or 3)

L

CC

H

W

INL

(Note 10)

Integral Non-linearity

Differential Non-linearity

Zero-scale Error

Monotonic over all tap positions

-1

1

LSB

(Note 6)

DNL

(Note 9)

Monotonic over all tap positions

-0.5

0.5

LSB

(Note 6)

ZSerror

(Note 7)

W option

0

1

0.5

-1

5

2

0

2

LSB

(Note 6)

U option

FSerror

(Note 8)

Full-scale error

W option

-5

-2

LSB

(Note 6)

U option

-1

V

DCP to DCP Matching

Any two DCPs at same tap position, same

LSB

(Note 6)

MATCH

(Note 11)

voltage at all R terminals, and same voltage

H

at all R terminals

L

TC

Ratiometric Temperature Coefficient

DCP register set to 40 hex

±4

ppm/°C

V

(Note 12)

RESISTOR MODE (Measurements between R i and R i with R i not connected, or between R i and R i with R i not connected. i = 0, 1, 2 or 3)

W

L

H

W

H

L

RINL

(Note 16)

Integral nOn-linearity

DCP register set between 10h and 7Fh;

monotonic over all tap positions

-1

1

MI

(Note 13)

FN6177.0

July 28, 2006

3

ISL22346

Analog Specifications Over recommended operating conditions unless otherwise stated. (Continued)

TYP

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

(NOTE 5)

MAX

UNIT

RDNL

(Note 15)

Differential Non-linearity

DCP register set between 10h and 7Fh;

monotonic over all tap positions

-0.5

0.5

MI

(Note 13)

Roffset

(Note 14)

Offset

W option

0

1

5

2

MI

(Note 13)

U option

0.5

MI

(Note 13)

R

DCP to DCP Matching

Any two DCPs at the same tap position with

the same terminal voltages

-2

MI

(Note 13)

MATCH

(Note 17)

Operating Specifications Over the recommended operating conditions unless otherwise specified.

TYP

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

(NOTE 5)

MAX

UNIT

2

I

V

Supply Current (volatile

f

= 400kHz; SDA = Open; (for I C, active,

0.5

mA

CC1

CC

SCL

read and write states)

write/read)

2

I

V

Supply Current (non-volatile

f

= 400kHz; SDA = Open; (for I C, active,

3

5

7

3

5

3

5

2

4

1

mA

µA

µs

CC2

CC

write/read)

SCL

read and write states)

2

I

V

Current (standby)

V

= +5.5V @ +85°C, I C interface in

SB

CC

standby state

2

V

= +5.5V @ +125°C, I C interface in

CC

standby state

2

V

= +3.6V @ +85°C, I C interface in

CC

standby state

2

V

= +3.6V @ +125°C, I C interface in

CC

standby state

2

I

V

Current (shutdown)

V

= +5.5V @ +85°C, I C interface in

SD

CC

standby state

2

V

= +5.5V @ +125°C, I C interface in

CC

standby state

2

V

= +3.6V @ +85°C, I C interface in

CC

standby state

2

V

= +3.6V @ +125°C, I C interface in

CC

standby state

I

Leakage Current, at Pins A0, A1, A2, Voltage at pin from GND to V

SHDN, SDA, and SCL

-1

LkgDig

CC

t

DCP Wiper Response Time

SCL falling edge of last bit of DCP data byte

to wiper new position

1.5

WRT

(Note 19)

t

DCP Recall Time from Shutdown

From rising edge of SHDN signal to wiper

stored position and RH connection

µs

ShdnRec

(Note 19) Mode

SCL falling edge of last bit of ACR data byte

to wiper stored position and RH connection

µs

Vpor

Power-on Recall Voltage

Ramp Rate

Minimum V

at which memory recall occurs

2.0

0.2

2.6

3

V

CC

VccRamp

V

V/ms

ms

CC

t

Power-up Delay

V

above Vpor, to DCP Initial Value

CC

D

2

Register recall completed, and I C Interface

in standby state

EEPROM SPECIFICATION

EEPROM Endurance

EEPROM Retention

1,000,000

50

Cycles

Years

Temperature T <55°C

FN6177.0

July 28, 2006

4

ISL22346

Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)

TYP

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

(NOTE 5)

MAX

UNIT

t

Non-volatile Write Cycle Time

12

20

ms

WC

(Note 20)

SERIAL INTERFACE SPECS

V

A2, A1, A0, SHDN, SDA, and SCL

Input Buffer LOW Voltage

-0.3

0.3*V

V

IL

CC

V

A2, A1, A0, SHDN, SDA, and SCL

Input Buffer HIGH Voltage

0.7*V

V

+0.3

CC

IH

CC

Hysteresis SDA and SCL Input Buffer Hysteresis

0.05*

V

CC

V

SDA Output Buffer LOW Voltage,

Sinking 4mA

0

0.4

V

OL

Cpin

A2, A1, A0, SHDN, SDA, and SCL Pin

10

pF

(Note 19) Capacitance

SCL Frequency

Pulse Width Suppression Time at SDA Any pulse narrower than the max spec is

f

400

50

kHz

ns

SCL

t

sp

(Note 19) and SCL Inputs

suppressed

t

SCL Falling Edge to SDA Output Data SCL falling edge crossing 30% of V , until

CC

900

ns

AA

Valid

SDA exits the 30% to 70% of V

window

CC

t

Time the Bus Must be Free Before the SDA crossing 70% of V

during a STOP

1300

BUF

CC

condition, to SDA crossing 70% of V

Start of a New Transmission

CC

during the following START condition

t

Clock LOW Time

Measured at the 30% of V

Measured at the 70% of V

crossing

1300

600

ns

LOW

CC

t

Clock HIGH Time

HIGH

t

START Condition Setup Time

SCL rising edge to SDA falling edge; both

crossing 70% of V

600

SU:STA

HD:STA

SU:DAT

CC

From SDA falling edge crossing 30% of V

t

START Condition Hold Time

Input Data Setup Time

600

100

ns

CC

to SCL falling edge crossing 70% of V

CC

From SDA exiting the 30% to 70% of V

CC

window, to SCL rising edge crossing 30% of

V

CC

t

Input Data Hold Time

From SCL rising edge crossing 70% of V

0

ns

HD:DAT

CC

to SDA entering the 30% to 70% of V

window

CC

t

STOP Condition Setup Time

From SCL rising edge crossing 70% of V

to SDA rising edge crossing 30% of V

,

600

1300

0

ns

SU:STO

CC

t

STOP Condition Hold Time for Read, From SDA rising edge to SCL falling edge;

HD:STO

or Volatile Only Write

Output Data Hold Time

both crossing 70% of V

CC

t

From SCL falling edge crossing 30% of V

,

DH

CC

until SDA enters the 30% to 70% of V

window

t

SDA and SCL Rise Time

From 30% to 70% of V

20 +

0.1 * Cb

250

400

ns

R

CC

t

SDA and SCL Fall Time

From 70% to 30% of V

20 +

0.1 * Cb

F

CC

Cb

Capacitive Loading of SDA or SCL

Total on-chip and off-chip

Maximum is determined by t and t

For Cb = 400pF, max is about 2~2.5kΩ

10

1

pF

Rpu

SDA and SCL Bus Pull-up Resistor

Off-chip

kΩ

R

F

For Cb = 40pF, max is about 15~20kΩ

t

A2, A1 and A0 Setup Time

Before START condition

600

ns

SU:A

FN6177.0

July 28, 2006

5

ISL22346

Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)

TYP

SYMBOL

PARAMETER

TEST CONDITIONS

After STOP condition

MIN

(NOTE 5)

MAX

UNIT

t

A2, A1 and A0 Hold Time

600

ns

HD:A

NOTES:

5. Typical values are for T = +25°C and 3.3V supply voltage.

A

6. LSB: [V(R

)

– V(R ) ]/127. V(R

)

and V(R ) are V(R ) for the DCP register set to 7F hex and 00 hex respectively. LSB is the

W 0

W 127

W 0 W 127

W

incremental voltage when changing from one tap to an adjacent tap.

7. ZS error = V(RW) /LSB.

0

8. FS error = [V(RW)

127

– V ]/LSB.

CC

9. DNL = [V(RW) – V(RW) ]/LSB-1, for i = 1 to 127. i is the DCP register setting.

i-1

i

10. INL = [V(RW) – i • LSB – V(RW) ]/LSB for i = 1 to 127.

i

0

11. V

= [V(RWx) – V(RWy) ]/LSB, for i = 1 to 127, x = 0 to 3 and y = 0 to 3.

i i

MATCH

Max(V(RW) ) – Min(V(RW) )

6

10

i

--------------------------------------------------------------------------------------------- ----------------

12. TC

=

×

for i = 16 to 112 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper

voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range.

V

[Max(V(RW) ) + Min(V(RW) )] ⁄ 2 165°C

i

13. MI = |RW

– RW |/127. RW

0

and RW are the measured resistances for the DCP register set to 7F hex and 00 hex respectively.

127 0

127

14. Roffset = RW /MI, when measuring between RW and RL.

0

Roffset = RW

/MI, when measuring between RW and RH.

127

15. RDNL = (RW – RW )/MI - 1, for i = 16 to 127.

i

i-1

16. RINL = [RW – (MI • i) – RW ]/MI, for i = 16 to 127.

i

0

17. R

= (RW – RW )/MI, for i = 1 to 127, x = 0 to 3 and y = 0 to 3.

i,x i,y

MATCH

6

[Max(Ri) – Min(Ri)]

10

--------------------------------------------------------------- ----------------

18.

for i = 16 to 112, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min ( ) is

the minimum value of the resistance over the temperature range.

TC

=

×

R

165°C

[Max(Ri) + Min(Ri)] ⁄ 2

19. This parameter is not 100% tested.

20. t

2

is the time from a valid STOP condition at the end of a Write sequence of I C serial interface, to the end of the self-timed internal non-volatile

WC

write cycle.

SDA vs SCL Timing

t

sp

t

R

F

HIGH

LOW

SCL

t

SU:DAT

t

SU:STO

SU:STA

HD:DAT

t

HD:STA

SDA

(INPUT TIMING)

t

BUF

AA

DH

SDA

(OUTPUT TIMING)

A0, A1, and A2 Pin Timing

STOP

START

SCL

CLK 1

SDA

t

HD:A

SU:A

A0, A1, OR A2

FN6177.0

July 28, 2006

6

ISL22346

Typical Performance Curves

VCC

100

1.4

1.2

1

Vcc = 3.3V, T = 125ºC

90

80

70

60

50

40

30

_T=125ºC

VCC

0.8

0.6

0.4

0.2

0

Vcc = 3.3V, T = -40ºC

Vcc = 3.3V, T = 20ºC

20

10

0

_T=25ºC

0

20

40

60

80

100

120

2.7

3.2

3.7

4.2

4.7

5.2

TAP POSITION (DECIMAL)

Vcc, V

FIGURE 1. WIPER RESISTANCE vs TAP POSITION

[ I(RW) = V /R ] FOR 10kΩ (W)

FIGURE 2. STANDBY I

vs V

CC

CC TOTAL

0.2

0.1

0

0.2

0.1

0

T = 25ºC

Vcc = 2.7V

T = 25ºC

Vcc =2.7V

-0.1

-0.2

-0.1

-0.2

Vcc = 5.5V

20 40

0

60

80

100

120

0

20

40

60

80

100

120

TAP POSITION(DECIMAL)

TAP POSITION (DECIMAL)

FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER

FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER

MODE FOR 10kΩ (W)

0.00

1.30

10k

1.10

0.90

0.70

-0.30

Vcc = 2.7V

50k

10k

Vcc = 5.5V

-0.60

-0.90

-1.20

-1.50

Vcc =2.7V

0.50

0.30

Vcc =5.5V

0.10

50k

-0.10

-0.30

-40 -20

0

20

40

60

80

100 120

-40

-20

0

20

40

60

80

100 120

TEMPERATURE(ºC)

TEMPERATURE (ºC)

FIGURE 5. ZSerror vs TEMPERATURE

FIGURE 6. FSerror vs TEMPERATURE

FN6177.0

July 28, 2006

7

ISL22346

Typical Performance Curves (Continued)

0.4

0.2

0

0.4

T = 25ºC

T = 25º C

0.2

0

Vcc = 5.5V

-0.2

-0.4

-0.6

Vcc =5.5V

Vcc =2.7V

Vcc = 2.7V

-0.4

-0.6

16

36

56

76

96

116

16

36

56

76

96

116

TAPPOSITION(DECIMAL)

TAP POSITION (DECIMAL)

FIGURE 8. INL vs TAP POSITION IN Rheostat MODE FOR

FIGURE 7. DNL vs TAP POSITION IN Rheostat MODE FOR

10kΩ (W)

1.00

105

50k

90

Vcc = 2.7V

10k

0.50

0.00

75

60

45

30

-0.50

50k

Vcc = 5.5V

10k

15

0

-1.00

-40

-20

0

20

40

60

80

100 120

16

36

56

76

96

TAP POSITION (DECIMAL)

TEMPERATURE(ºC)

FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm

FIGURE 9. END TO END R

TOTAL

% CHANGE vs

TEMPERATURE

OUTPUT

INPUT

300

250

200

150

100

50

10k

50k

Wiper at Mid Point (position 40h)

Rtotal = 9.5kΩ

0

16

36

56

76

96

TAP POSITION(DECIMAL)

FIGURE 12. FREQUENCY RESPONSE (2.6MHz)

FIGURE 11. TC FOR Rheostat MODE IN ppm

FN6177.0

July 28, 2006

8

ISL22346

Typical Performance Curves (Continued)

Wiper Mid Point Movement

from 3Fh to 40h

FIGURE 13. MIDSCALE GLITCH, CODE 3Fh TO 40h

FIGURE 14. LARGE SIGNAL SETTLING TIME

Bus Interface Pins

Serial Data Input/Output (SDA)

Pin Descriptions

Potentiometers Pins

2

The SDA is a bidirectional serial data input/output pin for I C

interface. It receives device address, operation code, wiper

address and data from an I C external master device at the

rising edge of the serial clock SCL, and it shifts out data after

each falling edge of the serial clock.

RHi and RLi (i = 0, 1, 2 or 3)

2

The high (RHi) and low (RLi) terminals of the ISL22346 are

equivalent to the fixed terminals of a mechanical

potentiometer. RHi and RLi are referenced to the relative

position of the wiper and not the voltage potential on the

terminals. With WRi set to 127 decimal, the wiper will be

closest to RHi, and with the WRi set to 0, the wiper is closest

to RLi.

SDA requires an external pull-up resistor, since it is an open

drain input/output.

Serial Clock (SCL)

2

RWi (i = 0, 1, 2 or 3)

This is the serial clock input of the I C serial interface. SCL

requires an external pull-up resistor, since it is an open drain

input.

RWi is the wiper terminal and is equivalent to the movable

terminal of a mechanical potentiometer. The position of the

wiper within the array is determined by the WRi register.

Device Address (A2 - A0)

SHDN

The address inputs are used to set the least significant 3 bits

of the 7-bit I C interface slave address. A match in the slave

2

The SHDN pin forces the resistor to end-to-end open circuit

condition on RHi and shorts RWi to RLi. When SHDN is

returned to logic high, the previous latch settings put RWi at

the same resistance setting prior to shutdown. This pin is

address serial data stream must match with the Address

input pins in order to initiate communication with the

ISL22346. A maximum of 8 ISL22346 devices may occupy

2

the I C serial bus.

logically OR’d with SHDN bit in ACR register. I C interface is

still available in shutdown mode and all registers are

accessible. This pin must remain HIGH for normal operation.

Principles of Operation

The ISL22346 is an integrated circuit incorporating four

DCPs with their associated registers, non-volatile memory

and an I C serial interface providing direct communication

RH

2

between a host and the potentiometers and memory. The

resistor arrays are comprised of individual resistors

connected in series. At either end of the array and between

each resistor is an electronic switch that transfers the

potential at that point to the wiper.

RW

RL

The electronic switches on the device operate in a “make

before break” mode when the wiper changes tap positions.

FIGURE 15. DCP CONNECTION IN SHUTDOWN MODE

FN6177.0

July 28, 2006

9

ISL22346

TABLE 1. MEMORY MAP

NON-VOLATILE

When the device is powered down, the last value stored in

IVRi will be maintained in the non-volatile memory. When

power is restored, the contents of the IVRi are recalled and

loaded into the corresponding WRi to set the wipers to the

initial value.

ADDRESS

VOLATILE

3

2

1

0

IVR3

IVR2

IVR1

IVR0

WR3

WR2

WR1

WR0

DCP Description

Each DCP is implemented with a combination of resistor

elements and CMOS switches. The physical ends of each

DCP are equivalent to the fixed terminals of a mechanical

potentiometer (RH and RL pins). The RW pin of each DCP is

connected to intermediate nodes, and is equivalent to the

wiper terminal of a mechanical potentiometer. The position

of the wiper terminal within the DCP is controlled by volatile

Wiper Register (WR). Each DCP has its own WR. When the

WR of a DCP contains all zeroes (WR[6:0]= 00h), its wiper

terminal (RW) is closest to its “Low” terminal (RL). When the

WR register of a DCP contains all ones (WR[6:0]= 7Fh), its

wiper terminal (RW) is closest to its “High” terminal (RH). As

the value of the WR increases from all zeroes (0) to all ones

(127 decimal), the wiper moves monotonically from the

position closest to RL to the closest to RH. At the same time,

the resistance between RW and RL increases monotonically,

while the resistance between RH and RW decreases

monotonically.

The non-volatile IVRi and volatile WRi registers are

accessible with the same address.

The Access Control Register (ACR) contains information

and control bits described below in Table 2. The VOL bit at

access control register (ACR[7]) determines whether the

access is to wiper registers WRi or initial value registers

IVRi.

TABLE 2. ACCESS CONTROL REGISTER (ACR)

VOL

SHDN

WIP

0

If VOL bit is 0, the non-volatile IVRi registers are accessible.

If VOL bit is 1, only the volatile WRi are accessible. Note,

value is written to IVRi register also is written to the

corresponding WRi. The default value of this bit is 0.

The SHDN bit (ACR[6]) disables or enables Shutdown

mode. This bit is logically OR’d with SHDN pin. When this bit

is 0, all DCPs are in Shutdown mode. Default value of SHDN

bit is 1.

While the ISL22346 is being powered up, all four WRs are

reset to 40h (64 decimal), which locates RW roughly at the

center between RL and RH. After the power supply voltage

becomes large enough for reliable non-volatile memory

reading, all WRs will be reload with the value stored in

corresponding non-volatile Initial Value Registers (IVRs).

The WIP bit (ACR[5]) is read only bit. It indicates that

non-volatile write operation is in progress. It is impossible to

write to the WRi or ACR while WIP bit is 1.

2

I C Serial Interface

2

The ISL22346 supports an I C bidirectional bus oriented

2

The WRs can be read or written to directly using the I C

protocol. The protocol defines any device that sends data

onto the bus as a transmitter and the receiving device as the

receiver. The device controlling the transfer is a master and

the device being controlled is the slave. The master always

initiates data transfers and provides the clock for both

transmit and receive operations. Therefore, the ISL22346

operates as a slave device in all applications.

serial interface as described in the following sections. The

I C interface Address Byte has to be set to 00h, 01h, 02h or

03h to access the WR of DCP0, DCP1, DCP2 or DCP3

respectively.

2

Memory Description

The ISL22346 contains seven non-volatile and five volatile

8-bit registers. The memory map of ISL22346 is on Table 1.

The four non-volatile registers (IVRi) at address 0, 1, 2 and 3

contain initial wiper value and volatile registers (WRi) contain

current wiper position. In addition, three non-volatile General

Purpose registers from address 4 to address 6 are available.

2

All communication over the I C interface is conducted by

sending the MSB of each byte of data first.

Protocol Conventions

Data states on the SDA line must change only during SCL

LOW periods. SDA state changes during SCL HIGH are

reserved for indicating START and STOP conditions (See

Figure 16). On power-up of the ISL22346 the SDA pin is in

the input mode.

TABLE 1. MEMORY MAP

ADDRESS

NON-VOLATILE

VOLATILE

8

7

—

ACR

Reserved

2

All I C interface operations must begin with a START

6

5

4

General Purpose

Not Available

condition, which is a HIGH to LOW transition of SDA while

SCL is HIGH. The ISL22346 continuously monitors the SDA

and SCL lines for the START condition and does not

respond to any command until this condition is met (See

Figure 16). A START condition is ignored during the

power-up of the device.

FN6177.0

July 28, 2006

10

ISL22346

2

All I C interface operations must be terminated by a STOP

Byte of a write operation. The master must respond with an

condition, which is a LOW to HIGH transition of SDA while

SCL is HIGH (See Figure 16). A STOP condition at the end

of a read operation, or at the end of a write operation places

the device in its standby mode.

ACK after receiving a Data Byte of a read operation.

A valid Identification Byte contains 1010 as the four MSBs,

and the following three bits matching the logic values

present at pins A2, A1, and A0. The LSB is the Read/Write

bit. Its value is “1” for a Read operation, and “0” for a Write

operation (See Table 3).

An ACK, Acknowledge, is a software convention used to

indicate a successful data transfer. The transmitting device,

either master or slave, releases the SDA bus after

transmitting eight bits. During the ninth clock cycle, the

receiver pulls the SDA line LOW to acknowledge the

reception of the eight bits of data (See Figure 17).

TABLE 3. IDENTIFICATION BYTE FORMAT

Logic values at pins A2, A1, and A0 respectively

1

0

1

0

A2

A1

A0

R/W

The ISL22346 responds with an ACK after recognition of a

START condition followed by a valid Identification Byte, and

once again after successful receipt of an Address Byte. The

ISL22346 also responds with an ACK after receiving a Data

(MSB)

(LSB)

SCL

SDA

START

DATA

STOP

STABLE

CHANGE STABLE

FIGURE 16. VALID DATA CHANGES, START, AND STOP CONDITIONS

SCL FROM

MASTER

1

8

9

SDA OUTPUT FROM

TRANSMITTER

HIGH IMPEDANCE

SDA OUTPUT FROM

RECEIVER

START

ACK

FIGURE 17. ACKNOWLEDGE RESPONSE FROM RECEIVER

WRITE

S

SIGNALS FROM

THE MASTER

T

A

R

T

S

T

O

P

IDENTIFICATION

BYTE

ADDRESS

BYTE

DATA

BYTE

SIGNAL AT SDA

1 0 1 0

A2A1A0 0

0 0 0 0

SIGNALS FROM

THE SLAVE

A

C

K

A

C

K

A

C

K

FIGURE 18. BYTE WRITE SEQUENCE

FN6177.0

July 28, 2006

11

ISL22346

S

T

A

R

T

S

T

A

R

T

SIGNALS

FROM THE

MASTER

S

T

O

P

A

C

K

A

C

K

IDENTIFICATION

BYTE WITH

R/W=0

IDENTIFICATION

BYTE WITH

R/W=1

A

C

K

ADDRESS

BYTE

SIGNAL AT SDA

1 0 1 0 A2A1A0 0

0 0 0 0

1 0 1 0 A2A1A0 1

A

C

K

A

C

K

A

C

K

SIGNALS FROM

THE SLAVE

FIRST READ

DATA BYTE

LAST READ

DATA BYTE

FIGURE 19. READ SEQUENCE

Write Operation

Read Operation

A Read operation consist of a three byte instruction followed

by one or more Data Bytes (See Figure 19). The master

initiates the operation issuing the following sequence: a

START, the Identification byte with the R/W bit set to “0”, an

Address Byte, a second START, and a second Identification

byte with the R/W bit set to “1”. After each of the three bytes,

the ISL22346 responds with an ACK. Then the ISL22346

transmits Data Bytes as long as the master responds with an

ACK during the SCL cycle following the eighth bit of each

byte. The master terminates the read operation (issuing a

ACK and a STOP condition) following the last bit of the last

Data Byte (See Figure 19).

A Write operation requires a START condition, followed by a

valid Identification Byte, a valid Address Byte, a Data Byte,

and a STOP condition. After each of the three bytes, the

ISL22346 responds with an ACK. At this time, the device

enters its standby state (See Figure 18). Device can receive

more than one byte of data by auto incrementing the

address after each received byte. Note after reaching the

address 08h, the internal pointer “rolls over” to address 00h.

The non-volatile write cycle starts after STOP condition is

determined and it requires up to 20ms delay for the next

non-volatile write. Thus, non-volatile registers must be

written individually.

The Data Bytes are from the registers indicated by an

internal pointer. This pointer initial value is determined by the

Address Byte in the Read operation instruction, and

increments by one during transmission of each Data Byte.

After reaching the memory location 08h, the pointer “rolls

over” to 00h, and the device continues to output data for

each ACK received.

In order to read back the non-volatile IVR, it is recommended

that the application reads the ACR first to verify the WIP bit

is 0. If the WIP bit (ACR[5]) is not 0, the host should repeat

its reading sequence again.

FN6177.0

July 28, 2006

12

ISL22346

Thin Shrink Small Outline Plastic Packages (TSSOP)

M20.173

N

20 LEAD THIN SHRINK SMALL OUTLINE PLASTIC

PACKAGE

INDEX

AREA

0.25(0.010)

M

B M

E

E1

-B-

INCHES

MIN

MILLIMETERS

GAUGE

PLANE

SYMBOL

MAX

0.047

0.006

0.051

0.0118

0.0079

0.260

0.177

MIN

-

MAX

1.20

0.15

1.05

0.30

0.20

6.60

4.50

NOTES

A

A1

A2

b

-

1

2

3

0.002

0.031

0.0075

0.0035

0.252

0.169

0.05

0.80

0.19

0.09

6.40

4.30

-

L

0.25

0.010

-

0.05(0.002)

SEATING PLANE

A

9

-A-

D

c

-

D

3

-C-

α

E1

e

4

A2

e

A1

0.026 BSC

0.65 BSC

-

c

b

0.10(0.004)

E

0.246

0.256

6.25

0.45

6.50

0.75

-

0.10(0.004) M

C

A M B S

L

0.0177

0.0295

6

N

20

7

NOTES:

o

0

8

0

8

-

α

1. These package dimensions are within allowable dimensions of

JEDEC MO-153-AC, Issue E.

Rev. 1 6/98

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm

(0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable dambar

protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-

sion at maximum material condition. Minimum space between protru-

sion and adjacent lead is 0.07mm (0.0027 inch).

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact. (Angles in degrees)

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6177.0

July 28, 2006

13


型号：	ISL22346UFV20Z
厂家：	Intersil
描述：	Quad Digitally Controlled Potentiometers 四通道数字电位器电位器
文件：	总13页 (文件大小：485K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL22346UFV20Z [INTERSIL]

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