ISL22416WFRT10Z_技术文档

ISL22416

®

Single Digitally Controlled Potentiometer (XDCP™)

Data Sheet

®

September 9, 2009

FN6227.2

Low Noise, Low Power, SPI Bus, 128 Taps

Features

The ISL22416 integrates a single digitally controlled

potentiometer (DCP) and non-volatile memory on a

monolithic CMOS integrated circuit.

• 128 resistor taps

• SPI serial interface

• Non-volatile storage of wiper position

The digitally controlled potentiometer is implemented with a

combination of resistor elements and CMOS switches. The

position of the wiper is controlled by the user through the SPI

serial interface. The potentiometer has an associated

volatile Wiper Register (WR) and a non-volatile Initial Value

Register (IVR) that can be directly written to and read by the

user. The contents of the WR controls the position of the

wiper. At power-up, the device recalls the contents of the

DCP’s IVR to the WR.

• Wiper resistance: 70Ω typical @ V

• Shutdown mode

= 3.3V

CC

• Shutdown current 5µA max

• Power supply: 2.7V to 5.5V

• 50kΩ or 10kΩ total resistance

• High reliability

- Endurance: 1,000,000 data changes per bit per register

The DCP can be used as a three-terminal potentiometer or

as a two-terminal variable resistor in a wide variety of

applications including control, parameter adjustments, and

signal processing.

- Register data retention: 50 years @ T ≤ +55°C

• 10 Ld MSOP and 10 Ld TDFN package

• Pb-free (RoHS compliant)

Pinout

ISL22416

(10 LD MSOP)

TOP VIEW

ISL22416

(10 LD TDFN)

TOP VIEW

O

10

1

2

3

4

5

10

SCK

SDO

SDI

VCC

SCK

SDO

SDI

VCC

RH

1

2

3

4

5

9

8

RH

9

RW

RL

8

7

6

CS

RL

SHDN

GND

SHDN

GND

6

Ordering Information

PART NUMBER

(Note)

RESISTANCE OPTION

TEMP. RANGE

(°C)

PACKAGE

(Pb-free)

PART MARKING

416UZ

(kΩ)

PKG. DWG. #

M10.118

ISL22416UFU10Z*

ISL22416UFRT10Z*

ISL22416WFU10Z*

ISL22416WFRT10Z*

50

10

-40 to +125

10 Ld MSOP

416U

10 Ld 3x3 TDFN

10 Ld MSOP

L10.3x3B

M10.118

416WZ

416W

10 Ld 3x3 TDFN

L10.3x3B

*Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%

matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1

1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

ISL22416

Block Diagram

V

CC

SCK

SDO

SDI

POWER-UP

INTERFACE,

CONTROL

AND

RH

SPI

INTERFACE

STATUS

LOGIC

CS

RW

RL

WR

IVR

NON-VOLATILE

REGISTER

SHDN

GND

Pin Descriptions

MSOP/TDFN PIN NUMBER

SYMBOL

SCK

SDO

SDI

DESCRIPTION

1

2

SPI interface clock input

Push-pull/Open Drain Data Output of the SPI serial interface

Data Input of the SPI serial interface

Chip Select active low input

Shutdown active low input

Device ground pin

3

4

CS

5

SHDN

GND

RL

6

7

“Low” terminal of DCP

8

RW

“Wiper” terminal of DCP

9

RH

“High” terminal of DCP

10

V

Power supply pin

CC

FN6227.2

September 9, 2009

2

ISL22416

Absolute Maximum Ratings

Thermal Information

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Voltage at any Digital Interface Pin

Thermal Resistance (Typical)

θ

(°C/W)

θ

(°C/W)

JC

JA

10 Lead MSOP (Note 2). . . . . . . . . . . .

10 Lead TDFN (Notes 2, 3) . . . . . . . . .

Maximum Junction Temperature (Plastic Package). . . . . . . . +150°C

Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

162

74

N/A

7

with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to V +0.3

CC

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V

CC

Voltage at any DCP pin with Respect to GND . . . . . . . -0.3V to V

CC

(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

I

W

Latchup (Note 1) . . . . . . . . . . . . . . . . . . Class II, Level B @ +125°C

ESD

Recommended Operating Conditions

Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5kV

Charge Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1kV

Temperature Range (Extended Industrial). . . . . . . .-40°C to +125°C

Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

CC

Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±3.0mA

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTES:

1. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: using a max positive pulse of 6.5V on the SHDN pin, and using

a max negative pulse of -1V for all pins.

2. θ is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See

JA

Tech Brief TB379.

3. For θ , the “case temp” location is the center of the exposed metal pad on the package underside.

JC

Analog Specifications Over recommended operating conditions, unless otherwise stated. Parameters with MIN and/or MAX limits are

100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not

production tested.

TYP

SYMBOL

PARAMETER

to R Resistance

TEST CONDITIONS

MIN

(Note 4)

MAX

UNIT

kΩ

R

W option

U option

10

TOTAL

H

L

50

kΩ

to R Resistance Tolerance

W and U option

W option

-20

+20

%

H

L

End-to-End Temperature Coefficient

±50

±80

70

ppm/°C

(Note 18)

U option

ppm/°C

(Note 18)

R

Wiper Resistance

V

= 3.3V, wiper current = V /R

CC TOTAL

200

Ω

V

W

CC

RH

V

, V

RH RL

V

and V Terminal Voltages

RL

and V to GND

RL

0

V

CC

RH

C /C /C

W

(Note 18)

Potentiometer Capacitance

10/10/25

0.1

pF

H

L

I

Leakage on DCP Pins

Voltage at pin from GND to V

1

µA

LkgDCP

CC

VOLTAGE DIVIDER MODE (0V @ R ; V

CC

@ R ; measured at R , unloaded)

H W

L

INL

(Note 9)

Integral Non-linearity

Differential Non-linearity

Zero-scale Error

Monotonic over all tap positions, W and U

option

-1

LSB

(Note 5)

DNL

(Note 8)

Monotonic over all tap positions, W and U

option

-0.5

0.5

LSB

(Note 5)

ZSerror

(Note 6)

W option

U option

W option

U option

0

1

0.5

-1

5

2

0

LSB

(Note 5)

FSerror

(Note 7)

Full-scale Error

-5

-2

LSB

(Note 5)

-1

TC

Ratiometric Temperature Coefficient

DCP register set to 40 hex for W and U

option

±4

ppm/°C

V

(Note 10, 18)

FN6227.2

September 9, 2009

3

ISL22416

Analog Specifications Over recommended operating conditions, unless otherwise stated. Parameters with MIN and/or MAX limits are

100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not

production tested. (Continued)

TYP

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

(Note 4)

MAX

UNIT

RESISTOR MODE (Measurements between R and R with R not connected, or between R and R with R not connected)

W

L

H

W

H

L

RINL

(Note 14)

Integral Non-linearity

DCP register set between 10 hex and 7F

hex; monotonic over all tap positions;

W and U option

-1

1

MI

(Note 11)

RDNL

(Note 13)

Differential Non-linearity

W option

U option

W option

U option

1

0.5

5

MI

(Note 11)

-0.5

0

MI

(Note 11)

Roffset

(Note 12)

Offset

1

MI

(Note 11)

0

0.5

2

MI

(Note 11)

Operating Specifications Over the recommended operating conditions, unless otherwise specified. Parameters with MIN and/or MAX

limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization

and are not production tested.

TYP

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

(Note 4)

MAX

UNIT

I

V

Supply Current (Volatile

f = 5MHz; (for SPI Active, Read and

SCK

0.5

mA

CC1

CC

Write/Read)

Volatile Write states only)

I

V

Supply Current (Non-volatile

f

= 5MHz; (for SPI Active, Read and

3

5

7

3

5

3

5

2

4

1

mA

µA

µs

CC2

CC

Write/Read)

SCK

Non-volatile Write states only)

I

V

Current (Standby)

V

= +5.5V @ +85°C, SPI interface in

SB

CC

standby state

V

= +5.5V @ +125°C, SPI interface in

CC

standby state

V

= +3.6V @ +85°C, SPI interface in

CC

standby state

V

= +3.6V @ +125°C, SPI interface in

CC

standby state

I

V

Current (Shutdown)

V

= +5.5V @ +85°C, SPI interface in

SD

CC

standby state

V

= +5.5V @ +125°C, SPI interface in

CC

standby state

V

= +3.6V @ +85°C, SPI interface in

CC

standby state

V

= +3.6V @ +125°C, SPI interface in

CC

standby state

I

Leakage Current, at Pins SHDN, SCK, Voltage at pin from GND to V

SDI, SDO and CS

-1

LkgDig

CC,

SDO is inactive

t

Wiper Response Time

Wiper Response Time after SPI write to WR

register

1.5

WRT

(Note 18)

t

DCP Recall Time from Shutdown

From rising edge of SHDN signal to wiper

stored position and RH connection

µs

ShdnRec

(Note 18) Mode

SCK rising edge of last bit of ACR data byte

to wiper stored position and RH connection

µs

V

Power-on Recall Voltage

Ramp Rate

Minimum V

CC

at which memory recall occurs

2.0

0.2

2.6

V

POR

V

Ramp

V

V/ms

CC

FN6227.2

September 9, 2009

4

ISL22416

Operating Specifications Over the recommended operating conditions, unless otherwise specified. Parameters with MIN and/or MAX

limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization

and are not production tested. (Continued)

TYP

SYMBOL

PARAMETER

Power-up Delay

TEST CONDITIONS

above V , to DCP Initial Value

MIN

(Note 4)

MAX

UNIT

t

V

3

ms

D

CC

POR

Register recall completed, and SPI Interface

in standby state

EEPROM SPECIFICATION

EEPROM Endurance

1,000,000

50

Cycles

Years

ms

EEPROM Retention

Temperature T ≤ +55°C

t

Non-volatile Write Cycle Time

12

20

WC

(Note 16)

SERIAL INTERFACE SPECIFICATIONS

V

SHDN, SCK, SDI, and CS Input Buffer

LOW Voltage

-0.3

0.3*V

CC

V

IL

V

SHDN, SCK, SDI, and CS Input Buffer

HIGH Voltage

0.7*V

V

+ 0.3

CC

IH

CC

Hysteresis SHDN, SCK, SDI, and CS Input Buffer

Hysteresis

0.05*

V

CC

V

SDO Output Buffer LOW Voltage

SDO Pull-up Resistor Off-chip

I

= 4mA

0

0.4

V

OL

R

Maximum is determined by t

and t with

FO

2

10

5

kΩ

pu

RO

maximum bus load Cb = 30pF, f

(Note 17)

= 5MHz

SCK

Cpin

SHDN, SCK, SDI, SDO and CS Pin

pF

(Note 18) Capacitance

f

SPI Frequency

MHz

ns

µs

SCK

t

SPI Clock Cycle Time

SPI Clock High Time

200

100

250

50

CYC

t

WH

t

SPI Clock Low Time

WL

t

Lead Time

LEAD

t

Lag Time

LAG

t

SDI, SCK and CS Input Setup Time

SDI, SCK and CS Input Hold Time

SDI, SCK and CS Input Rise Time

SDI, SCK and CS Input Fall Time

SDO Output Disable Time

SDO Output Valid Time

SDO Output Hold Time

SDO Output Rise Time

SDO Output Fall Time

CS Deselect Time

SU

t

50

H

t

10

RI

t

10

20

FI

t

0

100

350

DIS

t

V

t

0

2

HO

RO

t

R

= 2k, Cbus = 30pF

60

pu

t

R

pu

FO

CS

NOTES:

4. Typical values are for T = +25°C and 3.3V supply voltage.

A

5. LSB: [V(R

)

– V(R ) ]/127. V(R

)

and V(R ) are V(R ) for the DCP register set to 7F hex and 00 hex respectively. LSB is the

W 0

W 127

W 0 W 127

W

incremental voltage when changing from one tap to an adjacent tap.

6. ZS error = V(RW) /LSB.

0

7. FS error = [V(RW)

127

– V ]/LSB.

CC

FN6227.2

September 9, 2009

5

ISL22416

NOTES: (Continued)

8. DNL = [V(RW) – V(RW) ]/LSB-1, for i = 1 to 127. i is the DCP register setting.

i

i-1

9. INL = [V(RW) – (i • LSB) – V(RW) ]/LSB for i = 1 to 127

i

0

Max(V(RW) ) – Min(V(RW) )

6

10

i

10.

--------------------------------------------------------------------------------------------- -------------------- for i = 16 to 127 decimal, T = -40°C to 125°C. Max( ) is the maximum value of the wiper

TC

=

×

V

[Max(V(RW) ) + Min(V(RW) )] ⁄ 2 +165°C

i

voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range.

and RW are the measured resistances for the DCP register set to 7F hex and

11. MI = |RW

– RW |/127. MI is a minimum increment. RW

127

0

00 hex respectively.

12. Roffset = RW /MI, when measuring between RW and RL.

0

Roffset = RW

/MI, when measuring between RW and RH.

127

13. RDNL = (RW – RW )/MI -1, for i = 1 to 127.

i-1

i

14. RINL = [RW – (MI • i) – RW ]/MI, for i = 1 to 127.

i

0

6

[Max(Ri) – Min(Ri)]

10

15.

for i = 16 to 127, T = -40°C to 125°C. Max( ) is the maximum value of the resistance and Min ( ) is

the minimum value of the resistance over the temperature range.

--------------------------------------------------------------- ----------------

TC

=

×

R

165°C

[Max(Ri) + Min(Ri)] ⁄ 2

16. t

is the time from the end of a Write sequence of SPI serial interface, to the end of the self-timed internal non-volatile write cycle.

WC

17. R is specified for the highest data rate transfer for the device. Higher value pull-up can be used at lower data rates.

pu

18. Limits should be considered typical and are not production tested.

Timing Diagrams

Input Timing

t

CS

t

LAG

LEAD

t

CYC

...

SCK

SDI

t

RI

FI

t

WL

SU

H

WH

...

MSB

LSB

HIGH IMPEDANCE

SDO

Output Timing

CS

SCK

SDO

...

t

DIS

V

HO

MSB

LSB

SDI

ADDR

FN6227.2

September 9, 2009

6

ISL22416

XDCP Timing (for All Load Instructions)

CS

t

WC

SCK

...

t

WRT

MSB

LSB

SDI

V

W

HIGH IMPEDANCE

SDO

Typical Performance Curves

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

100

V

CC

= 3.3V, T = +125°C

90

80

70

60

50

40

30

20

10

0

T = +125°C

T = +25°C

V

= 3.3V, T = -40°C

V

CC

= 3.3V, T = +20°C

CC

2.7

3.2

3.7

4.2

(V)

4.7

CC

5.2

0

20

40

60

80

100

120

TAP POSITION (DECIMAL)

V

CC

FIGURE 1. WIPER RESISTANCE vs TAP POSITION

[ I(RW) = V /R ] FOR 10kΩ (W)

FIGURE 2. STANDBY I

vs V

CC

CC TOTAL

0.2

0.1

0

0.2

0.1

0

T = +25°C

V

= 2.7V

CC

V

= 2.7V

CC

-0.1

-0.2

-0.1

-0.2

V

= 5.5V

40

V

= 5.5V

CC

0

20

40

60

80

100

120

0

20

60

80

100

120

TAP POSITION (DECIMAL)

FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER

FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER

MODE FOR 10kΩ (W)

FN6227.2

September 9, 2009

7

ISL22416

Typical Performance Curves (Continued)

1.3

10k

1.1

0.0

-0.3

-0.6

-0.9

-1.2

-1.5

V

= 2.7V

CC

0.9

0.7

V

= 5.5V

CC

50k

V

= 2.7V

CC

0.5

0.3

V

= 5.5V

CC

10k

40

0.1

50k

-0.1

-0.3

-40

-20

0

20

40

60

80

100

120

-40

-20

0

20

60

80

100

120

TEMPERATURE (°C)

TEMPERATURE (ºC)

FIGURE 5. ZS

vs TEMPERATURE

FIGURE 6. FS

vs TEMPERATURE

ERROR

0.4

0.2

0

0.4

0.2

0

T = +25°C

V

= 5.5V

V

= 5.5V

CC

-0.2

-0.4

-0.6

-0.2

-0.4

-0.6

V

= 2.7V

CC

V

= 2.7V

CC

16

36

56

76

96

116

16

36

56

76

96

116

TAP POSITION (DECIMAL)

FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR

FIGURE 8. INL vs TAP POSITION IN RHEOSTAT MODE FOR

10kΩ (W)

1.0

0.5

105

90

75

60

45

V

= 2.7V

CC

50k

0.0

-0.5

-1.0

V

= 5.5V

CC

10k

50k

30

15

0

10k

16

36

56

76

96

-40

-20

0

20

40

60

80

100

120

TEMPERATURE (ºC)

TAP POSITION (DECIMAL)

FIGURE 9. END TO END R

% CHANGE vs

FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm

TOTAL

TEMPERATURE

FN6227.2

September 9, 2009

8

ISL22416

Typical Performance Curves (Continued)

OUTPUT

INPUT

300

250

200

150

100

50k

10k

WIPER AT MID POINT (POSITION 40h)

= 9.5kΩ

R

TOTAL

50

0

16

36

56

76

96

TAP POSITION (DECIMAL)

FIGURE 11. TC FOR RHEOSTAT MODE IN ppm

FIGURE 12. FREQUENCY RESPONSE (2.6MHz)

SCL

SIGNAL AT WIPER

(WIPER UNLOADED)

SIGNAL AT WIPER

(WIPER UNLOADED MOVEMENT

FROM 7Fh TO 00h)

WIPER MID POINT MOVEMENT

FROM 3Fh TO 40h

FIGURE 13. MIDSCALE GLITCH, CODE 3Fh TO 40h

FIGURE 14. LARGE SIGNAL SETTLING TIME

SHDN

Pin Description

Potentiometer Pins

RH AND RL

The SHDN pin forces the resistor to end-to-end open circuit

condition on RH and shorts RW to RL. When SHDN is

returned to logic high, the previous latch settings put RW at

the same resistance setting prior to shutdown. This pin is

logically ANDed with SHDN bit in ACR register. SPI interface

is still available in shutdown mode and all registers are

accessible. This pin must remain HIGH for normal operation.

The high (RH) and low (RL) terminals of the ISL22416 are

equivalent to the fixed terminals of a mechanical

potentiometer. RH and RL are referenced to the relative

position of the wiper and not the voltage potential on the

terminals. With WR set to 127 decimal, the wiper will be

closest to RH, and with the WR set to 0, the wiper is closest

to RL.

RH

RW

RW is the wiper terminal and is equivalent to the movable

terminal of a mechanical potentiometer. The position of the

wiper within the array is determined by the WR register.

RL

FIGURE 15. DCP CONNECTION IN SHUTDOWN MODE

FN6227.2

September 9, 2009

9

ISL22416

(RW) is closest to its “High” terminal (RH). As the value of the

Bus Interface Pins

WR increases from all zeroes (0) to all ones (127 decimal),

the wiper moves monotonically from the position closest to RL

to the closest to RH. At the same time, the resistance between

RW and RL increases monotonically, while the resistance

between RH and RW decreases monotonically.

SERIAL CLOCK (SCK)

This is the serial clock input of the SPI serial interface.

SERIAL DATA OUTPUT (SDO)

The SDO is an open drain serial data output pin. During a

read cycle, the data bits are shifted out at the falling edge of

the serial clock SCK, while the CS input is low.

While the ISL22416 is being powered up, the WR is reset to

40h (64 decimal), which locates RW roughly at the center

between RL and RH. After the power supply voltage

becomes large enough for reliable non-volatile memory

reading, the WR will be reload with the value stored in a

non-volatile Initial Value Register (IVR).

SDO requires an external pull-up resistor for proper

operation.

SERIAL DATA INPUT (SDI)

The SDI is the serial data input pin for the SPI interface. It

receives device address, operation code, wiper address and

data from the SPI external host device. The data bits are

shifted in at the rising edge of the serial clock SCK, while the

CS input is low.

The WR and IVR can be read or written to directly using the

SPI serial interface as described in the following sections.

Memory Description

The ISL22416 contains one non-volatile 7-bit register, known

as the Initial Value Register (IVR), volatile 7-bit Wiper Register

(WR), and volatile 8-bit Access Control Register (ACR). The

memory map is shown in Table 1. The non-volatile register

(IVR) at address 0, contain initial wiper position and volatile

registers (WR) contain current wiper position.

CHIP SELECT (CS)

CS LOW enables the ISL22416, placing it in the active

power mode. A HIGH to LOW transition on CS is required

prior to the start of any operation after power up. When CS is

HIGH, the ISL22416 is deselected and the SDO pin is at

high impedance, and (unless an internal write cycle is

underway) the device will be in the standby state.

TABLE 1. MEMORY MAP

ADDRESS

NON-VOLATILE

VOLATILE

2

1

0

—

ACR

Principles of Operation

Reserved

The ISL22416 is an integrated circuit incorporating one DCP

with its associated registers, non-volatile memory and the

SPI serial interface providing direct communication between

host and potentiometer and memory. The resistor array is

comprised of individual resistors connected in series. At

either end of the array and between each resistor is an

electronic switch that transfers the potential at that point to

the wiper.

IVR

WR

The non-volatile IVR and volatile WR registers are

accessible with the same address.

The Access Control Register (ACR) contains information

and control bits described in Table 2.

The VOL bit (ACR<7>) determines whether the access is to

wiper registers WR or initial value registers IVR.

The electronic switches on the device operate in a “make

before break” mode when the wiper changes tap positions.

TABLE 2. ACCESS CONTROL REGISTER (ACR)

When the device is powered down, the last value stored in

IVR will be maintained in the non-volatile memory. When

power is restored, the contents of the IVR is recalled and

loaded into the WR to set the wiper to the initial value.

BIT #

7

6

5

4

0

3

0

2

0

1

0

BIT NAME VOL SHDN WIP

If VOL bit is 0, the non-volatile IVR register is accessible. If

VOL bit is 1, only the volatile WR is accessible. Note, value

is written to IVR register also is written to the WR. The

default value of this bit is 0.

DCP Description

The DCP is implemented with a combination of resistor

elements and CMOS switches. The physical ends of each

DCP are equivalent to the fixed terminals of a mechanical

potentiometer (RH and RL pins). The RW pin of the DCP is

connected to intermediate nodes, and is equivalent to the

wiper terminal of a mechanical potentiometer. The position of

the wiper terminal within the DCP is controlled by a 7-bit

volatile Wiper Register (WR). When the WR of a DCP

contains all zeroes (WR<6:0>: 00h), its wiper terminal (RW) is

closest to its “Low” terminal (RL). When the WR register of a

DCP contains all ones (WR<6:0>: 7Fh), its wiper terminal

The SHDN bit (ACR<6>) disables or enables Shutdown mode.

This bit is logically ANDed with SHDN pin. When this bit is 0,

DCP is in Shutdown mode. Default value of SHDN bit is 1.

The WIP bit (ACR<5>) is read only bit. It indicates that

non-volatile write operation is in progress. The WIP bit can be

read repeatedly after a non-volatile write to determine if the

write has been completed. It is impossible to write to the WR or

ACR while WIP bit is 1.

FN6227.2

September 9, 2009

10

ISL22416

by Data Byte is sent to SDI pin. The host terminates the write

Shutdown Mode

operation by pulling the CS pin from LOW to HIGH. For a

write to address 0 (WR), the byte at address 2 (ACR<7>)

determines if the Data Byte is to be written to volatile or both

volatile and non-volatile registers. Refer to “Memory

Description” on page 10 and Figure 16.

The device can be put in Shutdown mode either by pulling the

SHDN pin to GND or setting the SHDN bit in the ACR register

to 0. The truth table for Shutdown mode is in Table 3.

TABLE 3. SHUTDOWN MODE

SHDN PIN

High

SHDN BIT

MODE

Normal operation

Shutdown

The internal non-volatile write cycle starts after rising edge of

CS and takes up to 20ms.

1

0

Low

Read Operation

High

Shutdown

A read operation to the ISL22416 is a three byte operation. It

requires first, the CS transition from HIGH to LOW, then a

valid Identification Byte, then a valid instruction byte followed

by “dummy” Data Byte is sent to SDI pin. The SPI host reads

the data from SDO pin on falling edge of SCK. The host

terminates the read operation by pulling the CS pin from

LOW to HIGH (see Figure 17).

Low

Shutdown

SPI Serial Interface

The ISL22416 supports an SPI serial protocol, mode 0. The

device is accessed via the SDI input and SDO output with

data clocked in on the rising edge of SCK, and clocked out

on the falling edge of SCK. CS must be LOW during

communication with the ISL22416. SCK and CS lines are

controlled by the host or master. The ISL22416 operates

only as a slave device.

In order to read back the non-volatile IVR, it is recommended

that the application reads the ACR first to verify the WIP bit

is 0. If the WIP bit (ACR[5]) is not 0, the host should repeat

its reading sequence again.

All communication over the SPI interface is conducted by

sending the MSB of each byte of data first.

Applications Information

Communicating with ISL22416

Protocol Conventions

Communication with ISL22416 proceeds using SPI interface

through the ACR (address 10b), IVR (address 00b) and WR

(address 00b) registers.

The first byte sent to the ISL22416 from the SPI host is the

Identification Byte. A valid Identification Byte contains 0101

as the four MSBs, with the following four bits set to 0.

The wiper of the potentiometer is controlled by the WR

register. Writes and reads can be made directly to this

register to control and monitor the wiper position without any

non-volatile memory changes. This is done by setting MSB

bit at address 10b to 1.

TABLE 4. IDENTIFICATION BYTE FORMAT

0

1

0

1

0

(MSB)

(LSB)

The next byte sent to the ISL22416 contains the instruction

and register pointer information. The four MSBs are the

instruction and two LSBs are register address (see Table 5).

The non-volatile IVR stores the power up value of the wiper.

IVR is accessible when MSB bit at address 10b is set to 0.

Writing a new value to the IVR register will set a new power

up position for the wiper. Also, writing to this register will load

the same value into the WR as the IVR. Reading from the

IVR will not change the WR, if its contents are different.

TABLE 5. IDENTIFICATION BYTE FORMAT

7

6

5

4

3

0

2

0

1

0

I3

I2

I1

I0

R1

R0

There are only two valid instruction sets:

1011(binary) - is a Read operation

1100(binary) - is a Write operation

There are only two registers address possible for this DCP. If

the R1, R0 bits are zero, then the read or write is to either the

IVR or the WR register (depends of VOL bit at ACR). If the R1

bit is 1 and R0 bit is 0, then the operation is on the ACR.

Write Operation

A Write operation to the ISL22416 is a three-byte operation.

It requires first, the CS transition from HIGH to LOW, then a

valid Identification Byte, then a valid instruction byte followed

FN6227.2

September 9, 2009

11

ISL22416

CS

SCK

SDI

0

1

0

1

0

I3 I2

I1 I0

0

R1 R0

0

D6 D5 D4 D3 D2 D1 D0

FIGURE 16. THREE BYTE WRITE SEQUENCE

CS

SCK

SDI

DON’T CARE

0

1

0

1

0

I3 I2

I1 I0

0

R1 R0

SDO

0

D6 D5 D4 D3 D2 D1 D0

FIGURE 17. THREE BYTE READ SEQUENCE

B. Reading from the WR

Examples

This sequence will read the value from the WR (volatile):

A. Writing to the IVR

Write to ACR first to access the WR

This sequence will write a new value (77h) to the IVR

(non-volatile):

Send the ID byte, Instruction Byte, then the Data byte

Set the ACR (Addr 02h) for NV write (40h)

0 1 0 1 0 0 0 0 1 1 0 0 0 0 1 0 1 1 0 0 0 0 0 0

Send the ID byte, Instruction Byte, then the Data byte

(Sent to DI)

0 1 0 1 0 0 0 0 1 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0

Read the data from WR (Addr 00h)

(Sent to DI)

Send the ID byte, Instruction Byte, then Read the Data byte

Set the IVR (Addr 00h) to 77h

0 1 0 1 0 0 0 0 1 0 1 1 0 0 0 0 x x x x x x x x

Send the ID byte, Instruction Byte, then the Data byte

(Out on DO)

0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 1 0 1 1 1

(Sent to DI)

FN6227.2

September 9, 2009

12

ISL22416

Mini Small Outline Plastic Packages (MSOP)

N

M10.118 (JEDEC MO-187BA)

10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE

E1

E

INCHES

MILLIMETERS

SYMBOL

MIN

MAX

MIN

0.94

0.05

0.75

0.18

0.09

2.95

MAX

1.10

0.15

0.95

0.27

0.20

3.05

NOTES

-B-

0.20 (0.008)

INDEX

AREA

A

A1

A2

b

0.037

0.002

0.030

0.007

0.004

0.116

0.043

0.006

0.037

0.011

0.008

0.120

-

1 2

A

B

C

-

TOP VIEW

-

4X θ

0.25

(0.010)

R1

9

R

GAUGE

PLANE

c

-

D

3

SEATING

PLANE

E1

e

4

L

-C-

4X θ

0.020 BSC

0.50 BSC

-

L1

A

A2

E

0.187

0.016

0.199

0.028

4.75

0.40

5.05

0.70

-

SEATING

PLANE

L

6

0.10 (0.004)

-A-

C

L1

N

0.037 REF

10

0.95 REF

10

-

b

-H-

A1

7

e

D

R

0.003

-

0.07

-

0.20 (0.008)

C

R1

θ

-

a

SIDE VIEW

o

C

L

5

15

5

15

-

o

E

1

0

6

0

6

-

α

-B-

0.20 (0.008)

C

D

END VIEW

Rev. 0 12/02

NOTES:

1. These package dimensions are within allowable dimensions of

JEDEC MO-187BA.

2. Dimensioning and tolerancing per ANSI Y14.5M-1994.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs and are measured at Datum Plane. Mold flash, protrusion

and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions

- H -

and are measured at Datum Plane.

Interlead flash and

protrusions shall not exceed 0.15mm (0.006 inch) per side.

5. Formed leads shall be planar with respect to one another within

0.10mm (.004) at seating Plane.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable

dambar protrusion shall be 0.08mm (0.003 inch) total in excess

of “b” dimension at maximum material condition. Minimum space

between protrusion and adjacent lead is 0.07mm (0.0027 inch).

- B -

-A -

10. Datums

and

to be determined at Datum plane

.

- H -

11. Controlling dimension: MILLIMETER. Converted inch dimen-

sions are for reference only

FN6227.2

September 9, 2009

13

ISL22416

Thin Dual Flat No-Lead Plastic Package (TDFN)

L10.3x3B

2X

10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE

0.15

C A

A

D

MILLIMETERS

2X

0.15

C B

SYMBOL

MIN

0.70

-

NOMINAL

0.75

MAX

0.80

0.05

NOTES

A

A1

A3

b

-

E

0.20 REF

0.25

-

6

0.18

2.23

1.49

0.30

2.48

1.74

5, 8

INDEX

AREA

D

3.00 BSC

2.38

-

D2

E

7, 8

TOP VIEW

B

A

3.00 BSC

1.64

-

// 0.10

0.08

C

E2

e

7, 8

0.50 BSC

-

C

k

0.20

0.30

-

A3

C

SIDE VIEW

L

0.40

0.50

8

SEATING

PLANE

N

10

2

Nd

5

3

D2

D2/2

2

7

8

(DATUM B)

Rev. 0 2/06

NOTES:

1

1. Dimensioning and tolerancing conform to ASME Y14.5-1994.

2. N is the number of terminals.

6

INDEX

AREA

NX k

E2

3. Nd refers to the number of terminals on D.

(DATUM A)

4. All dimensions are in millimeters. Angles are in degrees.

5. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

E2/2

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be

either a mold or mark feature.

NX L

N

N-1

NX b

5

8

e

7. Dimensions D2 and E2 are for the exposed pads which provide

improved electrical and thermal performance.

(Nd-1)Xe

REF.

M

0.10

C A B

8. Nominal dimensions are provided to assist with PCB Land

Pattern Design efforts, see Intersil Technical Brief TB389.

BOTTOM VIEW

9. COMPLIANT TO JEDEC MO-229-WEED-3 except for

dimensions E2 & D2.

C

L

(A1)

NX (b)

L

9

5

e

SECTION "C-C"

TERMINAL TIP

FOR ODD TERMINAL/SIDE

C

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6227.2

September 9, 2009

14


型号：	ISL22416WFRT10Z
厂家：	Intersil
描述：	Single Digitally Controlled Potentiometer XDCP 单数字控制电位器XDCP 转换器电位器电阻器光电二极管
文件：	总14页 (文件大小：518K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL22416WFRT10Z [INTERSIL]

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