ISL23415WFRUZ-TK_技术文档

Single, Low Voltage Digitally Controlled Potentiometer

(XDCP™)

ISL23415

The ISL23415 is a volatile, low voltage, low noise, low power,

SPI™ bus, 256 taps, single digitally controlled potentiometer

(DCP), which integrates DCP core, wiper switches and control

logic on a monolithic CMOS integrated circuit.

Features

• 256 resistor taps

• SPI serial interface

- No additional level translator for low bus supply

- Daisy Chaining of multiple DCP

The digitally controlled potentiometer is implemented with a

combination of resistor elements and CMOS switches. The

position of the wipers are controlled by the user through the

SPI bus interface. The potentiometer has an associated

volatile Wiper Register (WR) that can be directly written to and

read by the user. The contents of the WR controls the position

of the wiper. When powered on, the ISL23415’s wiper will

always commence at mid-scale (128 tap position).

• Wiper resistance: 70Ω typical @ V = 3.3V

CC

• Shutdown Mode - forces the DCP into an end-to-end open

circuit and RW is shorted to RL internally

• Power-on preset to mid-scale (128 tap position)

• Standby current <2.5µA max

• Shutdown current <2µA

• Power supply

The low voltage, low power consumption, and small package

of the ISL23415 make it an ideal choice for use in battery

- V = 1.7V to 5.5V analog power supply

CC

operated equipment. In addition, the ISL23415 has a V

LOGIC

- V

LOGIC

= 1.2V to 5.5V SPI bus/logic power supply

pin allowing down to 1.2V bus operation, independent from the

value. This allows for low logic levels to be connected

• DCP terminal voltage from 0V to V

CC

V

CC

directly to the ISL23415 without passing through a voltage

level shifter.

• 10kΩ, 50kΩ or 100kΩ total resistance

• Extended industrial temperature range: -40°C to +125°C

• 10 Ld MSOP or 10 Ld µTQFN packages

• Pb-free (RoHS compliant)

The DCP can be used as a three-terminal potentiometer or as a

two-terminal variable resistor in a wide variety of applications

including control, parameter adjustments, and signal

processing.

Applications

• Power supply margining

• RF power amplifier bias compensation

• LCD bias compensation

• Gain adjustment in battery powered instruments

• Portable medical equipment calibration

10000

8000

6000

4000

2000

0

V_REF

-

V_{REF_M}

ISL23415

+

ISL28114

0

50

100

150

200

250

TAP POSITION (DECIMAL)

FIGURE 1. FORWARD AND BACKWARD RESISTANCE vs TAP

POSITION, 10k

FIGURE 2. V

ADJUSTMENT

REF

December 15, 2010

FN7780.0

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

1

ISL23415

Block Diagram

V

CC

LOGIC

RH

SCK

SDI

POWER-UP

INTERFACE,

CONTROL

AND

STATUS

LOGIC

I/O BLOCK

LEVEL

SHIFTER

WR

SDO

CS

VOLATILE

REGISTER

AND

WIPER

CONTROL

CIRCUITRY

RL

RW

GND

Pin Configurations

Pin Description

ISL23415

(10 LD MSOP)

TOP VIEW

MSOP

µTQFN

SYMBOL

DESCRIPTION

1

10

V

SPI bus/logic supply.

LOGIC

Range 1.2V to 5.5V

O

10

GND

V

1

2

3

4

5

LOGIC

SCK

2

3

1

2

SCK

SDO

Logic Pin - Serial bus clock input

V

9

CC

Logic Pin - Serial bus data output

(configurable)

RH

SDO

SDI

CS

8

7

RW

RL

4

5

6

7

8

9

3

4

5

6

7

8

SDI

CS

Logic Pin - Serial bus data input

Logic Pin - Active low Chip Select

DCP “low” terminal

6

RL

ISL23415

(10 LD µTQFN)

TOP VIEW

RW

RH

DCP wiper terminal

DCP “high” terminal

V

Analog power supply.

Range 1.7V to 5.5V

CC

O

SCK

1

9

8

7

6

GND

10

9

GND

Ground pin

SDO

SDI

CS

2

3

4

V

CC

RH

RW

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December 15, 2010

2

ISL23415

Ordering Information

RESISTANCE

PART NUMBER

(Note 5)

PART

MARKING

OPTION

(kΩ)

TEMP. RANGE

PACKAGE

(Pb-free)

PKG.

DWG. #

(°C)

ISL23415TFUZ (Notes 1, 3)

ISL23415UFUZ (Notes 1, 3)

ISL23415WFUZ (Notes 1, 3)

ISL23415TFRUZ-T7A (Notes 2, 4)

ISL23415TFRUZ-TK (Notes 2, 4)

ISL23415UFRUZ-T7A (Notes 2, 4)

ISL23415UFRUZ-TK (Notes 2, 4)

ISL23415WFRUZ-T7A (Notes 2, 4)

ISL23415WFRUZ-TK (Notes 2, 4)

NOTES:

3415T

3415U

100

50

-40 to +125

10 Ld MSOP

M10.118

10 Ld MSOP

M10.118

3415W

HE

10

10 Ld MSOP

M10.118

100

50

10 Ld µTQFN 2.1x1.6

L10.2.1x1.6A

HE

HD

50

HC

10

HC

10

1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

2. Please refer to TB347 for details on reel specifications.

3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu

plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are

MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

5. For Moisture Sensitivity Level (MSL), please see device information page for ISL23415. For more information on MSL please see techbrief TB363.

FN7780.0

December 15, 2010

3

ISL23415

Absolute Maximum Ratings

Thermal Information

Supply Voltage Range

Thermal Resistance (Typical)

10 Ld MSOP Package (Note 6, 7). . . . . . . .

10 Ld µTQFN Package (Note 6, 7) . . . . . . .

θ

_JA(°C/W)

170

θ

_JC(°C/W)

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V

70

90

CC

LOGIC

145

Voltage on any DCP Terminal Pin . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V

Voltage on any Digital Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V

Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C

Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Wiper Current I (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

W

ESD Rating

Human Body Model (Tested per JESD22-A114E). . . . . . . . . . . . . . .6.5kV

CDM Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . . . . . . . . 1kV

Machine Model (Tested per JESD22-A115-A). . . . . . . . . . . . . . . . . . 200V

Latch Up

Recommended Operating Conditions

Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C

(Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . 100mA @ +125°C

V

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7V to 5.5V

CC

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2V to 5.5V

LOGIC

DCP Terminal Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to V

CC

Max Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3mA

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

6. θ_JAis measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

7. For θ , the “case temp” location is the center top of the package.

JC

Analog Specifications

V

= 2.7V to 5.5V, V

= 1.2V to 5.5V over recommended operating conditions unless otherwise stated.

LOGIC

CC

Boldface limits apply over the operating temperature range, -40°C to +125°C.

MIN

TYP

MAX

SYMBOL

PARAMETER

to R resistance

TEST CONDITIONS

(Note 20)

(Note 8)

(Note 20)

UNITS

R

W option

U option

T option

10

50

kΩ

TOTAL

H

L

kΩ

100

±2

R

to R resistance tolerance

-20

+20

%

H

L

End-to-End Temperature Coefficient

W option

U option

T option

175

85

ppm/°C

V

70

V

, V

RH RL

DCP terminal voltage

Wiper resistance

V

or V to GND

RL

0

V

CC

RH

R

RH - floating, V = 0V, force I current

RL

70

200

Ω

W

to the wiper, I = (V - V )/R

W

CC RL

TOTAL,

V

= 2.7V to 5.5V

CC

V

= 1.7V

580

22/22/32

<0.1

Ω

CC

C /C /C

W

Terminal capacitance

Leakage on DCP pins

Resistor noise density

See “DCP Macro Model” on page 8.

Voltage at pin from GND to V

pF

µA

H

L

I

-0.4

0.4

LkgDCP

Noise

CC

Wiper at middle point, W option

Wiper at middle point, U option

Wiper at middle point, T option

120

nV/ Hz

√

190

nV/ Hz

√

220

nV/ Hz

√

Feed Thru Digital feedthrough from bus to wiper Wiper at middle point

-65

dB

PSRR

Power Supply Reject Ratio

Wiper output change if V change

CC

-75

±10%; wiper at middle point

FN7780.0

December 15, 2010

4

ISL23415

Analog Specifications

V

= 2.7V to 5.5V, V

= 1.2V to 5.5V over recommended operating conditions unless otherwise stated.

LOGIC

CC

Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)

MIN

TYP

MAX

SYMBOL

PARAMETER

TEST CONDITIONS

(Note 20)

(Note 8)

(Note 20)

UNITS

VOLTAGE DIVIDER MODE (0V @ RL; V @ RH; measured at RW, unloaded)

CC

Integral non-linearity, Guaranteed

(Note 13) monotonic

INL

W option

U, T option

W option

U, T option

W option

U, T option

W option

U, T option

-1.0

-0.5

-1

±0.5

±0.15

±0.4

±0.1

-2

+1.0

+0.5

+1

LSB

(Note 9)

LSB

(Note 9)

DNL

Differential non-linearity, Guaranteed

LSB

(Note 9)

(Note 12) monotonic

-0.4

-3.5

-2

+0.4

0

LSB

(Note 9)

FSerror

Full-scale error

LSB

(Note 9)

(Note 11)

-0.5

2

0

LSB

(Note 9)

ZSerror

Zero-scale error

0

3.5

2

LSB

(Note 9)

(Note 10)

0

0.4

LSB

(Note 9)

TC

(Note 14)

Ratiometric temperature coefficient

W option, Wiper Register set to 80 hex

U option, Wiper Register set to 80 hex

T option, Wiper Register set to 80 hex

From code 0 to FF hex

8

4

ppm/°C

ns

V

2.3

Large signal wiper settling time

-3dB cutoff frequency

300

1200

250

120

f

Wiper at middle point W option

Wiper at middle point U option

Wiper at middle point T option

kHz

cutoff

kHz

RHEOSTAT MODE (Measurements between RW and RL pins with RH not connected, or between RW and RH with RL not connected)

RINL

Integral non-linearity, Guaranteed

W option; V = 2.7V to 5.5V

CC

-2.0

-1.0

-1

±1

10.5

±0.3

2.1

+2.0

+1.0

+1

MI

(Note 15)

(Note 18) monotonic

W option; V = 1.7V

CC

MI

(Note 15)

U, T option; V = 2.7V to 5.5V

CC

MI

(Note 15)

U, T option; V = 1.7V

CC

MI

(Note 15)

RDNL

(Note 17) monotonic

Differential non-linearity, Guaranteed

W option; V = 2.7V to 5.5V

CC

±0.4

±0.6

±0.15

±0.35

MI

(Note 15)

W option; V = 1.7V

CC

MI

(Note 15)

U, T option; V = 2.7V to 5.5V

CC

-0.5

+0.5

MI

(Note 15)

U, T option; V = 1.7V

CC

MI

(Note 15)

FN7780.0

December 15, 2010

5

ISL23415

Analog Specifications

V

= 2.7V to 5.5V, V

= 1.2V to 5.5V over recommended operating conditions unless otherwise stated.

LOGIC

CC

Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)

MIN

TYP

MAX

SYMBOL

PARAMETER

TEST CONDITIONS

W option; V = 2.7V to 5.5V

(Note 20)

(Note 8)

(Note 20)

UNITS

R

Offset, wiper at 0 position

0

3

5.5

2

MI

(Note 15)

offset

CC

(Note 16)

W option; V = 1.7V

CC

6.3

0.5

1.1

220

100

75

MI

(Note 15)

U, T option; V = 2.7V to 5.5V

CC

MI

(Note 15)

U, T option; V = 1.7V

CC

MI

(Note 15)

TCR

(Note 19)

Resistance temperature coefficient

W option; Wiper register set between

32 hex and FF hex

ppm/°C

U option; Wiper register set between

32 hex and FF hex

T option; Wiper register set between 32

hex and FF hex

Operating Specifications

V

= 2.7V to 5.5V, V

= 1.2V to 5.5V over recommended operating conditions unless otherwise stated.

LOGIC

CC

Boldface limits apply over the operating temperature range, -40°C to +125°C.

MIN

TYP

MAX

SYMBOL

PARAMETER

TEST CONDITIONS

(Note 20)

(Note 8)

(Note 20)

UNITS

mA

I

V

supply current (write/read)

V

= 5.5V, V = 5.5V,

1.5

30

LOGIC

CC

f

= 5MHz (for SPI active read and write)

SCK

V

= 1.2V, V = 1.7V,

CC

µA

LOGIC

= 1MHz (for SPI active read and write)

f

SCK

I

V

supply current (write/read)

V

= 5.5V, V = 5.5V

CC

100

10

1

µA

CC

LOGIC

= 1.2V, V = 1.7V

CC

I

standby current

= 5.5V, V = 5.5V,

CC

LOGIC SB

LOGIC

SPI interface in standby

V

= 1.2V, V = 1.7V,

0.5

1.5

1

µA

LOGIC

CC

SPI interface in standby

I

V

standby current

V = 5.5V, V = 5.5V,

LOGIC CC

SPI interface in standby

CC SB

CC

V

= 1.2V, V = 1.7V,

LOGIC

CC

SPI interface in standby

I

V

shutdown current

V

= 5.5V, V = 5.5V,

LOGIC CC

1.3

0.4

0.7

0.5

0.4

LOGIC SHDN LOGIC

SPI interface in standby

V

= 1.2V, V = 1.7V,

LOGIC

CC

SPI interface in standby

I

V

shutdown current

V = V = 5.5V,

LOGIC CC

SPI interface in standby

CC SHDN

CC

V

= 1.2V, V = 1.7V,

LOGIC

CC

SPI interface in standby

I

Leakage current, at pins CS, SDO, SDI, SCK Voltage at pin from GND to V

-0.4

<0.1

1.5

µA

µs

LkgDig

LOGIC

t

Wiper response time

CS rising edge to wiper new position

DCP

tShdnRec DCP recall time from shutdown mode

CS rising edge to wiper recalled position and

RH connection

1.5

V

, V

V

, V

ramp rate

Ramp monotonic at any level

0.01

50

V/ms

CC LOGIC CC LOGIC

Ramp

FN7780.0

December 15, 2010

6

ISL23415

Serial Interface Specification For SCK, SDI, SDO, CS Unless Otherwise Noted.

MIN

TYP

MAX

SYMBOL

PARAMETER

Input LOW Voltage

TEST CONDITIONS

(Note 20)

(Note 8)

(Note 20)

UNITS

V

-0.3

0.3 x V

V

IL

LOGIC

V

Input HIGH Voltage

0.7 x V

V

LOGIC

+ 0.3

IH

LOGIC

Hysteresis

SDI and SCK Input Buffer Hysteresis

V

> 2V

< 2V

0.05 x V

LOGIC

0.1 x V

0

LOGIC

V

SDO Output Buffer LOW Voltage

SDO pull-up resistor off-chip

I

= 3mA, V

> 2V

0.4

V

OL

LOGIC

= 1.5mA, V

< 2V

0.2 x V

LOGIC

R

Maximum is determined by t and t with

1.5

kΩ

pu

(Note 19)

RO

FO

= 5MHz

maximum bus load Cb = 30pF, f

SCK

C

SCK, SDO, SDI, CS Pin Capacitance

SCK Frequency

10

pF

MHz

ns

f

V

= 1.7V to 5.5V

= 1.2V to 1.6V

≥ 1.7V

5

1

SCK

LOGIC

t

SPI clock cycle time

200

CYC

t

SPI clock high time

≥ 1.7V

100

250

50

ns

WH

t

SPI clock low time

≥ 1.7V

ns

WL

t

Lead time

≥ 1.7V

ns

LEAD

t

Lag time

≥ 1.7V

ns

LAG

t

SDI, SCK and CS input setup time

SDI, SCK and CS input hold time

SDI, SCK and CS input rise time

SDI, SCK and CS input fall time

SDO output Disable time

SDO output setup time

SDO output valid time

SDO output hold time

SDO output rise time

SDO output fall time

CS deselect time

≥ 1.7V

ns

SU

t

≥ 1.7V

50

ns

H

t

≥ 1.7V

10

ns

RI

t

≥ 1.7V

10

20

ns

FI

t

≥ 1.7V

0

100

ns

DIS

t

≥ 1.7V

50

ns

SO

t

≥ 1.7V

150

0

ns

V

t

≥ 1.7V

ns

HO

RO

t

R

= 1.5k, Cbus = 30pF

60

ns

pu

t

R

ns

FO

CS

2

µs

NOTES:

8. Typical values are for T = +25°C and 3.3V supply voltages.

A

9. LSB = [V(RW)

255

– V(RW) ]/255. V(RW)

and V(RW) are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the incremental

255 0

0

voltage when changing from one tap to an adjacent tap.

10. ZS error = V(RW) /LSB.

0

11. FS error = [V(RW)

255

– V ]/LSB.

CC

12. DNL = [V(RW) – V(RW) ]/LSB-1, for i = 1 to 255. i is the DCP register setting.

i-1

i

13. INL = [V(RW) – i • LSB – V(RW) ]/LSB for i = 1 to 255

i

0

Max(V(RW) ) – Min(V(RW) )

6

10

14.

i

for i = 16 to 255 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper voltage

and Min( ) is the minimum value of the wiper voltage over the temperature range.

----------------------------------------------------------------------------- ---------------------

TC

=

×

V

V(RWi(+25°C))

+165°C

15. MI = |RW

– RW |/255. MI is a minimum increment. RW and RW are the measured resistances for the DCP register set to FF hex and 00

255 0

255

hex respectively.

0

16. Roffset = RW /MI, when measuring between RW and RL.

0

Roffset = RW

/MI, when measuring between RW and RH.

255

17. RDNL = (RW – RW )/MI -1, for i = 16 to 255.

i-1

i

18. RINL = [RW – (MI • i) – RW ]/MI, for i = 16 to 255.

i

0

6

[Max(Ri) – Min(Ri)]

10

19.

for i = 16 to 255, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min( ) is the

minimum value of the resistance over the temperature range.

------------------------------------------------------ ---------------------

TC

=

×

R

Ri(+25°C)

+165°C

20. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

FN7780.0

December 15, 2010

7

ISL23415

DCP Macro Model

R

TOTAL

RH

RL

C

L

C

H

C

W

22pF

32pF

RW

Timing Diagrams

Input Timing

t

CS

t

LAG

LEAD

CYC

SCK

SDI

...

t

WH

t

RI

FI

t

WL

SU

H

...

MSB

LSB

SDO

Output Timing

CS

SCK

SDO

SDI

...

t

SO

HO

DIS

MSB

LSB

t

V

ADDR

XDCP™ Timing (for All Load Instructions)

CS

t

DCP

SCK

...

MSB

LSB

SDI

V

W

SDO

*When CS is HIGH

SDO at Z or Hi-Z state

FN7780.0

December 15, 2010

8

ISL23415

Typical Performance Curves

0.4

0.30

0.2

0

0.15

0

-0.2

-0.4

-0.15

-0.30

0

50

100

150

200

250

0

50

100

150

200

250

TAP POSITION (DECIMAL)

FIGURE 3. 10k DNL vs TAP POSITION, V = 5V

CC

FIGURE 4. 50k DNL vs TAP POSITION, V = 5V

CC

0.30

0.15

0

0.4

0.2

0

-0.2

-0.4

-0.15

-0.30

0

50

100

150

200

250

50

100

150

200

TAP POSITION (DECIMAL)

FIGURE 5. 10k INL vs TAP POSITION, V = 5V

CC

FIGURE 6. 50k INL vs TAP POSITION, V = 5V

CC

0.4

0.2

0

0.30

0.15

0

-0.2

-0.4

-0.15

-0.30

50

100

150

200

0

50

100

150

200

250

TAP POSITION (DECIMAL)

FIGURE 7. 10k RDNL vs TAP POSITION, V = 5V

CC

FIGURE 8. 50k RDNL vs TAP POSITION, V = 5V

CC

FN7780.0

December 15, 2010

9

ISL23415

Typical Performance Curves (Continued)

0.6

0.4

0.2

0

0.30

0.15

0

-0.2

-0.4

-0.6

-0.15

-0.30

0

50

100

150

200

250

0

50

100

150

200

250

TAP POSITION (DECIMAL)

FIGURE 9. 10k RINL vs TAP POSITION, V = 5V

CC

FIGURE 10. 50k RINL vs TAP POSITION, V = 5V

CC

60

50

40

30

20

10

0

70

60

50

40

30

20

10

0

+125°C

+25°C

-40°C

0

50

100

150

200

250

0

50

100

150

200

250

TAP POSITION (DECIMAL)

FIGURE 11. 10k WIPER RESISTANCE vs TAP POSITION, V = 5V

CC

FIGURE 12. 50k WIPER RESISTANCE vs TAP POSITION, V = 5V

CC

300

250

200

150

100

50

70

60

50

40

30

20

10

0

15

65

115

165

215

15

65

115

165

215

TAP POSITION (DECIMAL)

FIGURE 13. 10k TCv vs TAP POSITION

FIGURE 14. 50k TCv vs TAP POSITION

FN7780.0

December 15, 2010

10

ISL23415

Typical Performance Curves (Continued)

600

500

400

300

200

100

0

200

150

100

50

0

15

65

115

165

215

65

115

165

215

TAP POSITION (DECIMAL)

FIGURE 15. 10k TCr vs TAP POSITION

FIGURE 16. 50k TCr vs TAP POSITION

35

30

25

20

15

10

5

120

90

60

30

0

15

65

115

165

215

15

65

115

165

215

TAP POSITION (DECIMAL)

FIGURE 17. 100k TCv vs TAP POSITION

FIGURE 18. 100k TCr vs TAP POSITION

SCK CLOCK

RW PIN

10mV/DIV

1µs/DIV

20mV/DIV

5µs/DIV

FIGURE 19. WIPER DIGITAL FEEDTHROUGH

FIGURE 20. WIPER TRANSITION GLITCH

FN7780.0

December 15, 2010

11

ISL23415

Typical Performance Curves (Continued)

1V/DIV

1µs/DIV

0.1s/DIV

VRW

CS RISING EDGE

FIGURE 21. WIPER LARGE SIGNAL SETTLING TIME

FIGURE 22. POWER-ON START-UP IN VOLTAGE DIVIDER MODE

1.2

1.0

0.8

CH1: 0.5V/DIV, 0.2µs/DIV RH PIN

CH2: 0.2V/DIV, 0.2µs/DIV RW PIN

V

= 5.5V, V

= 5.5V

LOGIC

CC

0.6

0.4

0.2

0

V

= 1.7V, V

= 1.2V

LOGIC

CC

R

= 10k

TOTAL

-40

-15

10

35

60

85

110

-3dB FREQUENCY = 1.4MHz AT MIDDLE TAP

TEMPERATURE (°C)

FIGURE 23. 10k -3dB CUT OFF FREQUENCY

FIGURE 24. STANDBY CURRENT vs TEMPERATURE

Functional Pin Description

Potentiometers Pins

RH AND RL

Bus Interface Pins

SERIAL CLOCK (SCL)

The high (RH) and low (RL) terminals of the ISL23415 are

equivalent to the fixed terminals of a mechanical potentiometer.

The RH and RL are referenced to the relative position of the wiper

and not the voltage potential on the terminals. With the WR

register set to 255 decimal, the wiper will be closest to RH, and

with the WR register set to 0, the wiper is closest to RL.

This input is the serial clock of the SPI serial interface.

SERIAL DATA INPUT (SDI)

The SDI is a serial data input pin for SPI interface. It receives

operation code, wiper address and data from the SPI remote

host device. The data bits are shifted in at the rising edge of the

serial clock SCK, while the CS input is low.

RW

SERIAL DATA OUTPUT (SDO)

The RW is the wiper terminal, and it is equivalent to the

moveable terminal of a mechanical potentiometer. The position

of the wiper within the array is determined by the WR register.

The SDO is a serial data output pin. During a read cycle, the data

bits are shifted out on the falling edge of the serial clock SCK and

will be available to the master on the following rising edge of SCK.

The output type is configured through ACR[1] bit for Push-Pull or

Open Drain operation. Default setting for this pin is Push-Pull. An

FN7780.0

December 15, 2010

12

ISL23415

external pull-up resistor is required for Open Drain output

operation. When CS is HIGH, the SDO pin is in tri-state (Z) or

high-tri-state (Hi-Z) depends on the selected configuration.

Register (ACR) at address 10h contains information and control

bits described in Table 2.

TABLE 1. MEMORY MAP

CHIP SELECT (CS)

ADDRESS

(hex)

DEFAULT SETTING

(hex)

VOLATILE

ACR

CS LOW enables the ISL23415, placing it in the active power

mode. A HIGH to LOW transition on CS is required prior to the

start of any operation after power-up. When CS is HIGH, the

ISL23415 is deselected and the SDO pin is at high impedance,

and the device will be in the standby state.

10

0

40

80

WR

TABLE 2. ACCESS CONTROL REGISTER (ACR)

BIT #

7

6

5

0

4

0

3

0

2

0

1

0

Principles of Operation

NAME

0

SHDN

SDO

The ISL23415 is an integrated circuit incorporating one DCP with

its associated registers and an SPI serial interface providing

direct communication between a host and the potentiometer.

The resistor array is comprised of individual resistors connected

in series. At either end of the array and between each resistor is

an electronic switch that transfers the potential at that point to

the wiper.

The SHDN bit (ACR[6]) disables or enables Shutdown mode. When

this bit is 0, i.e., each DCP is forced to end-to-end open circuit and

each RW is shorted to RL as shown in Figure 25. Default value of

the SHDN bit is 1.

RH

The electronic switches on the device operate in a “make before

break” mode when the wiper changes tap positions.

Voltage at any DCP pins, RH, RL or RW, should not exceed V

CC

RW

level at any conditions during power-up and normal operation.

The V

pin needs to be connected to the SPI bus supply

LOGIC

which allows reliable communication with the wide range of

RL

microcontrollers and independent of the V level. This is

CC

FIGURE 25. DCP CONNECTION IN SHUTDOWN MODE

extremely important in systems where the digital supply has

lower levels than the analog supply.

The SDO bit (ACR[1]) configures type of SDO output pin. The

default value of SDO bit is 0 for Push-Pull output. The SDO pin

can be configured as Open Drain output for some applications. In

this case, an external pull-up resistor is required, reference the

“Serial Interface Specification” on page 7.

DCP Description

Each DCP is implemented with a combination of resistor

elements and CMOS switches. The physical ends of DCP are

equivalent to the fixed terminals of a mechanical potentiometer

(RH and RL pins). The RW pin of the DCP is connected to

intermediate nodes, and is equivalent to the wiper terminal of a

mechanical potentiometer. The position of the wiper terminal

within the DCP is controlled by the 8-bit volatile Wiper Register

(WR). When the WR of a DCP contains all zeroes (WR[7:0] = 00h),

its wiper terminal (RW) is closest to its “Low” terminal (RL). When

the WR register of a DCP contains all ones (WR[7:0] = FFh), its

wiper terminal (RW) is closest to its “High” terminal (RH). As the

value of the WR increases from all zeroes (0) to all ones (255

decimal), the wiper moves monotonically from the position

closest to RL to the position closest to RH. At the same time, the

resistance between RW and RL increases monotonically, while

the resistance between RH and RW decreases monotonically.

SPI Serial Interface

The ISL23415 supports an SPI serial protocol, mode 0. The

device is accessed via the SDI input and SDO output with data

clocked in on the rising edge of SCK, and clocked out on the

falling edge of SCK. CS must be LOW during communication with

the ISL23415. The SCK and CS lines are controlled by the host or

master. The ISL23415 operates only as a slave device.

All communication over the SPI interface is conducted by

sending the MSB of each byte of data first.

Protocol Conventions

The SPI protocol contains Instruction Byte followed by one or more

Data Bytes. A valid Instruction Byte contains instruction as the three

MSBs, with the following five register address bits (see Table 3).

While the ISL23415 is being powered up, the WR is reset to 80h

(128 decimal), which locates RW roughly at the center between

RL and RH.

The next byte sent to the ISL23415 is the Data Byte.

TABLE 3. INSTRUCTION BYTE FORMAT

The WR can be read or written to directly using the SPI serial

interface as described in the following sections.

BIT #

7

6

5

4

3

2

1

0

I2

I1

I0

R4

R3

R2

R1

R0

Memory Description

The ISL23415 contains two volatile 8-bit registers: the Wiper

Register (WR) and the Access Control Register (ACR). Memory map

of ISL23415 is in Table 1. The Wiper Register WR at address 0

contains current wiper position of the DCP. The Access Control

Table 4 contains a valid instruction set for ISL23415.

If the [R4:R0] bits are zero, then the read or write is to the WR

register. If the [R4:R0] are 10000, then the operation is to the ACR.

FN7780.0

December 15, 2010

13

ISL23415

Write Operation

Read Operation

A write operation to the ISL23415 is a two or more bytes

operation. It requires first, the CS transition from HIGH-to-LOW.

Then host send a valid Instruction Byte, followed by one or more

Data Bytes to SDI pin. The host terminates the write operation by

pulling the CS pin from LOW-to-HIGH. Instruction is executed on

rising edge of CS.

A Read operation to the ISL23415 is a four byte operation. It

requires first, the CS transition from HIGH-to-LOW. Then host

send a valid Instruction Byte, followed by “dummy” Data Byte,

NOP Instruction Byte and another “dummy” Data Byte to SDI pin.

The SPI host receives the Instruction Byte (instruction code +

register address) and requested Data Byte from SDO pin on the

rising edge of SCK during third and fourth bytes respectively. The

host terminates the read by pulling the CS pin from LOW-to-HIGH

(see Figure 27).

TABLE 4. INSTRUCTION SET

INSTRUCTION SET

I2

0

1

I1

0

1

0

1

I0

0

1

0

R4

X

R3

X

R2

X

R1

X

R0

X

OPERATION

NOP

X

ACR READ

X

ACR WRTE

R4

R3

R2

R1

R0

WR or ACR READ

WR or ACR WRTE

where X means “do not care”.

CS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

SCK

DATA BYTE

WR INSTRUCTION

ADDR

SDI

SDO

FIGURE 26. TWO BYTE WRITE SEQUENCE

1

8

16

24

32

CS

SCK

NOP

RD

ADDR

SDI

RD

ADDR

READ DATA

SDO

FIGURE 27. FOUR BYTE READ SEQUENCE

FN7780.0

December 15, 2010

14

ISL23415

The first part starts by HIGH-to-LOW transition on CS line,

Applications Information

Communicating with ISL23415

Communication with ISL23415 proceeds using SPI interface

through the ACR (address 10000b) and WR (addresses 00000b)

registers.

followed by N two bytes read instruction on SDI line with reversed

chain access sequence: the instruction byte + dummy data byte

for the last DCP in chain is going first, followed by LOW-to-HIGH

transition on CS line. The read instructions are executed during

second part of read sequence. It also starts by HIGH-to-LOW

transition on CS line, followed by N number of two bytes NOP

instructions on SDI line and LOW-to-HIGH transition of CS. The

data is read on every even byte during second part of read

sequence while every odd byte contains code 111b followed by

address from which the data is being read.

The wiper of the potentiometer is controlled by the WR register.

Writes and reads can be made directly to these register to control

and monitor the wiper position.

Daisy Chain Configuration

Wiper Transition

When application needs more than one ISL23415, it can

communicate with all of them without additional CS lines by

daisy chaining the DCPs as shown on Figure 28. In Daisy Chain

configuration, the SDO pin of the previous chip is connected to

the SDI pin of the following chip, and each CS and SCK pins are

connected to the corresponding microcontroller pins in parallel,

like regular SPI interface implementation. The Daisy Chain

configuration can also be used for simultaneous setting of

multiple DCPs. Note, the number of daisy chained DCPs is

limited only by the driving capabilities of SCK and CS pins of

microcontroller; for larger number of SPI devices buffering of

SCK and CS lines is required.

When stepping up through each tap in voltage divider mode,

some tap transition points can result in noticeable voltage

transients, or overshoot/undershoot, resulting from the sudden

transition from a very low impedance “make” to a much higher

impedance “break within a short period of time (<1µs). There are

several code transitions such as 0Fh to 10h, 1Fh to 20h,..., EFh to

FFh, which have higher transient glitch. Note, that all switching

transients will settle well within the settling time as stated in the

datasheet. A small capacitor can be added externally to reduce

the amplitude of these voltage transients, but that will also

reduce the useful bandwidth of the circuit, thus may not be a

good solution for some applications. It may be a good idea, in

that case, to use fast amplifiers in a signal chain for fast

recovery.

Daisy Chain Write Operation

The write operation starts by HIGH-to-LOW transition on CS line,

followed by N number of two bytes write instructions on SDI line

with reversed chain access sequence: the instruction byte + data

byte for the last DCP in chain is going first, as shown in Figure 29,

where N is a number of DCPs in chain. The serial data is going

through DCPs from DCP0 to DCP(N-1) as follow: DCP0 --> DCP1 -->

DCP2 --> ... --> DCP(N-1). The write instruction is executed on the

rising edge of CS for all N DCPs simultaneously.

V

Requirements

LOGIC

It is recommended to keep V

normal operation. In a case where turning V

LOGIC

necessary, it is recommended to ground the V

ISL23415. Grounding the V

not affect other devices on the same bus. It is good practice to put

a 1µF capacitor in parallel with 0.1µF decoupling capacitor close to

powered all the time during

OFF is

pin of the

LOGIC

and V does

pin or both V

LOGIC

CC

Daisy Chain Read Operation

the V pin.

LOGIC

The read operation consists of two parts: first, send the read

instructions (N two bytes operation) with valid address; second,

read the requested data while sending NOP instructions (N two

bytes operation) as shown in Figures 30 and 31.

V

Requirements and Placement

CC

It is recommended to put a 1µF capacitor in parallel with 0.1µF

decoupling capacitor close to the V pin.

CC

N DCP IN A CHAIN

CS

SCK

DCP0

DCP1

DCP2

DCP(N-1)

CS

MOSI

MISO

CS

SCK

SDI

SCK

SDI

SCK

SDI

SCK

SDI

µC

SDO

FIGURE 28. DAISY CHAIN CONFIGURATION

FN7780.0

December 15, 2010

15

ISL23415

CS

SCK

16 CLKS

C P0

16 CLKLS

C P2

16 CLKS

WR

D

WR

D

C P1

C P2

WR

D

SDI

D

C P1

C P2

SDO 0

WR

D

SDO 1

SDO 2

FIGURE 29. DAISY CHAIN WRITE SEQUENCE OF N = 3 DCP

CS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

SCK

SDI

INSTRUCTION

ADDR

DATA IN

SDO

DATA OUT

FIGURE 30. TWO BYTE READ INSTRUCTION

CS

SCK

SDI

16 CLKS

RD DCP2

16 CLKS

RD DCP1

16 CLKS

RD DCP0

16 CLKS

NOP

16 CLKS

NOP

16 CLKS

NOP

DCP0 OUT

DCP2 OUT

DCP1 OUT

SDO

FIGURE 31. DAISY CHAIN READ SEQUENCE OF N = 3 DCP

FN7780.0

December 15, 2010

16

ISL23415

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make

sure you have the latest Rev.

DATE

REVISION

FN7780.0

CHANGE

12/15/10

Initial Release

Products

Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address

some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product

families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil

product families.

*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on

intersil.com: ISL23415

To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff

FITs are available from our website at http://rel.intersil.com/reports/search.php

For additional products, see www.intersil.com/product_tree

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time

without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be

accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN7780.0

December 15, 2010

17

ISL23415

Mini Small Outline Plastic Packages (MSOP)

N

M10.118 (JEDEC MO-187BA)

10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE

INCHES

MILLIMETERS

E1

E

SYMBOL

MIN

MAX

MIN

0.94

0.05

0.75

0.18

0.09

2.95

MAX

1.10

0.15

0.95

0.27

0.20

3.05

NOTES

A

A1

A2

b

0.037

0.002

0.030

0.007

0.004

0.116

0.043

0.006

0.037

0.011

0.008

0.120

-

-B-

0.20 (0.008)

INDEX

AREA

1 2

A

B

C

-

TOP VIEW

4X θ

9

0.25

(0.010)

R1

c

-

R

GAUGE

PLANE

D

3

E1

e

4

SEATING

PLANE

L

0.020 BSC

0.50 BSC

-

-C-

4X θ

L1

A

A2

E

0.187

0.016

0.199

0.028

4.75

0.40

5.05

0.70

-

L

6

SEATING

PLANE

L1

N

0.037 REF

10

0.95 REF

10

-

0.10 (0.004)

-A-

C

b

7

-H-

A1

e

R

0.003

-

0.07

-

D

0.20 (0.008)

C

R1

θ

-

o

a

SIDE VIEW

5

15

5

15

-

C

L

o

0

6

0

6

-

α

E

1

-B-

Rev. 0 12/02

0.20 (0.008)

C

D

END VIEW

NOTES:

1. These package dimensions are within allowable dimensions of

JEDEC MO-187BA.

2. Dimensioning and tolerancing per ANSI Y14.5M-1994.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs and are measured at Datum Plane. Mold flash, protrusion

and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions

- H -

and are measured at Datum Plane.

Interlead flash and

protrusions shall not exceed 0.15mm (0.006 inch) per side.

5. Formed leads shall be planar with respect to one another within

0.10mm (.004) at seating Plane.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable

dambar protrusion shall be 0.08mm (0.003 inch) total in excess

of “b” dimension at maximum material condition. Minimum space

between protrusion and adjacent lead is 0.07mm (0.0027 inch).

- B -

-A -

10. Datums

and

to be determined at Datum plane

.

- H -

11. Controlling dimension: MILLIMETER. Converted inch dimen-

sions are for reference only

FN7780.0

December 15, 2010

18

ISL23415

Package Outline Drawing

L10.2.1x1.6A

10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 5, 3/10

8.

PIN 1

INDEX AREA

2.10

A

PIN #1 ID

8.

0.05 MIN.

B

1

4

1

4X 0.20 MIN.

0.10 MIN.

10

5

0.80

10X 0.40

10 X 0.20

0.10

6

9

2X

6X 0.50

4

TOP VIEW

(10 X 0.20)

0.10 M C A B

M C

BOTTOM VIEW

SEE DETAIL "X"

(0.05 MIN)

(0.10 MIN.)

MAX. 0.55

PACKAGE

OUTLINE

1

0.10 C

C

(10X 0.60)

SEATING PLANE

0.08 C

(2.00)

SIDE VIEW

0 . 125 REF

(0.80)

(1.30)

C

(6X 0.50 )

(2.50)

0-0.05

TYPICAL RECOMMENDED LAND PATTERN

DETAIL "X"

NOTES:

1. Dimensioning and tolerancing conform to ASME Y14.5M-1994.

2. All Dimensions are in millimeters. Angles are in degrees.

Dimensions in ( ) for Reference Only.

3. Unless otherwise specified, tolerance : Decimal ± 0.05

4. Lead width dimension applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

5. Maximum package warpage is 0.05mm.

6. Maximum allowable burrs is 0.076mm in all directions.

7. Same as JEDEC MO-255UABD except:

No lead-pull-back, MIN. Package thickness = 0.45 not 0.50mm

Lead Length dim. = 0.45mm max. not 0.42mm.

8. The configuration of the pin #1 identifier is optional, but must be located within

the zone indicated. The pin #1 identifier may be either a mold or mark feature.

FN7780.0

December 15, 2010

19


型号：	ISL23415WFRUZ-TK
厂家：	Intersil
描述：	Single, Low Voltage Digitally Controlled Potentiometer (XDCP?) 单路低电压数字控制电位器（ XDCP ？）电位器
文件：	总19页 (文件大小：935K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISL23415WFRUZ-TK [INTERSIL]

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